mirror of https://github.com/PCSX2/pcsx2.git
coded the microVU opcode tables, this took me all-day to get right lol xD
git-svn-id: http://pcsx2.googlecode.com/svn/trunk@498 96395faa-99c1-11dd-bbfe-3dabce05a288
This commit is contained in:
parent
042e904a65
commit
c7deaad3c6
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@ -61,7 +61,7 @@ microVUt(void) mVUreset() {
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}
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}
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// Dynarec Cache
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// Dynarec Cache
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mVU->cache = SysMmapEx(mVU->cacheAddr, mVU->cacheSize, 0x10000000, "Micro VU");
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mVU->cache = SysMmapEx(mVU->cacheAddr, mVU->cacheSize, 0x10000000, (vuIndex ? "Micro VU1" : "Micro VU0"));
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if ( mVU->cache == NULL ) throw Exception::OutOfMemory(fmt_string( "microVU Error: failed to allocate recompiler memory! (addr: 0x%x)", params (u32)mVU->cache));
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if ( mVU->cache == NULL ) throw Exception::OutOfMemory(fmt_string( "microVU Error: failed to allocate recompiler memory! (addr: 0x%x)", params (u32)mVU->cache));
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// Other Variables
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// Other Variables
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@ -15,5 +15,83 @@
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* along with this program; if not, write to the Free Software
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
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*/
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*/
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#pragma once
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#include "PrecompiledHeader.h"
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#include "PrecompiledHeader.h"
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#include "microVU.h"
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#ifdef PCSX2_MICROVU
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//------------------------------------------------------------------
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// Micro VU Micromode Lower instructions
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//------------------------------------------------------------------
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microVUf(void) mVU_DIV(){}
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microVUf(void) mVU_SQRT(){}
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microVUf(void) mVU_RSQRT(){}
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microVUf(void) mVU_IADD(){}
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microVUf(void) mVU_IADDI(){}
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microVUf(void) mVU_IADDIU(){}
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microVUf(void) mVU_IAND(){}
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microVUf(void) mVU_IOR(){}
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microVUf(void) mVU_ISUB(){}
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microVUf(void) mVU_ISUBIU(){}
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microVUf(void) mVU_MOVE(){}
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microVUf(void) mVU_MFIR(){}
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microVUf(void) mVU_MTIR(){}
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microVUf(void) mVU_MR32(){}
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microVUf(void) mVU_LQ(){}
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microVUf(void) mVU_LQD(){}
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microVUf(void) mVU_LQI(){}
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microVUf(void) mVU_SQ(){}
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microVUf(void) mVU_SQD(){}
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microVUf(void) mVU_SQI(){}
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microVUf(void) mVU_ILW(){}
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microVUf(void) mVU_ISW(){}
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microVUf(void) mVU_ILWR(){}
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microVUf(void) mVU_ISWR(){}
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microVUf(void) mVU_LOI(){}
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microVUf(void) mVU_RINIT(){}
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microVUf(void) mVU_RGET(){}
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microVUf(void) mVU_RNEXT(){}
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microVUf(void) mVU_RXOR(){}
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microVUf(void) mVU_WAITQ(){}
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microVUf(void) mVU_FSAND(){}
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microVUf(void) mVU_FSEQ(){}
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microVUf(void) mVU_FSOR(){}
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microVUf(void) mVU_FSSET(){}
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microVUf(void) mVU_FMAND(){}
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microVUf(void) mVU_FMEQ(){}
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microVUf(void) mVU_FMOR(){}
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microVUf(void) mVU_FCAND(){}
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microVUf(void) mVU_FCEQ(){}
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microVUf(void) mVU_FCOR(){}
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microVUf(void) mVU_FCSET(){}
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microVUf(void) mVU_FCGET(){}
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microVUf(void) mVU_IBEQ(){}
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microVUf(void) mVU_IBGEZ(){}
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microVUf(void) mVU_IBGTZ(){}
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microVUf(void) mVU_IBLTZ(){}
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microVUf(void) mVU_IBLEZ(){}
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microVUf(void) mVU_IBNE(){}
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microVUf(void) mVU_B(){}
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microVUf(void) mVU_BAL(){}
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microVUf(void) mVU_JR(){}
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microVUf(void) mVU_JALR(){}
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microVUf(void) mVU_MFP(){}
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microVUf(void) mVU_WAITP(){}
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microVUf(void) mVU_ESADD(){}
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microVUf(void) mVU_ERSADD(){}
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microVUf(void) mVU_ELENG(){}
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microVUf(void) mVU_ERLENG(){}
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microVUf(void) mVU_EATANxy(){}
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microVUf(void) mVU_EATANxz(){}
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microVUf(void) mVU_ESUM(){}
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microVUf(void) mVU_ERCPR(){}
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microVUf(void) mVU_ESQRT(){}
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microVUf(void) mVU_ERSQRT(){}
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microVUf(void) mVU_ESIN(){}
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microVUf(void) mVU_EATAN(){}
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microVUf(void) mVU_EEXP(){}
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microVUf(void) mVU_XGKICK(){}
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microVUf(void) mVU_XTOP(){}
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microVUf(void) mVU_XITOP(){}
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#endif //PCSX2_MICROVU
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@ -18,210 +18,741 @@
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#include "PrecompiledHeader.h"
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#include "PrecompiledHeader.h"
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#include "microVU.h"
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#include "microVU.h"
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#include "microVU_Upper.cpp"
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#include "microVU_Lower.cpp"
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#ifdef PCSX2_MICROVU_lulz
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#ifdef PCSX2_MICROVU
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void mVU_UPPER_FD_00(VURegs* VU, s32 info);
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//------------------------------------------------------------------
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void mVU_UPPER_FD_01(VURegs* VU, s32 info);
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// Declarations
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void mVU_UPPER_FD_10(VURegs* VU, s32 info);
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//------------------------------------------------------------------
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void mVU_UPPER_FD_11(VURegs* VU, s32 info);
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extern PCSX2_ALIGNED16(microVU microVU0);
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void mVULowerOP(VURegs* VU, s32 info);
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extern PCSX2_ALIGNED16(microVU microVU1);
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void mVULowerOP_T3_00(VURegs* VU, s32 info);
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void mVULowerOP_T3_01(VURegs* VU, s32 info);
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void mVULowerOP_T3_10(VURegs* VU, s32 info);
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void mVULowerOP_T3_11(VURegs* VU, s32 info);
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void mVUunknown(VURegs* VU, s32 info);
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void (*mVU_LOWER_OPCODE[128])(VURegs* VU, s32 info) = {
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#define mVUgetCode (vuIndex ? microVU1.regs->code : microVU0.regs->code)
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mVU_LQ , mVU_SQ , mVUunknown , mVUunknown,
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mVU_ILW , mVU_ISW , mVUunknown , mVUunknown,
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mVU_IADDIU , mVU_ISUBIU , mVUunknown , mVUunknown,
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mVUunknown , mVUunknown , mVUunknown , mVUunknown,
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mVU_FCEQ , mVU_FCSET , mVU_FCAND , mVU_FCOR, /* 0x10 */
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mVU_FSEQ , mVU_FSSET , mVU_FSAND , mVU_FSOR,
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mVU_FMEQ , mVUunknown , mVU_FMAND , mVU_FMOR,
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mVU_FCGET , mVUunknown , mVUunknown , mVUunknown,
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mVU_B , mVU_BAL , mVUunknown , mVUunknown, /* 0x20 */
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mVU_JR , mVU_JALR , mVUunknown , mVUunknown,
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mVU_IBEQ , mVU_IBNE , mVUunknown , mVUunknown,
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mVU_IBLTZ , mVU_IBGTZ , mVU_IBLEZ , mVU_IBGEZ,
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mVUunknown , mVUunknown , mVUunknown , mVUunknown, /* 0x30 */
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mVUunknown , mVUunknown , mVUunknown , mVUunknown,
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mVUunknown , mVUunknown , mVUunknown , mVUunknown,
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mVUunknown , mVUunknown , mVUunknown , mVUunknown,
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mVULowerOP , mVUunknown , mVUunknown , mVUunknown, /* 0x40*/
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mVUunknown , mVUunknown , mVUunknown , mVUunknown,
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mVUunknown , mVUunknown , mVUunknown , mVUunknown,
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mVUunknown , mVUunknown , mVUunknown , mVUunknown,
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mVUunknown , mVUunknown , mVUunknown , mVUunknown, /* 0x50 */
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mVUunknown , mVUunknown , mVUunknown , mVUunknown,
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mVUunknown , mVUunknown , mVUunknown , mVUunknown,
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mVUunknown , mVUunknown , mVUunknown , mVUunknown,
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mVUunknown , mVUunknown , mVUunknown , mVUunknown, /* 0x60 */
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mVUunknown , mVUunknown , mVUunknown , mVUunknown,
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mVUunknown , mVUunknown , mVUunknown , mVUunknown,
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mVUunknown , mVUunknown , mVUunknown , mVUunknown,
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mVUunknown , mVUunknown , mVUunknown , mVUunknown, /* 0x70 */
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mVUunknown , mVUunknown , mVUunknown , mVUunknown,
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mVUunknown , mVUunknown , mVUunknown , mVUunknown,
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mVUunknown , mVUunknown , mVUunknown , mVUunknown,
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};
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void (*mVULowerOP_T3_00_OPCODE[32])(VURegs* VU, s32 info) = {
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microVUf(void) mVU_UPPER_FD_00();
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mVUunknown , mVUunknown , mVUunknown , mVUunknown,
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microVUf(void) mVU_UPPER_FD_01();
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mVUunknown , mVUunknown , mVUunknown , mVUunknown,
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microVUf(void) mVU_UPPER_FD_10();
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mVUunknown , mVUunknown , mVUunknown , mVUunknown,
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microVUf(void) mVU_UPPER_FD_11();
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mVU_MOVE , mVU_LQI , mVU_DIV , mVU_MTIR,
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microVUf(void) mVULowerOP();
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mVU_RNEXT , mVUunknown , mVUunknown , mVUunknown, /* 0x10 */
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microVUf(void) mVULowerOP_T3_00();
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mVUunknown , mVUunknown , mVUunknown , mVUunknown,
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microVUf(void) mVULowerOP_T3_01();
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mVUunknown , mVU_MFP , mVU_XTOP , mVU_XGKICK,
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microVUf(void) mVULowerOP_T3_10();
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mVU_ESADD , mVU_EATANxy , mVU_ESQRT , mVU_ESIN,
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microVUf(void) mVULowerOP_T3_11();
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};
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microVUf(void) mVUunknown();
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//------------------------------------------------------------------
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void (*mVULowerOP_T3_01_OPCODE[32])(VURegs* VU, s32 info) = {
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//------------------------------------------------------------------
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mVUunknown , mVUunknown , mVUunknown , mVUunknown,
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// mVULOWER_OPCODE
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mVUunknown , mVUunknown , mVUunknown , mVUunknown,
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//------------------------------------------------------------------
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mVUunknown , mVUunknown , mVUunknown , mVUunknown,
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void (* mVULOWER_OPCODE00 [128])() = {
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mVU_MR32 , mVU_SQI , mVU_SQRT , mVU_MFIR,
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mVU_LQ<0,0> , mVU_SQ<0,0> , mVUunknown<0,0> , mVUunknown<0,0>,
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mVU_RGET , mVUunknown , mVUunknown , mVUunknown, /* 0x10 */
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mVU_ILW<0,0> , mVU_ISW<0,0> , mVUunknown<0,0> , mVUunknown<0,0>,
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mVUunknown , mVUunknown , mVUunknown , mVUunknown,
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mVU_IADDIU<0,0> , mVU_ISUBIU<0,0> , mVUunknown<0,0> , mVUunknown<0,0>,
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mVUunknown , mVUunknown , mVU_XITOP , mVUunknown,
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mVUunknown<0,0> , mVUunknown<0,0> , mVUunknown<0,0> , mVUunknown<0,0>,
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mVU_ERSADD , mVU_EATANxz , mVU_ERSQRT , mVU_EATAN,
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mVU_FCEQ<0,0> , mVU_FCSET<0,0> , mVU_FCAND<0,0> , mVU_FCOR<0,0>, /* 0x10 */
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};
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mVU_FSEQ<0,0> , mVU_FSSET<0,0> , mVU_FSAND<0,0> , mVU_FSOR<0,0>,
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mVU_FMEQ<0,0> , mVUunknown<0,0> , mVU_FMAND<0,0> , mVU_FMOR<0,0>,
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mVU_FCGET<0,0> , mVUunknown<0,0> , mVUunknown<0,0> , mVUunknown<0,0>,
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mVU_B<0,0> , mVU_BAL<0,0> , mVUunknown<0,0> , mVUunknown<0,0>, /* 0x20 */
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mVU_JR<0,0> , mVU_JALR<0,0> , mVUunknown<0,0> , mVUunknown<0,0>,
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mVU_IBEQ<0,0> , mVU_IBNE<0,0> , mVUunknown<0,0> , mVUunknown<0,0>,
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mVU_IBLTZ<0,0> , mVU_IBGTZ<0,0> , mVU_IBLEZ<0,0> , mVU_IBGEZ<0,0>,
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mVUunknown<0,0> , mVUunknown<0,0> , mVUunknown<0,0> , mVUunknown<0,0>, /* 0x30 */
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mVUunknown<0,0> , mVUunknown<0,0> , mVUunknown<0,0> , mVUunknown<0,0>,
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mVUunknown<0,0> , mVUunknown<0,0> , mVUunknown<0,0> , mVUunknown<0,0>,
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mVUunknown<0,0> , mVUunknown<0,0> , mVUunknown<0,0> , mVUunknown<0,0>,
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mVULowerOP<0,0> , mVUunknown<0,0> , mVUunknown<0,0> , mVUunknown<0,0>, /* 0x40*/
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mVUunknown<0,0> , mVUunknown<0,0> , mVUunknown<0,0> , mVUunknown<0,0>,
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mVUunknown<0,0> , mVUunknown<0,0> , mVUunknown<0,0> , mVUunknown<0,0>,
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mVUunknown<0,0> , mVUunknown<0,0> , mVUunknown<0,0> , mVUunknown<0,0>,
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mVUunknown<0,0> , mVUunknown<0,0> , mVUunknown<0,0> , mVUunknown<0,0>, /* 0x50 */
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mVUunknown<0,0> , mVUunknown<0,0> , mVUunknown<0,0> , mVUunknown<0,0>,
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mVUunknown<0,0> , mVUunknown<0,0> , mVUunknown<0,0> , mVUunknown<0,0>,
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mVUunknown<0,0> , mVUunknown<0,0> , mVUunknown<0,0> , mVUunknown<0,0>,
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mVUunknown<0,0> , mVUunknown<0,0> , mVUunknown<0,0> , mVUunknown<0,0>, /* 0x60 */
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mVUunknown<0,0> , mVUunknown<0,0> , mVUunknown<0,0> , mVUunknown<0,0>,
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mVUunknown<0,0> , mVUunknown<0,0> , mVUunknown<0,0> , mVUunknown<0,0>,
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mVUunknown<0,0> , mVUunknown<0,0> , mVUunknown<0,0> , mVUunknown<0,0>,
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mVUunknown<0,0> , mVUunknown<0,0> , mVUunknown<0,0> , mVUunknown<0,0>, /* 0x70 */
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mVUunknown<0,0> , mVUunknown<0,0> , mVUunknown<0,0> , mVUunknown<0,0>,
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mVUunknown<0,0> , mVUunknown<0,0> , mVUunknown<0,0> , mVUunknown<0,0>,
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mVUunknown<0,0> , mVUunknown<0,0> , mVUunknown<0,0> , mVUunknown<0,0>,
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};
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void (*mVULowerOP_T3_10_OPCODE[32])(VURegs* VU, s32 info) = {
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void (* mVULOWER_OPCODE01 [128])() = {
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mVUunknown , mVUunknown , mVUunknown , mVUunknown,
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mVU_LQ<0,1> , mVU_SQ<0,1> , mVUunknown<0,1> , mVUunknown<0,1>,
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mVUunknown , mVUunknown , mVUunknown , mVUunknown,
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mVU_ILW<0,1> , mVU_ISW<0,1> , mVUunknown<0,1> , mVUunknown<0,1>,
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mVUunknown , mVUunknown , mVUunknown , mVUunknown,
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mVU_IADDIU<0,1> , mVU_ISUBIU<0,1> , mVUunknown<0,1> , mVUunknown<0,1>,
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mVUunknown , mVU_LQD , mVU_RSQRT , mVU_ILWR,
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mVUunknown<0,1> , mVUunknown<0,1> , mVUunknown<0,1> , mVUunknown<0,1>,
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mVU_RINIT , mVUunknown , mVUunknown , mVUunknown, /* 0x10 */
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mVU_FCEQ<0,1> , mVU_FCSET<0,1> , mVU_FCAND<0,1> , mVU_FCOR<0,1>, /* 0x10 */
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mVUunknown , mVUunknown , mVUunknown , mVUunknown,
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mVU_FSEQ<0,1> , mVU_FSSET<0,1> , mVU_FSAND<0,1> , mVU_FSOR<0,1>,
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mVUunknown , mVUunknown , mVUunknown , mVUunknown,
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mVU_FMEQ<0,1> , mVUunknown<0,1> , mVU_FMAND<0,1> , mVU_FMOR<0,1>,
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mVU_ELENG , mVU_ESUM , mVU_ERCPR , mVU_EEXP,
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mVU_FCGET<0,1> , mVUunknown<0,1> , mVUunknown<0,1> , mVUunknown<0,1>,
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};
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mVU_B<0,1> , mVU_BAL<0,1> , mVUunknown<0,1> , mVUunknown<0,1>, /* 0x20 */
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mVU_JR<0,1> , mVU_JALR<0,1> , mVUunknown<0,1> , mVUunknown<0,1>,
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mVU_IBEQ<0,1> , mVU_IBNE<0,1> , mVUunknown<0,1> , mVUunknown<0,1>,
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mVU_IBLTZ<0,1> , mVU_IBGTZ<0,1> , mVU_IBLEZ<0,1> , mVU_IBGEZ<0,1>,
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mVUunknown<0,1> , mVUunknown<0,1> , mVUunknown<0,1> , mVUunknown<0,1>, /* 0x30 */
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mVUunknown<0,1> , mVUunknown<0,1> , mVUunknown<0,1> , mVUunknown<0,1>,
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mVUunknown<0,1> , mVUunknown<0,1> , mVUunknown<0,1> , mVUunknown<0,1>,
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mVUunknown<0,1> , mVUunknown<0,1> , mVUunknown<0,1> , mVUunknown<0,1>,
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mVULowerOP<0,1> , mVUunknown<0,1> , mVUunknown<0,1> , mVUunknown<0,1>, /* 0x40*/
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mVUunknown<0,1> , mVUunknown<0,1> , mVUunknown<0,1> , mVUunknown<0,1>,
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mVUunknown<0,1> , mVUunknown<0,1> , mVUunknown<0,1> , mVUunknown<0,1>,
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||||||
|
mVUunknown<0,1> , mVUunknown<0,1> , mVUunknown<0,1> , mVUunknown<0,1>,
|
||||||
|
mVUunknown<0,1> , mVUunknown<0,1> , mVUunknown<0,1> , mVUunknown<0,1>, /* 0x50 */
|
||||||
|
mVUunknown<0,1> , mVUunknown<0,1> , mVUunknown<0,1> , mVUunknown<0,1>,
|
||||||
|
mVUunknown<0,1> , mVUunknown<0,1> , mVUunknown<0,1> , mVUunknown<0,1>,
|
||||||
|
mVUunknown<0,1> , mVUunknown<0,1> , mVUunknown<0,1> , mVUunknown<0,1>,
|
||||||
|
mVUunknown<0,1> , mVUunknown<0,1> , mVUunknown<0,1> , mVUunknown<0,1>, /* 0x60 */
|
||||||
|
mVUunknown<0,1> , mVUunknown<0,1> , mVUunknown<0,1> , mVUunknown<0,1>,
|
||||||
|
mVUunknown<0,1> , mVUunknown<0,1> , mVUunknown<0,1> , mVUunknown<0,1>,
|
||||||
|
mVUunknown<0,1> , mVUunknown<0,1> , mVUunknown<0,1> , mVUunknown<0,1>,
|
||||||
|
mVUunknown<0,1> , mVUunknown<0,1> , mVUunknown<0,1> , mVUunknown<0,1>, /* 0x70 */
|
||||||
|
mVUunknown<0,1> , mVUunknown<0,1> , mVUunknown<0,1> , mVUunknown<0,1>,
|
||||||
|
mVUunknown<0,1> , mVUunknown<0,1> , mVUunknown<0,1> , mVUunknown<0,1>,
|
||||||
|
mVUunknown<0,1> , mVUunknown<0,1> , mVUunknown<0,1> , mVUunknown<0,1>,
|
||||||
|
};
|
||||||
|
|
||||||
void (*mVULowerOP_T3_11_OPCODE[32])(VURegs* VU, s32 info) = {
|
void (* mVULOWER_OPCODE10 [128])() = {
|
||||||
mVUunknown , mVUunknown , mVUunknown , mVUunknown,
|
mVU_LQ<1,0> , mVU_SQ<1,0> , mVUunknown<1,0> , mVUunknown<1,0>,
|
||||||
mVUunknown , mVUunknown , mVUunknown , mVUunknown,
|
mVU_ILW<1,0> , mVU_ISW<1,0> , mVUunknown<1,0> , mVUunknown<1,0>,
|
||||||
mVUunknown , mVUunknown , mVUunknown , mVUunknown,
|
mVU_IADDIU<1,0> , mVU_ISUBIU<1,0> , mVUunknown<1,0> , mVUunknown<1,0>,
|
||||||
mVUunknown , mVU_SQD , mVU_WAITQ , mVU_ISWR,
|
mVUunknown<1,0> , mVUunknown<1,0> , mVUunknown<1,0> , mVUunknown<1,0>,
|
||||||
mVU_RXOR , mVUunknown , mVUunknown , mVUunknown, /* 0x10 */
|
mVU_FCEQ<1,0> , mVU_FCSET<1,0> , mVU_FCAND<1,0> , mVU_FCOR<1,0>, /* 0x10 */
|
||||||
mVUunknown , mVUunknown , mVUunknown , mVUunknown,
|
mVU_FSEQ<1,0> , mVU_FSSET<1,0> , mVU_FSAND<1,0> , mVU_FSOR<1,0>,
|
||||||
mVUunknown , mVUunknown , mVUunknown , mVUunknown,
|
mVU_FMEQ<1,0> , mVUunknown<1,0> , mVU_FMAND<1,0> , mVU_FMOR<1,0>,
|
||||||
mVU_ERLENG , mVUunknown , mVU_WAITP , mVUunknown,
|
mVU_FCGET<1,0> , mVUunknown<1,0> , mVUunknown<1,0> , mVUunknown<1,0>,
|
||||||
};
|
mVU_B<1,0> , mVU_BAL<1,0> , mVUunknown<1,0> , mVUunknown<1,0>, /* 0x20 */
|
||||||
|
mVU_JR<1,0> , mVU_JALR<1,0> , mVUunknown<1,0> , mVUunknown<1,0>,
|
||||||
|
mVU_IBEQ<1,0> , mVU_IBNE<1,0> , mVUunknown<1,0> , mVUunknown<1,0>,
|
||||||
|
mVU_IBLTZ<1,0> , mVU_IBGTZ<1,0> , mVU_IBLEZ<1,0> , mVU_IBGEZ<1,0>,
|
||||||
|
mVUunknown<1,0> , mVUunknown<1,0> , mVUunknown<1,0> , mVUunknown<1,0>, /* 0x30 */
|
||||||
|
mVUunknown<1,0> , mVUunknown<1,0> , mVUunknown<1,0> , mVUunknown<1,0>,
|
||||||
|
mVUunknown<1,0> , mVUunknown<1,0> , mVUunknown<1,0> , mVUunknown<1,0>,
|
||||||
|
mVUunknown<1,0> , mVUunknown<1,0> , mVUunknown<1,0> , mVUunknown<1,0>,
|
||||||
|
mVULowerOP<1,0> , mVUunknown<1,0> , mVUunknown<1,0> , mVUunknown<1,0>, /* 0x40*/
|
||||||
|
mVUunknown<1,0> , mVUunknown<1,0> , mVUunknown<1,0> , mVUunknown<1,0>,
|
||||||
|
mVUunknown<1,0> , mVUunknown<1,0> , mVUunknown<1,0> , mVUunknown<1,0>,
|
||||||
|
mVUunknown<1,0> , mVUunknown<1,0> , mVUunknown<1,0> , mVUunknown<1,0>,
|
||||||
|
mVUunknown<1,0> , mVUunknown<1,0> , mVUunknown<1,0> , mVUunknown<1,0>, /* 0x50 */
|
||||||
|
mVUunknown<1,0> , mVUunknown<1,0> , mVUunknown<1,0> , mVUunknown<1,0>,
|
||||||
|
mVUunknown<1,0> , mVUunknown<1,0> , mVUunknown<1,0> , mVUunknown<1,0>,
|
||||||
|
mVUunknown<1,0> , mVUunknown<1,0> , mVUunknown<1,0> , mVUunknown<1,0>,
|
||||||
|
mVUunknown<1,0> , mVUunknown<1,0> , mVUunknown<1,0> , mVUunknown<1,0>, /* 0x60 */
|
||||||
|
mVUunknown<1,0> , mVUunknown<1,0> , mVUunknown<1,0> , mVUunknown<1,0>,
|
||||||
|
mVUunknown<1,0> , mVUunknown<1,0> , mVUunknown<1,0> , mVUunknown<1,0>,
|
||||||
|
mVUunknown<1,0> , mVUunknown<1,0> , mVUunknown<1,0> , mVUunknown<1,0>,
|
||||||
|
mVUunknown<1,0> , mVUunknown<1,0> , mVUunknown<1,0> , mVUunknown<1,0>, /* 0x70 */
|
||||||
|
mVUunknown<1,0> , mVUunknown<1,0> , mVUunknown<1,0> , mVUunknown<1,0>,
|
||||||
|
mVUunknown<1,0> , mVUunknown<1,0> , mVUunknown<1,0> , mVUunknown<1,0>,
|
||||||
|
mVUunknown<1,0> , mVUunknown<1,0> , mVUunknown<1,0> , mVUunknown<1,0>,
|
||||||
|
};
|
||||||
|
|
||||||
void (*mVULowerOP_OPCODE[64])(VURegs* VU, s32 info) = {
|
void (* mVULOWER_OPCODE11 [128])() = {
|
||||||
mVUunknown , mVUunknown , mVUunknown , mVUunknown,
|
mVU_LQ<1,1> , mVU_SQ<1,1> , mVUunknown<1,1> , mVUunknown<1,1>,
|
||||||
mVUunknown , mVUunknown , mVUunknown , mVUunknown,
|
mVU_ILW<1,1> , mVU_ISW<1,1> , mVUunknown<1,1> , mVUunknown<1,1>,
|
||||||
mVUunknown , mVUunknown , mVUunknown , mVUunknown,
|
mVU_IADDIU<1,1> , mVU_ISUBIU<1,1> , mVUunknown<1,1> , mVUunknown<1,1>,
|
||||||
mVUunknown , mVUunknown , mVUunknown , mVUunknown,
|
mVUunknown<1,1> , mVUunknown<1,1> , mVUunknown<1,1> , mVUunknown<1,1>,
|
||||||
mVUunknown , mVUunknown , mVUunknown , mVUunknown, /* 0x10 */
|
mVU_FCEQ<1,1> , mVU_FCSET<1,1> , mVU_FCAND<1,1> , mVU_FCOR<1,1>, /* 0x10 */
|
||||||
mVUunknown , mVUunknown , mVUunknown , mVUunknown,
|
mVU_FSEQ<1,1> , mVU_FSSET<1,1> , mVU_FSAND<1,1> , mVU_FSOR<1,1>,
|
||||||
mVUunknown , mVUunknown , mVUunknown , mVUunknown,
|
mVU_FMEQ<1,1> , mVUunknown<1,1> , mVU_FMAND<1,1> , mVU_FMOR<1,1>,
|
||||||
mVUunknown , mVUunknown , mVUunknown , mVUunknown,
|
mVU_FCGET<1,1> , mVUunknown<1,1> , mVUunknown<1,1> , mVUunknown<1,1>,
|
||||||
mVUunknown , mVUunknown , mVUunknown , mVUunknown, /* 0x20 */
|
mVU_B<1,1> , mVU_BAL<1,1> , mVUunknown<1,1> , mVUunknown<1,1>, /* 0x20 */
|
||||||
mVUunknown , mVUunknown , mVUunknown , mVUunknown,
|
mVU_JR<1,1> , mVU_JALR<1,1> , mVUunknown<1,1> , mVUunknown<1,1>,
|
||||||
mVUunknown , mVUunknown , mVUunknown , mVUunknown,
|
mVU_IBEQ<1,1> , mVU_IBNE<1,1> , mVUunknown<1,1> , mVUunknown<1,1>,
|
||||||
mVUunknown , mVUunknown , mVUunknown , mVUunknown,
|
mVU_IBLTZ<1,1> , mVU_IBGTZ<1,1> , mVU_IBLEZ<1,1> , mVU_IBGEZ<1,1>,
|
||||||
mVU_IADD , mVU_ISUB , mVU_IADDI , mVUunknown, /* 0x30 */
|
mVUunknown<1,1> , mVUunknown<1,1> , mVUunknown<1,1> , mVUunknown<1,1>, /* 0x30 */
|
||||||
mVU_IAND , mVU_IOR , mVUunknown , mVUunknown,
|
mVUunknown<1,1> , mVUunknown<1,1> , mVUunknown<1,1> , mVUunknown<1,1>,
|
||||||
mVUunknown , mVUunknown , mVUunknown , mVUunknown,
|
mVUunknown<1,1> , mVUunknown<1,1> , mVUunknown<1,1> , mVUunknown<1,1>,
|
||||||
mVULowerOP_T3_00, mVULowerOP_T3_01, mVULowerOP_T3_10, mVULowerOP_T3_11,
|
mVUunknown<1,1> , mVUunknown<1,1> , mVUunknown<1,1> , mVUunknown<1,1>,
|
||||||
};
|
mVULowerOP<1,1> , mVUunknown<1,1> , mVUunknown<1,1> , mVUunknown<1,1>, /* 0x40*/
|
||||||
|
mVUunknown<1,1> , mVUunknown<1,1> , mVUunknown<1,1> , mVUunknown<1,1>,
|
||||||
|
mVUunknown<1,1> , mVUunknown<1,1> , mVUunknown<1,1> , mVUunknown<1,1>,
|
||||||
|
mVUunknown<1,1> , mVUunknown<1,1> , mVUunknown<1,1> , mVUunknown<1,1>,
|
||||||
|
mVUunknown<1,1> , mVUunknown<1,1> , mVUunknown<1,1> , mVUunknown<1,1>, /* 0x50 */
|
||||||
|
mVUunknown<1,1> , mVUunknown<1,1> , mVUunknown<1,1> , mVUunknown<1,1>,
|
||||||
|
mVUunknown<1,1> , mVUunknown<1,1> , mVUunknown<1,1> , mVUunknown<1,1>,
|
||||||
|
mVUunknown<1,1> , mVUunknown<1,1> , mVUunknown<1,1> , mVUunknown<1,1>,
|
||||||
|
mVUunknown<1,1> , mVUunknown<1,1> , mVUunknown<1,1> , mVUunknown<1,1>, /* 0x60 */
|
||||||
|
mVUunknown<1,1> , mVUunknown<1,1> , mVUunknown<1,1> , mVUunknown<1,1>,
|
||||||
|
mVUunknown<1,1> , mVUunknown<1,1> , mVUunknown<1,1> , mVUunknown<1,1>,
|
||||||
|
mVUunknown<1,1> , mVUunknown<1,1> , mVUunknown<1,1> , mVUunknown<1,1>,
|
||||||
|
mVUunknown<1,1> , mVUunknown<1,1> , mVUunknown<1,1> , mVUunknown<1,1>, /* 0x70 */
|
||||||
|
mVUunknown<1,1> , mVUunknown<1,1> , mVUunknown<1,1> , mVUunknown<1,1>,
|
||||||
|
mVUunknown<1,1> , mVUunknown<1,1> , mVUunknown<1,1> , mVUunknown<1,1>,
|
||||||
|
mVUunknown<1,1> , mVUunknown<1,1> , mVUunknown<1,1> , mVUunknown<1,1>,
|
||||||
|
};
|
||||||
|
//------------------------------------------------------------------
|
||||||
|
|
||||||
void (*mVU_UPPER_OPCODE[64])(VURegs* VU, s32 info) = {
|
//------------------------------------------------------------------
|
||||||
mVU_ADDx , mVU_ADDy , mVU_ADDz , mVU_ADDw,
|
// mVULowerOP_T3_00_OPCODE
|
||||||
mVU_SUBx , mVU_SUBy , mVU_SUBz , mVU_SUBw,
|
//------------------------------------------------------------------
|
||||||
mVU_MADDx , mVU_MADDy , mVU_MADDz , mVU_MADDw,
|
void (* mVULowerOP_T3_00_OPCODE00 [32])() = {
|
||||||
mVU_MSUBx , mVU_MSUBy , mVU_MSUBz , mVU_MSUBw,
|
mVUunknown<0,0> , mVUunknown<0,0> , mVUunknown<0,0> , mVUunknown<0,0>,
|
||||||
mVU_MAXx , mVU_MAXy , mVU_MAXz , mVU_MAXw, /* 0x10 */
|
mVUunknown<0,0> , mVUunknown<0,0> , mVUunknown<0,0> , mVUunknown<0,0>,
|
||||||
mVU_MINIx , mVU_MINIy , mVU_MINIz , mVU_MINIw,
|
mVUunknown<0,0> , mVUunknown<0,0> , mVUunknown<0,0> , mVUunknown<0,0>,
|
||||||
mVU_MULx , mVU_MULy , mVU_MULz , mVU_MULw,
|
mVU_MOVE<0,0> , mVU_LQI<0,0> , mVU_DIV<0,0> , mVU_MTIR<0,0>,
|
||||||
mVU_MULq , mVU_MAXi , mVU_MULi , mVU_MINIi,
|
mVU_RNEXT<0,0> , mVUunknown<0,0> , mVUunknown<0,0> , mVUunknown<0,0>, /* 0x10 */
|
||||||
mVU_ADDq , mVU_MADDq , mVU_ADDi , mVU_MADDi, /* 0x20 */
|
mVUunknown<0,0> , mVUunknown<0,0> , mVUunknown<0,0> , mVUunknown<0,0>,
|
||||||
mVU_SUBq , mVU_MSUBq , mVU_SUBi , mVU_MSUBi,
|
mVUunknown<0,0> , mVU_MFP<0,0> , mVU_XTOP<0,0> , mVU_XGKICK<0,0>,
|
||||||
mVU_ADD , mVU_MADD , mVU_MUL , mVU_MAX,
|
mVU_ESADD<0,0> , mVU_EATANxy<0,0> , mVU_ESQRT<0,0> , mVU_ESIN<0,0>,
|
||||||
mVU_SUB , mVU_MSUB , mVU_OPMSUB , mVU_MINI,
|
};
|
||||||
mVUunknown , mVUunknown , mVUunknown , mVUunknown, /* 0x30 */
|
|
||||||
mVUunknown , mVUunknown , mVUunknown , mVUunknown,
|
|
||||||
mVUunknown , mVUunknown , mVUunknown , mVUunknown,
|
|
||||||
mVU_UPPER_FD_00, mVU_UPPER_FD_01, mVU_UPPER_FD_10, mVU_UPPER_FD_11,
|
|
||||||
};
|
|
||||||
|
|
||||||
void (*mVU_UPPER_FD_00_TABLE[32])(VURegs* VU, s32 info) = {
|
void (* mVULowerOP_T3_00_OPCODE01 [32])() = {
|
||||||
mVU_ADDAx , mVU_SUBAx , mVU_MADDAx , mVU_MSUBAx,
|
mVUunknown<0,1> , mVUunknown<0,1> , mVUunknown<0,1> , mVUunknown<0,1>,
|
||||||
mVU_ITOF0 , mVU_FTOI0 , mVU_MULAx , mVU_MULAq,
|
mVUunknown<0,1> , mVUunknown<0,1> , mVUunknown<0,1> , mVUunknown<0,1>,
|
||||||
mVU_ADDAq , mVU_SUBAq , mVU_ADDA , mVU_SUBA,
|
mVUunknown<0,1> , mVUunknown<0,1> , mVUunknown<0,1> , mVUunknown<0,1>,
|
||||||
mVUunknown , mVUunknown , mVUunknown , mVUunknown,
|
mVU_MOVE<0,1> , mVU_LQI<0,1> , mVU_DIV<0,1> , mVU_MTIR<0,1>,
|
||||||
mVUunknown , mVUunknown , mVUunknown , mVUunknown,
|
mVU_RNEXT<0,1> , mVUunknown<0,1> , mVUunknown<0,1> , mVUunknown<0,1>, /* 0x10 */
|
||||||
mVUunknown , mVUunknown , mVUunknown , mVUunknown,
|
mVUunknown<0,1> , mVUunknown<0,1> , mVUunknown<0,1> , mVUunknown<0,1>,
|
||||||
mVUunknown , mVUunknown , mVUunknown , mVUunknown,
|
mVUunknown<0,1> , mVU_MFP<0,1> , mVU_XTOP<0,1> , mVU_XGKICK<0,1>,
|
||||||
mVUunknown , mVUunknown , mVUunknown , mVUunknown,
|
mVU_ESADD<0,1> , mVU_EATANxy<0,1> , mVU_ESQRT<0,1> , mVU_ESIN<0,1>,
|
||||||
};
|
};
|
||||||
|
|
||||||
void (*mVU_UPPER_FD_01_TABLE[32])(VURegs* VU, s32 info) = {
|
void (* mVULowerOP_T3_00_OPCODE10 [32])() = {
|
||||||
mVU_ADDAy , mVU_SUBAy , mVU_MADDAy , mVU_MSUBAy,
|
mVUunknown<1,0> , mVUunknown<1,0> , mVUunknown<1,0> , mVUunknown<1,0>,
|
||||||
mVU_ITOF4 , mVU_FTOI4 , mVU_MULAy , mVU_ABS,
|
mVUunknown<1,0> , mVUunknown<1,0> , mVUunknown<1,0> , mVUunknown<1,0>,
|
||||||
mVU_MADDAq , mVU_MSUBAq , mVU_MADDA , mVU_MSUBA,
|
mVUunknown<1,0> , mVUunknown<1,0> , mVUunknown<1,0> , mVUunknown<1,0>,
|
||||||
mVUunknown , mVUunknown , mVUunknown , mVUunknown,
|
mVU_MOVE<1,0> , mVU_LQI<1,0> , mVU_DIV<1,0> , mVU_MTIR<1,0>,
|
||||||
mVUunknown , mVUunknown , mVUunknown , mVUunknown,
|
mVU_RNEXT<1,0> , mVUunknown<1,0> , mVUunknown<1,0> , mVUunknown<1,0>, /* 0x10 */
|
||||||
mVUunknown , mVUunknown , mVUunknown , mVUunknown,
|
mVUunknown<1,0> , mVUunknown<1,0> , mVUunknown<1,0> , mVUunknown<1,0>,
|
||||||
mVUunknown , mVUunknown , mVUunknown , mVUunknown,
|
mVUunknown<1,0> , mVU_MFP<1,0> , mVU_XTOP<1,0> , mVU_XGKICK<1,0>,
|
||||||
mVUunknown , mVUunknown , mVUunknown , mVUunknown,
|
mVU_ESADD<1,0> , mVU_EATANxy<1,0> , mVU_ESQRT<1,0> , mVU_ESIN<1,0>,
|
||||||
};
|
};
|
||||||
|
|
||||||
void (*mVU_UPPER_FD_10_TABLE[32])(VURegs* VU, s32 info) = {
|
void (* mVULowerOP_T3_00_OPCODE11 [32])() = {
|
||||||
mVU_ADDAz , mVU_SUBAz , mVU_MADDAz , mVU_MSUBAz,
|
mVUunknown<1,1> , mVUunknown<1,1> , mVUunknown<1,1> , mVUunknown<1,1>,
|
||||||
mVU_ITOF12 , mVU_FTOI12 , mVU_MULAz , mVU_MULAi,
|
mVUunknown<1,1> , mVUunknown<1,1> , mVUunknown<1,1> , mVUunknown<1,1>,
|
||||||
mVU_ADDAi , mVU_SUBAi , mVU_MULA , mVU_OPMULA,
|
mVUunknown<1,1> , mVUunknown<1,1> , mVUunknown<1,1> , mVUunknown<1,1>,
|
||||||
mVUunknown , mVUunknown , mVUunknown , mVUunknown,
|
mVU_MOVE<1,1> , mVU_LQI<1,1> , mVU_DIV<1,1> , mVU_MTIR<1,1>,
|
||||||
mVUunknown , mVUunknown , mVUunknown , mVUunknown,
|
mVU_RNEXT<1,1> , mVUunknown<1,1> , mVUunknown<1,1> , mVUunknown<1,1>, /* 0x10 */
|
||||||
mVUunknown , mVUunknown , mVUunknown , mVUunknown,
|
mVUunknown<1,1> , mVUunknown<1,1> , mVUunknown<1,1> , mVUunknown<1,1>,
|
||||||
mVUunknown , mVUunknown , mVUunknown , mVUunknown,
|
mVUunknown<1,1> , mVU_MFP<1,1> , mVU_XTOP<1,1> , mVU_XGKICK<1,1>,
|
||||||
mVUunknown , mVUunknown , mVUunknown , mVUunknown,
|
mVU_ESADD<1,1> , mVU_EATANxy<1,1> , mVU_ESQRT<1,1> , mVU_ESIN<1,1>,
|
||||||
};
|
};
|
||||||
|
//------------------------------------------------------------------
|
||||||
|
|
||||||
void (*mVU_UPPER_FD_11_TABLE[32])(VURegs* VU, s32 info) = {
|
//------------------------------------------------------------------
|
||||||
mVU_ADDAw , mVU_SUBAw , mVU_MADDAw , mVU_MSUBAw,
|
// mVULowerOP_T3_01_OPCODE
|
||||||
mVU_ITOF15 , mVU_FTOI15 , mVU_MULAw , mVU_CLIP,
|
//------------------------------------------------------------------
|
||||||
mVU_MADDAi , mVU_MSUBAi , mVUunknown , mVU_NOP,
|
void (* mVULowerOP_T3_01_OPCODE00 [32])() = {
|
||||||
mVUunknown , mVUunknown , mVUunknown , mVUunknown,
|
mVUunknown<0,0> , mVUunknown<0,0> , mVUunknown<0,0> , mVUunknown<0,0>,
|
||||||
mVUunknown , mVUunknown , mVUunknown , mVUunknown,
|
mVUunknown<0,0> , mVUunknown<0,0> , mVUunknown<0,0> , mVUunknown<0,0>,
|
||||||
mVUunknown , mVUunknown , mVUunknown , mVUunknown,
|
mVUunknown<0,0> , mVUunknown<0,0> , mVUunknown<0,0> , mVUunknown<0,0>,
|
||||||
mVUunknown , mVUunknown , mVUunknown , mVUunknown,
|
mVU_MR32<0,0> , mVU_SQI<0,0> , mVU_SQRT<0,0> , mVU_MFIR<0,0>,
|
||||||
mVUunknown , mVUunknown , mVUunknown , mVUunknown,
|
mVU_RGET<0,0> , mVUunknown<0,0> , mVUunknown<0,0> , mVUunknown<0,0>, /* 0x10 */
|
||||||
};
|
mVUunknown<0,0> , mVUunknown<0,0> , mVUunknown<0,0> , mVUunknown<0,0>,
|
||||||
|
mVUunknown<0,0> , mVUunknown<0,0> , mVU_XITOP<0,0> , mVUunknown<0,0>,
|
||||||
|
mVU_ERSADD<0,0> , mVU_EATANxz<0,0> , mVU_ERSQRT<0,0> , mVU_EATAN<0,0>,
|
||||||
|
};
|
||||||
|
|
||||||
void mVU_UPPER_FD_00(VURegs* VU, s32 info) {
|
void (* mVULowerOP_T3_01_OPCODE01 [32])() = {
|
||||||
mVU_UPPER_FD_00_TABLE[ ( VU->code >> 6 ) & 0x1f ]( VU, info );
|
mVUunknown<0,1> , mVUunknown<0,1> , mVUunknown<0,1> , mVUunknown<0,1>,
|
||||||
}
|
mVUunknown<0,1> , mVUunknown<0,1> , mVUunknown<0,1> , mVUunknown<0,1>,
|
||||||
void mVU_UPPER_FD_01(VURegs* VU, s32 info) {
|
mVUunknown<0,1> , mVUunknown<0,1> , mVUunknown<0,1> , mVUunknown<0,1>,
|
||||||
mVU_UPPER_FD_01_TABLE[ ( VU->code >> 6 ) & 0x1f ]( VU, info );
|
mVU_MR32<0,1> , mVU_SQI<0,1> , mVU_SQRT<0,1> , mVU_MFIR<0,1>,
|
||||||
}
|
mVU_RGET<0,1> , mVUunknown<0,1> , mVUunknown<0,1> , mVUunknown<0,1>, /* 0x10 */
|
||||||
void mVU_UPPER_FD_10(VURegs* VU, s32 info) {
|
mVUunknown<0,1> , mVUunknown<0,1> , mVUunknown<0,1> , mVUunknown<0,1>,
|
||||||
mVU_UPPER_FD_10_TABLE[ ( VU->code >> 6 ) & 0x1f ]( VU, info );
|
mVUunknown<0,1> , mVUunknown<0,1> , mVU_XITOP<0,1> , mVUunknown<0,1>,
|
||||||
}
|
mVU_ERSADD<0,1> , mVU_EATANxz<0,1> , mVU_ERSQRT<0,1> , mVU_EATAN<0,1>,
|
||||||
void mVU_UPPER_FD_11(VURegs* VU, s32 info) {
|
};
|
||||||
mVU_UPPER_FD_11_TABLE[ ( VU->code >> 6 ) & 0x1f ]( VU, info );
|
|
||||||
}
|
void (* mVULowerOP_T3_01_OPCODE10 [32])() = {
|
||||||
void mVULowerOP(VURegs* VU, s32 info) {
|
mVUunknown<1,0> , mVUunknown<1,0> , mVUunknown<1,0> , mVUunknown<1,0>,
|
||||||
mVULowerOP_OPCODE[ VU->code & 0x3f ]( VU, info );
|
mVUunknown<1,0> , mVUunknown<1,0> , mVUunknown<1,0> , mVUunknown<1,0>,
|
||||||
}
|
mVUunknown<1,0> , mVUunknown<1,0> , mVUunknown<1,0> , mVUunknown<1,0>,
|
||||||
void mVULowerOP_T3_00(VURegs* VU, s32 info) {
|
mVU_MR32<1,0> , mVU_SQI<1,0> , mVU_SQRT<1,0> , mVU_MFIR<1,0>,
|
||||||
mVULowerOP_T3_00_OPCODE[ ( VU->code >> 6 ) & 0x1f ]( VU, info );
|
mVU_RGET<1,0> , mVUunknown<1,0> , mVUunknown<1,0> , mVUunknown<1,0>, /* 0x10 */
|
||||||
}
|
mVUunknown<1,0> , mVUunknown<1,0> , mVUunknown<1,0> , mVUunknown<1,0>,
|
||||||
void mVULowerOP_T3_01(VURegs* VU, s32 info) {
|
mVUunknown<1,0> , mVUunknown<1,0> , mVU_XITOP<1,0> , mVUunknown<1,0>,
|
||||||
mVULowerOP_T3_01_OPCODE[ ( VU->code >> 6 ) & 0x1f ]( VU, info );
|
mVU_ERSADD<1,0> , mVU_EATANxz<1,0> , mVU_ERSQRT<1,0> , mVU_EATAN<1,0>,
|
||||||
}
|
};
|
||||||
void mVULowerOP_T3_10(VURegs* VU, s32 info) {
|
|
||||||
mVULowerOP_T3_10_OPCODE[ ( VU->code >> 6 ) & 0x1f ]( VU, info );
|
void (* mVULowerOP_T3_01_OPCODE11 [32])() = {
|
||||||
}
|
mVUunknown<1,1> , mVUunknown<1,1> , mVUunknown<1,1> , mVUunknown<1,1>,
|
||||||
void mVULowerOP_T3_11(VURegs* VU, s32 info) {
|
mVUunknown<1,1> , mVUunknown<1,1> , mVUunknown<1,1> , mVUunknown<1,1>,
|
||||||
mVULowerOP_T3_11_OPCODE[ ( VU->code >> 6 ) & 0x1f ]( VU, info );
|
mVUunknown<1,1> , mVUunknown<1,1> , mVUunknown<1,1> , mVUunknown<1,1>,
|
||||||
}
|
mVU_MR32<1,1> , mVU_SQI<1,1> , mVU_SQRT<1,1> , mVU_MFIR<1,1>,
|
||||||
void mVUunknown(VURegs* VU, s32 info) {
|
mVU_RGET<1,1> , mVUunknown<1,1> , mVUunknown<1,1> , mVUunknown<1,1>, /* 0x10 */
|
||||||
SysPrintf("Unknown Micro VU opcode called\n");
|
mVUunknown<1,1> , mVUunknown<1,1> , mVUunknown<1,1> , mVUunknown<1,1>,
|
||||||
|
mVUunknown<1,1> , mVUunknown<1,1> , mVU_XITOP<1,1> , mVUunknown<1,1>,
|
||||||
|
mVU_ERSADD<1,1> , mVU_EATANxz<1,1> , mVU_ERSQRT<1,1> , mVU_EATAN<1,1>,
|
||||||
|
};
|
||||||
|
//------------------------------------------------------------------
|
||||||
|
|
||||||
|
//------------------------------------------------------------------
|
||||||
|
// mVULowerOP_T3_10_OPCODE
|
||||||
|
//------------------------------------------------------------------
|
||||||
|
void (* mVULowerOP_T3_10_OPCODE00 [32])() = {
|
||||||
|
mVUunknown<0,0> , mVUunknown<0,0> , mVUunknown<0,0> , mVUunknown<0,0>,
|
||||||
|
mVUunknown<0,0> , mVUunknown<0,0> , mVUunknown<0,0> , mVUunknown<0,0>,
|
||||||
|
mVUunknown<0,0> , mVUunknown<0,0> , mVUunknown<0,0> , mVUunknown<0,0>,
|
||||||
|
mVUunknown<0,0> , mVU_LQD<0,0> , mVU_RSQRT<0,0> , mVU_ILWR<0,0>,
|
||||||
|
mVU_RINIT<0,0> , mVUunknown<0,0> , mVUunknown<0,0> , mVUunknown<0,0>, /* 0x10 */
|
||||||
|
mVUunknown<0,0> , mVUunknown<0,0> , mVUunknown<0,0> , mVUunknown<0,0>,
|
||||||
|
mVUunknown<0,0> , mVUunknown<0,0> , mVUunknown<0,0> , mVUunknown<0,0>,
|
||||||
|
mVU_ELENG<0,0> , mVU_ESUM<0,0> , mVU_ERCPR<0,0> , mVU_EEXP<0,0>,
|
||||||
|
};
|
||||||
|
|
||||||
|
void (* mVULowerOP_T3_10_OPCODE01 [32])() = {
|
||||||
|
mVUunknown<0,1> , mVUunknown<0,1> , mVUunknown<0,1> , mVUunknown<0,1>,
|
||||||
|
mVUunknown<0,1> , mVUunknown<0,1> , mVUunknown<0,1> , mVUunknown<0,1>,
|
||||||
|
mVUunknown<0,1> , mVUunknown<0,1> , mVUunknown<0,1> , mVUunknown<0,1>,
|
||||||
|
mVUunknown<0,1> , mVU_LQD<0,1> , mVU_RSQRT<0,1> , mVU_ILWR<0,1>,
|
||||||
|
mVU_RINIT<0,1> , mVUunknown<0,1> , mVUunknown<0,1> , mVUunknown<0,1>, /* 0x10 */
|
||||||
|
mVUunknown<0,1> , mVUunknown<0,1> , mVUunknown<0,1> , mVUunknown<0,1>,
|
||||||
|
mVUunknown<0,1> , mVUunknown<0,1> , mVUunknown<0,1> , mVUunknown<0,1>,
|
||||||
|
mVU_ELENG<0,1> , mVU_ESUM<0,1> , mVU_ERCPR<0,1> , mVU_EEXP<0,1>,
|
||||||
|
};
|
||||||
|
|
||||||
|
void (* mVULowerOP_T3_10_OPCODE10 [32])() = {
|
||||||
|
mVUunknown<1,0> , mVUunknown<1,0> , mVUunknown<1,0> , mVUunknown<1,0>,
|
||||||
|
mVUunknown<1,0> , mVUunknown<1,0> , mVUunknown<1,0> , mVUunknown<1,0>,
|
||||||
|
mVUunknown<1,0> , mVUunknown<1,0> , mVUunknown<1,0> , mVUunknown<1,0>,
|
||||||
|
mVUunknown<1,0> , mVU_LQD<1,0> , mVU_RSQRT<1,0> , mVU_ILWR<1,0>,
|
||||||
|
mVU_RINIT<1,0> , mVUunknown<1,0> , mVUunknown<1,0> , mVUunknown<1,0>, /* 0x10 */
|
||||||
|
mVUunknown<1,0> , mVUunknown<1,0> , mVUunknown<1,0> , mVUunknown<1,0>,
|
||||||
|
mVUunknown<1,0> , mVUunknown<1,0> , mVUunknown<1,0> , mVUunknown<1,0>,
|
||||||
|
mVU_ELENG<1,0> , mVU_ESUM<1,0> , mVU_ERCPR<1,0> , mVU_EEXP<1,0>,
|
||||||
|
};
|
||||||
|
|
||||||
|
void (* mVULowerOP_T3_10_OPCODE11 [32])() = {
|
||||||
|
mVUunknown<1,1> , mVUunknown<1,1> , mVUunknown<1,1> , mVUunknown<1,1>,
|
||||||
|
mVUunknown<1,1> , mVUunknown<1,1> , mVUunknown<1,1> , mVUunknown<1,1>,
|
||||||
|
mVUunknown<1,1> , mVUunknown<1,1> , mVUunknown<1,1> , mVUunknown<1,1>,
|
||||||
|
mVUunknown<1,1> , mVU_LQD<1,1> , mVU_RSQRT<1,1> , mVU_ILWR<1,1>,
|
||||||
|
mVU_RINIT<1,1> , mVUunknown<1,1> , mVUunknown<1,1> , mVUunknown<1,1>, /* 0x10 */
|
||||||
|
mVUunknown<1,1> , mVUunknown<1,1> , mVUunknown<1,1> , mVUunknown<1,1>,
|
||||||
|
mVUunknown<1,1> , mVUunknown<1,1> , mVUunknown<1,1> , mVUunknown<1,1>,
|
||||||
|
mVU_ELENG<1,1> , mVU_ESUM<1,1> , mVU_ERCPR<1,1> , mVU_EEXP<1,1>,
|
||||||
|
};
|
||||||
|
//------------------------------------------------------------------
|
||||||
|
|
||||||
|
//------------------------------------------------------------------
|
||||||
|
// mVULowerOP_T3_11_OPCODE
|
||||||
|
//------------------------------------------------------------------
|
||||||
|
void (* mVULowerOP_T3_11_OPCODE00 [32])() = {
|
||||||
|
mVUunknown<0,0> , mVUunknown<0,0> , mVUunknown<0,0> , mVUunknown<0,0>,
|
||||||
|
mVUunknown<0,0> , mVUunknown<0,0> , mVUunknown<0,0> , mVUunknown<0,0>,
|
||||||
|
mVUunknown<0,0> , mVUunknown<0,0> , mVUunknown<0,0> , mVUunknown<0,0>,
|
||||||
|
mVUunknown<0,0> , mVU_SQD<0,0> , mVU_WAITQ<0,0> , mVU_ISWR<0,0>,
|
||||||
|
mVU_RXOR<0,0> , mVUunknown<0,0> , mVUunknown<0,0> , mVUunknown<0,0>, /* 0x10 */
|
||||||
|
mVUunknown<0,0> , mVUunknown<0,0> , mVUunknown<0,0> , mVUunknown<0,0>,
|
||||||
|
mVUunknown<0,0> , mVUunknown<0,0> , mVUunknown<0,0> , mVUunknown<0,0>,
|
||||||
|
mVU_ERLENG<0,0> , mVUunknown<0,0> , mVU_WAITP<0,0> , mVUunknown<0,0>,
|
||||||
|
};
|
||||||
|
|
||||||
|
void (* mVULowerOP_T3_11_OPCODE01 [32])() = {
|
||||||
|
mVUunknown<0,1> , mVUunknown<0,1> , mVUunknown<0,1> , mVUunknown<0,1>,
|
||||||
|
mVUunknown<0,1> , mVUunknown<0,1> , mVUunknown<0,1> , mVUunknown<0,1>,
|
||||||
|
mVUunknown<0,1> , mVUunknown<0,1> , mVUunknown<0,1> , mVUunknown<0,1>,
|
||||||
|
mVUunknown<0,1> , mVU_SQD<0,1> , mVU_WAITQ<0,1> , mVU_ISWR<0,1>,
|
||||||
|
mVU_RXOR<0,1> , mVUunknown<0,1> , mVUunknown<0,1> , mVUunknown<0,1>, /* 0x10 */
|
||||||
|
mVUunknown<0,1> , mVUunknown<0,1> , mVUunknown<0,1> , mVUunknown<0,1>,
|
||||||
|
mVUunknown<0,1> , mVUunknown<0,1> , mVUunknown<0,1> , mVUunknown<0,1>,
|
||||||
|
mVU_ERLENG<0,1> , mVUunknown<0,1> , mVU_WAITP<0,1> , mVUunknown<0,1>,
|
||||||
|
};
|
||||||
|
|
||||||
|
void (* mVULowerOP_T3_11_OPCODE10 [32])() = {
|
||||||
|
mVUunknown<1,0> , mVUunknown<1,0> , mVUunknown<1,0> , mVUunknown<1,0>,
|
||||||
|
mVUunknown<1,0> , mVUunknown<1,0> , mVUunknown<1,0> , mVUunknown<1,0>,
|
||||||
|
mVUunknown<1,0> , mVUunknown<1,0> , mVUunknown<1,0> , mVUunknown<1,0>,
|
||||||
|
mVUunknown<1,0> , mVU_SQD<1,0> , mVU_WAITQ<1,0> , mVU_ISWR<1,0>,
|
||||||
|
mVU_RXOR<1,0> , mVUunknown<1,0> , mVUunknown<1,0> , mVUunknown<1,0>, /* 0x10 */
|
||||||
|
mVUunknown<1,0> , mVUunknown<1,0> , mVUunknown<1,0> , mVUunknown<1,0>,
|
||||||
|
mVUunknown<1,0> , mVUunknown<1,0> , mVUunknown<1,0> , mVUunknown<1,0>,
|
||||||
|
mVU_ERLENG<1,0> , mVUunknown<1,0> , mVU_WAITP<1,0> , mVUunknown<1,0>,
|
||||||
|
};
|
||||||
|
|
||||||
|
void (* mVULowerOP_T3_11_OPCODE11 [32])() = {
|
||||||
|
mVUunknown<1,1> , mVUunknown<1,1> , mVUunknown<1,1> , mVUunknown<1,1>,
|
||||||
|
mVUunknown<1,1> , mVUunknown<1,1> , mVUunknown<1,1> , mVUunknown<1,1>,
|
||||||
|
mVUunknown<1,1> , mVUunknown<1,1> , mVUunknown<1,1> , mVUunknown<1,1>,
|
||||||
|
mVUunknown<1,1> , mVU_SQD<1,1> , mVU_WAITQ<1,1> , mVU_ISWR<1,1>,
|
||||||
|
mVU_RXOR<1,1> , mVUunknown<1,1> , mVUunknown<1,1> , mVUunknown<1,1>, /* 0x10 */
|
||||||
|
mVUunknown<1,1> , mVUunknown<1,1> , mVUunknown<1,1> , mVUunknown<1,1>,
|
||||||
|
mVUunknown<1,1> , mVUunknown<1,1> , mVUunknown<1,1> , mVUunknown<1,1>,
|
||||||
|
mVU_ERLENG<1,1> , mVUunknown<1,1> , mVU_WAITP<1,1> , mVUunknown<1,1>,
|
||||||
|
};
|
||||||
|
//------------------------------------------------------------------
|
||||||
|
|
||||||
|
//------------------------------------------------------------------
|
||||||
|
// mVULowerOP_OPCODE
|
||||||
|
//------------------------------------------------------------------
|
||||||
|
void (* mVULowerOP_OPCODE00 [64])() = {
|
||||||
|
mVUunknown<0,0> , mVUunknown<0,0> , mVUunknown<0,0> , mVUunknown<0,0>,
|
||||||
|
mVUunknown<0,0> , mVUunknown<0,0> , mVUunknown<0,0> , mVUunknown<0,0>,
|
||||||
|
mVUunknown<0,0> , mVUunknown<0,0> , mVUunknown<0,0> , mVUunknown<0,0>,
|
||||||
|
mVUunknown<0,0> , mVUunknown<0,0> , mVUunknown<0,0> , mVUunknown<0,0>,
|
||||||
|
mVUunknown<0,0> , mVUunknown<0,0> , mVUunknown<0,0> , mVUunknown<0,0>, /* 0x10 */
|
||||||
|
mVUunknown<0,0> , mVUunknown<0,0> , mVUunknown<0,0> , mVUunknown<0,0>,
|
||||||
|
mVUunknown<0,0> , mVUunknown<0,0> , mVUunknown<0,0> , mVUunknown<0,0>,
|
||||||
|
mVUunknown<0,0> , mVUunknown<0,0> , mVUunknown<0,0> , mVUunknown<0,0>,
|
||||||
|
mVUunknown<0,0> , mVUunknown<0,0> , mVUunknown<0,0> , mVUunknown<0,0>, /* 0x20 */
|
||||||
|
mVUunknown<0,0> , mVUunknown<0,0> , mVUunknown<0,0> , mVUunknown<0,0>,
|
||||||
|
mVUunknown<0,0> , mVUunknown<0,0> , mVUunknown<0,0> , mVUunknown<0,0>,
|
||||||
|
mVUunknown<0,0> , mVUunknown<0,0> , mVUunknown<0,0> , mVUunknown<0,0>,
|
||||||
|
mVU_IADD<0,0> , mVU_ISUB<0,0> , mVU_IADDI<0,0> , mVUunknown<0,0>, /* 0x30 */
|
||||||
|
mVU_IAND<0,0> , mVU_IOR<0,0> , mVUunknown<0,0> , mVUunknown<0,0>,
|
||||||
|
mVUunknown<0,0> , mVUunknown<0,0> , mVUunknown<0,0> , mVUunknown<0,0>,
|
||||||
|
mVULowerOP_T3_00<0,0>, mVULowerOP_T3_01<0,0>, mVULowerOP_T3_10<0,0>, mVULowerOP_T3_11<0,0>,
|
||||||
|
};
|
||||||
|
|
||||||
|
void (* mVULowerOP_OPCODE01 [64])() = {
|
||||||
|
mVUunknown<0,1> , mVUunknown<0,1> , mVUunknown<0,1> , mVUunknown<0,1>,
|
||||||
|
mVUunknown<0,1> , mVUunknown<0,1> , mVUunknown<0,1> , mVUunknown<0,1>,
|
||||||
|
mVUunknown<0,1> , mVUunknown<0,1> , mVUunknown<0,1> , mVUunknown<0,1>,
|
||||||
|
mVUunknown<0,1> , mVUunknown<0,1> , mVUunknown<0,1> , mVUunknown<0,1>,
|
||||||
|
mVUunknown<0,1> , mVUunknown<0,1> , mVUunknown<0,1> , mVUunknown<0,1>, /* 0x10 */
|
||||||
|
mVUunknown<0,1> , mVUunknown<0,1> , mVUunknown<0,1> , mVUunknown<0,1>,
|
||||||
|
mVUunknown<0,1> , mVUunknown<0,1> , mVUunknown<0,1> , mVUunknown<0,1>,
|
||||||
|
mVUunknown<0,1> , mVUunknown<0,1> , mVUunknown<0,1> , mVUunknown<0,1>,
|
||||||
|
mVUunknown<0,1> , mVUunknown<0,1> , mVUunknown<0,1> , mVUunknown<0,1>, /* 0x20 */
|
||||||
|
mVUunknown<0,1> , mVUunknown<0,1> , mVUunknown<0,1> , mVUunknown<0,1>,
|
||||||
|
mVUunknown<0,1> , mVUunknown<0,1> , mVUunknown<0,1> , mVUunknown<0,1>,
|
||||||
|
mVUunknown<0,1> , mVUunknown<0,1> , mVUunknown<0,1> , mVUunknown<0,1>,
|
||||||
|
mVU_IADD<0,1> , mVU_ISUB<0,1> , mVU_IADDI<0,1> , mVUunknown<0,1>, /* 0x30 */
|
||||||
|
mVU_IAND<0,1> , mVU_IOR<0,1> , mVUunknown<0,1> , mVUunknown<0,1>,
|
||||||
|
mVUunknown<0,1> , mVUunknown<0,1> , mVUunknown<0,1> , mVUunknown<0,1>,
|
||||||
|
mVULowerOP_T3_00<0,1>, mVULowerOP_T3_01<0,1>, mVULowerOP_T3_10<0,1>, mVULowerOP_T3_11<0,1>,
|
||||||
|
};
|
||||||
|
|
||||||
|
void (* mVULowerOP_OPCODE10 [64])() = {
|
||||||
|
mVUunknown<1,0> , mVUunknown<1,0> , mVUunknown<1,0> , mVUunknown<1,0>,
|
||||||
|
mVUunknown<1,0> , mVUunknown<1,0> , mVUunknown<1,0> , mVUunknown<1,0>,
|
||||||
|
mVUunknown<1,0> , mVUunknown<1,0> , mVUunknown<1,0> , mVUunknown<1,0>,
|
||||||
|
mVUunknown<1,0> , mVUunknown<1,0> , mVUunknown<1,0> , mVUunknown<1,0>,
|
||||||
|
mVUunknown<1,0> , mVUunknown<1,0> , mVUunknown<1,0> , mVUunknown<1,0>, /* 0x10 */
|
||||||
|
mVUunknown<1,0> , mVUunknown<1,0> , mVUunknown<1,0> , mVUunknown<1,0>,
|
||||||
|
mVUunknown<1,0> , mVUunknown<1,0> , mVUunknown<1,0> , mVUunknown<1,0>,
|
||||||
|
mVUunknown<1,0> , mVUunknown<1,0> , mVUunknown<1,0> , mVUunknown<1,0>,
|
||||||
|
mVUunknown<1,0> , mVUunknown<1,0> , mVUunknown<1,0> , mVUunknown<1,0>, /* 0x20 */
|
||||||
|
mVUunknown<1,0> , mVUunknown<1,0> , mVUunknown<1,0> , mVUunknown<1,0>,
|
||||||
|
mVUunknown<1,0> , mVUunknown<1,0> , mVUunknown<1,0> , mVUunknown<1,0>,
|
||||||
|
mVUunknown<1,0> , mVUunknown<1,0> , mVUunknown<1,0> , mVUunknown<1,0>,
|
||||||
|
mVU_IADD<1,0> , mVU_ISUB<1,0> , mVU_IADDI<1,0> , mVUunknown<1,0>, /* 0x30 */
|
||||||
|
mVU_IAND<1,0> , mVU_IOR<1,0> , mVUunknown<1,0> , mVUunknown<1,0>,
|
||||||
|
mVUunknown<1,0> , mVUunknown<1,0> , mVUunknown<1,0> , mVUunknown<1,0>,
|
||||||
|
mVULowerOP_T3_00<1,0>, mVULowerOP_T3_01<1,0>, mVULowerOP_T3_10<1,0>, mVULowerOP_T3_11<1,0>,
|
||||||
|
};
|
||||||
|
|
||||||
|
void (* mVULowerOP_OPCODE11 [64])() = {
|
||||||
|
mVUunknown<1,1> , mVUunknown<1,1> , mVUunknown<1,1> , mVUunknown<1,1>,
|
||||||
|
mVUunknown<1,1> , mVUunknown<1,1> , mVUunknown<1,1> , mVUunknown<1,1>,
|
||||||
|
mVUunknown<1,1> , mVUunknown<1,1> , mVUunknown<1,1> , mVUunknown<1,1>,
|
||||||
|
mVUunknown<1,1> , mVUunknown<1,1> , mVUunknown<1,1> , mVUunknown<1,1>,
|
||||||
|
mVUunknown<1,1> , mVUunknown<1,1> , mVUunknown<1,1> , mVUunknown<1,1>, /* 0x10 */
|
||||||
|
mVUunknown<1,1> , mVUunknown<1,1> , mVUunknown<1,1> , mVUunknown<1,1>,
|
||||||
|
mVUunknown<1,1> , mVUunknown<1,1> , mVUunknown<1,1> , mVUunknown<1,1>,
|
||||||
|
mVUunknown<1,1> , mVUunknown<1,1> , mVUunknown<1,1> , mVUunknown<1,1>,
|
||||||
|
mVUunknown<1,1> , mVUunknown<1,1> , mVUunknown<1,1> , mVUunknown<1,1>, /* 0x20 */
|
||||||
|
mVUunknown<1,1> , mVUunknown<1,1> , mVUunknown<1,1> , mVUunknown<1,1>,
|
||||||
|
mVUunknown<1,1> , mVUunknown<1,1> , mVUunknown<1,1> , mVUunknown<1,1>,
|
||||||
|
mVUunknown<1,1> , mVUunknown<1,1> , mVUunknown<1,1> , mVUunknown<1,1>,
|
||||||
|
mVU_IADD<1,1> , mVU_ISUB<1,1> , mVU_IADDI<1,1> , mVUunknown<1,1>, /* 0x30 */
|
||||||
|
mVU_IAND<1,1> , mVU_IOR<1,1> , mVUunknown<1,1> , mVUunknown<1,1>,
|
||||||
|
mVUunknown<1,1> , mVUunknown<1,1> , mVUunknown<1,1> , mVUunknown<1,1>,
|
||||||
|
mVULowerOP_T3_00<1,1>, mVULowerOP_T3_01<1,1>, mVULowerOP_T3_10<1,1>, mVULowerOP_T3_11<1,1>,
|
||||||
|
};
|
||||||
|
//------------------------------------------------------------------
|
||||||
|
|
||||||
|
//------------------------------------------------------------------
|
||||||
|
// mVU_UPPER_OPCODE
|
||||||
|
//------------------------------------------------------------------
|
||||||
|
void (* mVU_UPPER_OPCODE00 [64])() = {
|
||||||
|
mVU_ADDx<0,0> , mVU_ADDy<0,0> , mVU_ADDz<0,0> , mVU_ADDw<0,0>,
|
||||||
|
mVU_SUBx<0,0> , mVU_SUBy<0,0> , mVU_SUBz<0,0> , mVU_SUBw<0,0>,
|
||||||
|
mVU_MADDx<0,0> , mVU_MADDy<0,0> , mVU_MADDz<0,0> , mVU_MADDw<0,0>,
|
||||||
|
mVU_MSUBx<0,0> , mVU_MSUBy<0,0> , mVU_MSUBz<0,0> , mVU_MSUBw<0,0>,
|
||||||
|
mVU_MAXx<0,0> , mVU_MAXy<0,0> , mVU_MAXz<0,0> , mVU_MAXw<0,0>, /* 0x10 */
|
||||||
|
mVU_MINIx<0,0> , mVU_MINIy<0,0> , mVU_MINIz<0,0> , mVU_MINIw<0,0>,
|
||||||
|
mVU_MULx<0,0> , mVU_MULy<0,0> , mVU_MULz<0,0> , mVU_MULw<0,0>,
|
||||||
|
mVU_MULq<0,0> , mVU_MAXi<0,0> , mVU_MULi<0,0> , mVU_MINIi<0,0>,
|
||||||
|
mVU_ADDq<0,0> , mVU_MADDq<0,0> , mVU_ADDi<0,0> , mVU_MADDi<0,0>, /* 0x20 */
|
||||||
|
mVU_SUBq<0,0> , mVU_MSUBq<0,0> , mVU_SUBi<0,0> , mVU_MSUBi<0,0>,
|
||||||
|
mVU_ADD<0,0> , mVU_MADD<0,0> , mVU_MUL<0,0> , mVU_MAX<0,0>,
|
||||||
|
mVU_SUB<0,0> , mVU_MSUB<0,0> , mVU_OPMSUB<0,0> , mVU_MINI<0,0>,
|
||||||
|
mVUunknown<0,0> , mVUunknown<0,0> , mVUunknown<0,0> , mVUunknown<0,0>, /* 0x30 */
|
||||||
|
mVUunknown<0,0> , mVUunknown<0,0> , mVUunknown<0,0> , mVUunknown<0,0>,
|
||||||
|
mVUunknown<0,0> , mVUunknown<0,0> , mVUunknown<0,0> , mVUunknown<0,0>,
|
||||||
|
mVU_UPPER_FD_00<0,0>, mVU_UPPER_FD_01<0,0>, mVU_UPPER_FD_10<0,0>, mVU_UPPER_FD_11<0,0>,
|
||||||
|
};
|
||||||
|
|
||||||
|
void (* mVU_UPPER_OPCODE01 [64])() = {
|
||||||
|
mVU_ADDx<0,1> , mVU_ADDy<0,1> , mVU_ADDz<0,1> , mVU_ADDw<0,1>,
|
||||||
|
mVU_SUBx<0,1> , mVU_SUBy<0,1> , mVU_SUBz<0,1> , mVU_SUBw<0,1>,
|
||||||
|
mVU_MADDx<0,1> , mVU_MADDy<0,1> , mVU_MADDz<0,1> , mVU_MADDw<0,1>,
|
||||||
|
mVU_MSUBx<0,1> , mVU_MSUBy<0,1> , mVU_MSUBz<0,1> , mVU_MSUBw<0,1>,
|
||||||
|
mVU_MAXx<0,1> , mVU_MAXy<0,1> , mVU_MAXz<0,1> , mVU_MAXw<0,1>, /* 0x10 */
|
||||||
|
mVU_MINIx<0,1> , mVU_MINIy<0,1> , mVU_MINIz<0,1> , mVU_MINIw<0,1>,
|
||||||
|
mVU_MULx<0,1> , mVU_MULy<0,1> , mVU_MULz<0,1> , mVU_MULw<0,1>,
|
||||||
|
mVU_MULq<0,1> , mVU_MAXi<0,1> , mVU_MULi<0,1> , mVU_MINIi<0,1>,
|
||||||
|
mVU_ADDq<0,1> , mVU_MADDq<0,1> , mVU_ADDi<0,1> , mVU_MADDi<0,1>, /* 0x20 */
|
||||||
|
mVU_SUBq<0,1> , mVU_MSUBq<0,1> , mVU_SUBi<0,1> , mVU_MSUBi<0,1>,
|
||||||
|
mVU_ADD<0,1> , mVU_MADD<0,1> , mVU_MUL<0,1> , mVU_MAX<0,1>,
|
||||||
|
mVU_SUB<0,1> , mVU_MSUB<0,1> , mVU_OPMSUB<0,1> , mVU_MINI<0,1>,
|
||||||
|
mVUunknown<0,1> , mVUunknown<0,1> , mVUunknown<0,1> , mVUunknown<0,1>, /* 0x30 */
|
||||||
|
mVUunknown<0,1> , mVUunknown<0,1> , mVUunknown<0,1> , mVUunknown<0,1>,
|
||||||
|
mVUunknown<0,1> , mVUunknown<0,1> , mVUunknown<0,1> , mVUunknown<0,1>,
|
||||||
|
mVU_UPPER_FD_00<0,1>, mVU_UPPER_FD_01<0,1>, mVU_UPPER_FD_10<0,1>, mVU_UPPER_FD_11<0,1>,
|
||||||
|
};
|
||||||
|
|
||||||
|
void (* mVU_UPPER_OPCODE10 [64])() = {
|
||||||
|
mVU_ADDx<1,0> , mVU_ADDy<1,0> , mVU_ADDz<1,0> , mVU_ADDw<1,0>,
|
||||||
|
mVU_SUBx<1,0> , mVU_SUBy<1,0> , mVU_SUBz<1,0> , mVU_SUBw<1,0>,
|
||||||
|
mVU_MADDx<1,0> , mVU_MADDy<1,0> , mVU_MADDz<1,0> , mVU_MADDw<1,0>,
|
||||||
|
mVU_MSUBx<1,0> , mVU_MSUBy<1,0> , mVU_MSUBz<1,0> , mVU_MSUBw<1,0>,
|
||||||
|
mVU_MAXx<1,0> , mVU_MAXy<1,0> , mVU_MAXz<1,0> , mVU_MAXw<1,0>, /* 0x10 */
|
||||||
|
mVU_MINIx<1,0> , mVU_MINIy<1,0> , mVU_MINIz<1,0> , mVU_MINIw<1,0>,
|
||||||
|
mVU_MULx<1,0> , mVU_MULy<1,0> , mVU_MULz<1,0> , mVU_MULw<1,0>,
|
||||||
|
mVU_MULq<1,0> , mVU_MAXi<1,0> , mVU_MULi<1,0> , mVU_MINIi<1,0>,
|
||||||
|
mVU_ADDq<1,0> , mVU_MADDq<1,0> , mVU_ADDi<1,0> , mVU_MADDi<1,0>, /* 0x20 */
|
||||||
|
mVU_SUBq<1,0> , mVU_MSUBq<1,0> , mVU_SUBi<1,0> , mVU_MSUBi<1,0>,
|
||||||
|
mVU_ADD<1,0> , mVU_MADD<1,0> , mVU_MUL<1,0> , mVU_MAX<1,0>,
|
||||||
|
mVU_SUB<1,0> , mVU_MSUB<1,0> , mVU_OPMSUB<1,0> , mVU_MINI<1,0>,
|
||||||
|
mVUunknown<1,0> , mVUunknown<1,0> , mVUunknown<1,0> , mVUunknown<1,0>, /* 0x30 */
|
||||||
|
mVUunknown<1,0> , mVUunknown<1,0> , mVUunknown<1,0> , mVUunknown<1,0>,
|
||||||
|
mVUunknown<1,0> , mVUunknown<1,0> , mVUunknown<1,0> , mVUunknown<1,0>,
|
||||||
|
mVU_UPPER_FD_00<1,0>, mVU_UPPER_FD_01<1,0>, mVU_UPPER_FD_10<1,0>, mVU_UPPER_FD_11<1,0>,
|
||||||
|
};
|
||||||
|
|
||||||
|
void (* mVU_UPPER_OPCODE11 [64])() = {
|
||||||
|
mVU_ADDx<1,1> , mVU_ADDy<1,1> , mVU_ADDz<1,1> , mVU_ADDw<1,1>,
|
||||||
|
mVU_SUBx<1,1> , mVU_SUBy<1,1> , mVU_SUBz<1,1> , mVU_SUBw<1,1>,
|
||||||
|
mVU_MADDx<1,1> , mVU_MADDy<1,1> , mVU_MADDz<1,1> , mVU_MADDw<1,1>,
|
||||||
|
mVU_MSUBx<1,1> , mVU_MSUBy<1,1> , mVU_MSUBz<1,1> , mVU_MSUBw<1,1>,
|
||||||
|
mVU_MAXx<1,1> , mVU_MAXy<1,1> , mVU_MAXz<1,1> , mVU_MAXw<1,1>, /* 0x10 */
|
||||||
|
mVU_MINIx<1,1> , mVU_MINIy<1,1> , mVU_MINIz<1,1> , mVU_MINIw<1,1>,
|
||||||
|
mVU_MULx<1,1> , mVU_MULy<1,1> , mVU_MULz<1,1> , mVU_MULw<1,1>,
|
||||||
|
mVU_MULq<1,1> , mVU_MAXi<1,1> , mVU_MULi<1,1> , mVU_MINIi<1,1>,
|
||||||
|
mVU_ADDq<1,1> , mVU_MADDq<1,1> , mVU_ADDi<1,1> , mVU_MADDi<1,1>, /* 0x20 */
|
||||||
|
mVU_SUBq<1,1> , mVU_MSUBq<1,1> , mVU_SUBi<1,1> , mVU_MSUBi<1,1>,
|
||||||
|
mVU_ADD<1,1> , mVU_MADD<1,1> , mVU_MUL<1,1> , mVU_MAX<1,1>,
|
||||||
|
mVU_SUB<1,1> , mVU_MSUB<1,1> , mVU_OPMSUB<1,1> , mVU_MINI<1,1>,
|
||||||
|
mVUunknown<1,1> , mVUunknown<1,1> , mVUunknown<1,1> , mVUunknown<1,1>, /* 0x30 */
|
||||||
|
mVUunknown<1,1> , mVUunknown<1,1> , mVUunknown<1,1> , mVUunknown<1,1>,
|
||||||
|
mVUunknown<1,1> , mVUunknown<1,1> , mVUunknown<1,1> , mVUunknown<1,1>,
|
||||||
|
mVU_UPPER_FD_00<1,1>, mVU_UPPER_FD_01<1,1>, mVU_UPPER_FD_10<1,1>, mVU_UPPER_FD_11<1,1>,
|
||||||
|
};
|
||||||
|
//------------------------------------------------------------------
|
||||||
|
|
||||||
|
//------------------------------------------------------------------
|
||||||
|
// mVU_UPPER_FD_00_TABLE
|
||||||
|
//------------------------------------------------------------------
|
||||||
|
void (* mVU_UPPER_FD_00_TABLE00 [32])() = {
|
||||||
|
mVU_ADDAx<0,0> , mVU_SUBAx<0,0> , mVU_MADDAx<0,0> , mVU_MSUBAx<0,0>,
|
||||||
|
mVU_ITOF0<0,0> , mVU_FTOI0<0,0> , mVU_MULAx<0,0> , mVU_MULAq<0,0>,
|
||||||
|
mVU_ADDAq<0,0> , mVU_SUBAq<0,0> , mVU_ADDA<0,0> , mVU_SUBA<0,0>,
|
||||||
|
mVUunknown<0,0> , mVUunknown<0,0> , mVUunknown<0,0> , mVUunknown<0,0>,
|
||||||
|
mVUunknown<0,0> , mVUunknown<0,0> , mVUunknown<0,0> , mVUunknown<0,0>,
|
||||||
|
mVUunknown<0,0> , mVUunknown<0,0> , mVUunknown<0,0> , mVUunknown<0,0>,
|
||||||
|
mVUunknown<0,0> , mVUunknown<0,0> , mVUunknown<0,0> , mVUunknown<0,0>,
|
||||||
|
mVUunknown<0,0> , mVUunknown<0,0> , mVUunknown<0,0> , mVUunknown<0,0>,
|
||||||
|
};
|
||||||
|
|
||||||
|
void (* mVU_UPPER_FD_00_TABLE01 [32])() = {
|
||||||
|
mVU_ADDAx<0,1> , mVU_SUBAx<0,1> , mVU_MADDAx<0,1> , mVU_MSUBAx<0,1>,
|
||||||
|
mVU_ITOF0<0,1> , mVU_FTOI0<0,1> , mVU_MULAx<0,1> , mVU_MULAq<0,1>,
|
||||||
|
mVU_ADDAq<0,1> , mVU_SUBAq<0,1> , mVU_ADDA<0,1> , mVU_SUBA<0,1>,
|
||||||
|
mVUunknown<0,1> , mVUunknown<0,1> , mVUunknown<0,1> , mVUunknown<0,1>,
|
||||||
|
mVUunknown<0,1> , mVUunknown<0,1> , mVUunknown<0,1> , mVUunknown<0,1>,
|
||||||
|
mVUunknown<0,1> , mVUunknown<0,1> , mVUunknown<0,1> , mVUunknown<0,1>,
|
||||||
|
mVUunknown<0,1> , mVUunknown<0,1> , mVUunknown<0,1> , mVUunknown<0,1>,
|
||||||
|
mVUunknown<0,1> , mVUunknown<0,1> , mVUunknown<0,1> , mVUunknown<0,1>,
|
||||||
|
};
|
||||||
|
|
||||||
|
void (* mVU_UPPER_FD_00_TABLE10 [32])() = {
|
||||||
|
mVU_ADDAx<1,0> , mVU_SUBAx<1,0> , mVU_MADDAx<1,0> , mVU_MSUBAx<1,0>,
|
||||||
|
mVU_ITOF0<1,0> , mVU_FTOI0<1,0> , mVU_MULAx<1,0> , mVU_MULAq<1,0>,
|
||||||
|
mVU_ADDAq<1,0> , mVU_SUBAq<1,0> , mVU_ADDA<1,0> , mVU_SUBA<1,0>,
|
||||||
|
mVUunknown<1,0> , mVUunknown<1,0> , mVUunknown<1,0> , mVUunknown<1,0>,
|
||||||
|
mVUunknown<1,0> , mVUunknown<1,0> , mVUunknown<1,0> , mVUunknown<1,0>,
|
||||||
|
mVUunknown<1,0> , mVUunknown<1,0> , mVUunknown<1,0> , mVUunknown<1,0>,
|
||||||
|
mVUunknown<1,0> , mVUunknown<1,0> , mVUunknown<1,0> , mVUunknown<1,0>,
|
||||||
|
mVUunknown<1,0> , mVUunknown<1,0> , mVUunknown<1,0> , mVUunknown<1,0>,
|
||||||
|
};
|
||||||
|
|
||||||
|
void (* mVU_UPPER_FD_00_TABLE11 [32])() = {
|
||||||
|
mVU_ADDAx<1,1> , mVU_SUBAx<1,1> , mVU_MADDAx<1,1> , mVU_MSUBAx<1,1>,
|
||||||
|
mVU_ITOF0<1,1> , mVU_FTOI0<1,1> , mVU_MULAx<1,1> , mVU_MULAq<1,1>,
|
||||||
|
mVU_ADDAq<1,1> , mVU_SUBAq<1,1> , mVU_ADDA<1,1> , mVU_SUBA<1,1>,
|
||||||
|
mVUunknown<1,1> , mVUunknown<1,1> , mVUunknown<1,1> , mVUunknown<1,1>,
|
||||||
|
mVUunknown<1,1> , mVUunknown<1,1> , mVUunknown<1,1> , mVUunknown<1,1>,
|
||||||
|
mVUunknown<1,1> , mVUunknown<1,1> , mVUunknown<1,1> , mVUunknown<1,1>,
|
||||||
|
mVUunknown<1,1> , mVUunknown<1,1> , mVUunknown<1,1> , mVUunknown<1,1>,
|
||||||
|
mVUunknown<1,1> , mVUunknown<1,1> , mVUunknown<1,1> , mVUunknown<1,1>,
|
||||||
|
};
|
||||||
|
//------------------------------------------------------------------
|
||||||
|
|
||||||
|
//------------------------------------------------------------------
|
||||||
|
// mVU_UPPER_FD_01_TABLE
|
||||||
|
//------------------------------------------------------------------
|
||||||
|
void (* mVU_UPPER_FD_01_TABLE00 [32])() = {
|
||||||
|
mVU_ADDAy<0,0> , mVU_SUBAy<0,0> , mVU_MADDAy<0,0> , mVU_MSUBAy<0,0>,
|
||||||
|
mVU_ITOF4<0,0> , mVU_FTOI4<0,0> , mVU_MULAy<0,0> , mVU_ABS<0,0>,
|
||||||
|
mVU_MADDAq<0,0> , mVU_MSUBAq<0,0> , mVU_MADDA<0,0> , mVU_MSUBA<0,0>,
|
||||||
|
mVUunknown<0,0> , mVUunknown<0,0> , mVUunknown<0,0> , mVUunknown<0,0>,
|
||||||
|
mVUunknown<0,0> , mVUunknown<0,0> , mVUunknown<0,0> , mVUunknown<0,0>,
|
||||||
|
mVUunknown<0,0> , mVUunknown<0,0> , mVUunknown<0,0> , mVUunknown<0,0>,
|
||||||
|
mVUunknown<0,0> , mVUunknown<0,0> , mVUunknown<0,0> , mVUunknown<0,0>,
|
||||||
|
mVUunknown<0,0> , mVUunknown<0,0> , mVUunknown<0,0> , mVUunknown<0,0>,
|
||||||
|
};
|
||||||
|
|
||||||
|
void (* mVU_UPPER_FD_01_TABLE01 [32])() = {
|
||||||
|
mVU_ADDAy<0,1> , mVU_SUBAy<0,1> , mVU_MADDAy<0,1> , mVU_MSUBAy<0,1>,
|
||||||
|
mVU_ITOF4<0,1> , mVU_FTOI4<0,1> , mVU_MULAy<0,1> , mVU_ABS<0,1>,
|
||||||
|
mVU_MADDAq<0,1> , mVU_MSUBAq<0,1> , mVU_MADDA<0,1> , mVU_MSUBA<0,1>,
|
||||||
|
mVUunknown<0,1> , mVUunknown<0,1> , mVUunknown<0,1> , mVUunknown<0,1>,
|
||||||
|
mVUunknown<0,1> , mVUunknown<0,1> , mVUunknown<0,1> , mVUunknown<0,1>,
|
||||||
|
mVUunknown<0,1> , mVUunknown<0,1> , mVUunknown<0,1> , mVUunknown<0,1>,
|
||||||
|
mVUunknown<0,1> , mVUunknown<0,1> , mVUunknown<0,1> , mVUunknown<0,1>,
|
||||||
|
mVUunknown<0,1> , mVUunknown<0,1> , mVUunknown<0,1> , mVUunknown<0,1>,
|
||||||
|
};
|
||||||
|
|
||||||
|
void (* mVU_UPPER_FD_01_TABLE10 [32])() = {
|
||||||
|
mVU_ADDAy<1,0> , mVU_SUBAy<1,0> , mVU_MADDAy<1,0> , mVU_MSUBAy<1,0>,
|
||||||
|
mVU_ITOF4<1,0> , mVU_FTOI4<1,0> , mVU_MULAy<1,0> , mVU_ABS<1,0>,
|
||||||
|
mVU_MADDAq<1,0> , mVU_MSUBAq<1,0> , mVU_MADDA<1,0> , mVU_MSUBA<1,0>,
|
||||||
|
mVUunknown<1,0> , mVUunknown<1,0> , mVUunknown<1,0> , mVUunknown<1,0>,
|
||||||
|
mVUunknown<1,0> , mVUunknown<1,0> , mVUunknown<1,0> , mVUunknown<1,0>,
|
||||||
|
mVUunknown<1,0> , mVUunknown<1,0> , mVUunknown<1,0> , mVUunknown<1,0>,
|
||||||
|
mVUunknown<1,0> , mVUunknown<1,0> , mVUunknown<1,0> , mVUunknown<1,0>,
|
||||||
|
mVUunknown<1,0> , mVUunknown<1,0> , mVUunknown<1,0> , mVUunknown<1,0>,
|
||||||
|
};
|
||||||
|
|
||||||
|
void (* mVU_UPPER_FD_01_TABLE11 [32])() = {
|
||||||
|
mVU_ADDAy<1,1> , mVU_SUBAy<1,1> , mVU_MADDAy<1,1> , mVU_MSUBAy<1,1>,
|
||||||
|
mVU_ITOF4<1,1> , mVU_FTOI4<1,1> , mVU_MULAy<1,1> , mVU_ABS<1,1>,
|
||||||
|
mVU_MADDAq<1,1> , mVU_MSUBAq<1,1> , mVU_MADDA<1,1> , mVU_MSUBA<1,1>,
|
||||||
|
mVUunknown<1,1> , mVUunknown<1,1> , mVUunknown<1,1> , mVUunknown<1,1>,
|
||||||
|
mVUunknown<1,1> , mVUunknown<1,1> , mVUunknown<1,1> , mVUunknown<1,1>,
|
||||||
|
mVUunknown<1,1> , mVUunknown<1,1> , mVUunknown<1,1> , mVUunknown<1,1>,
|
||||||
|
mVUunknown<1,1> , mVUunknown<1,1> , mVUunknown<1,1> , mVUunknown<1,1>,
|
||||||
|
mVUunknown<1,1> , mVUunknown<1,1> , mVUunknown<1,1> , mVUunknown<1,1>,
|
||||||
|
};
|
||||||
|
//------------------------------------------------------------------
|
||||||
|
|
||||||
|
//------------------------------------------------------------------
|
||||||
|
// mVU_UPPER_FD_10_TABLE
|
||||||
|
//------------------------------------------------------------------
|
||||||
|
void (* mVU_UPPER_FD_10_TABLE00 [32])() = {
|
||||||
|
mVU_ADDAz<0,0> , mVU_SUBAz<0,0> , mVU_MADDAz<0,0> , mVU_MSUBAz<0,0>,
|
||||||
|
mVU_ITOF12<0,0> , mVU_FTOI12<0,0> , mVU_MULAz<0,0> , mVU_MULAi<0,0>,
|
||||||
|
mVU_ADDAi<0,0> , mVU_SUBAi<0,0> , mVU_MULA<0,0> , mVU_OPMULA<0,0>,
|
||||||
|
mVUunknown<0,0> , mVUunknown<0,0> , mVUunknown<0,0> , mVUunknown<0,0>,
|
||||||
|
mVUunknown<0,0> , mVUunknown<0,0> , mVUunknown<0,0> , mVUunknown<0,0>,
|
||||||
|
mVUunknown<0,0> , mVUunknown<0,0> , mVUunknown<0,0> , mVUunknown<0,0>,
|
||||||
|
mVUunknown<0,0> , mVUunknown<0,0> , mVUunknown<0,0> , mVUunknown<0,0>,
|
||||||
|
mVUunknown<0,0> , mVUunknown<0,0> , mVUunknown<0,0> , mVUunknown<0,0>,
|
||||||
|
};
|
||||||
|
|
||||||
|
void (* mVU_UPPER_FD_10_TABLE01 [32])() = {
|
||||||
|
mVU_ADDAz<0,1> , mVU_SUBAz<0,1> , mVU_MADDAz<0,1> , mVU_MSUBAz<0,1>,
|
||||||
|
mVU_ITOF12<0,1> , mVU_FTOI12<0,1> , mVU_MULAz<0,1> , mVU_MULAi<0,1>,
|
||||||
|
mVU_ADDAi<0,1> , mVU_SUBAi<0,1> , mVU_MULA<0,1> , mVU_OPMULA<0,1>,
|
||||||
|
mVUunknown<0,1> , mVUunknown<0,1> , mVUunknown<0,1> , mVUunknown<0,1>,
|
||||||
|
mVUunknown<0,1> , mVUunknown<0,1> , mVUunknown<0,1> , mVUunknown<0,1>,
|
||||||
|
mVUunknown<0,1> , mVUunknown<0,1> , mVUunknown<0,1> , mVUunknown<0,1>,
|
||||||
|
mVUunknown<0,1> , mVUunknown<0,1> , mVUunknown<0,1> , mVUunknown<0,1>,
|
||||||
|
mVUunknown<0,1> , mVUunknown<0,1> , mVUunknown<0,1> , mVUunknown<0,1>,
|
||||||
|
};
|
||||||
|
|
||||||
|
void (* mVU_UPPER_FD_10_TABLE10 [32])() = {
|
||||||
|
mVU_ADDAz<1,0> , mVU_SUBAz<1,0> , mVU_MADDAz<1,0> , mVU_MSUBAz<1,0>,
|
||||||
|
mVU_ITOF12<1,0> , mVU_FTOI12<1,0> , mVU_MULAz<1,0> , mVU_MULAi<1,0>,
|
||||||
|
mVU_ADDAi<1,0> , mVU_SUBAi<1,0> , mVU_MULA<1,0> , mVU_OPMULA<1,0>,
|
||||||
|
mVUunknown<1,0> , mVUunknown<1,0> , mVUunknown<1,0> , mVUunknown<1,0>,
|
||||||
|
mVUunknown<1,0> , mVUunknown<1,0> , mVUunknown<1,0> , mVUunknown<1,0>,
|
||||||
|
mVUunknown<1,0> , mVUunknown<1,0> , mVUunknown<1,0> , mVUunknown<1,0>,
|
||||||
|
mVUunknown<1,0> , mVUunknown<1,0> , mVUunknown<1,0> , mVUunknown<1,0>,
|
||||||
|
mVUunknown<1,0> , mVUunknown<1,0> , mVUunknown<1,0> , mVUunknown<1,0>,
|
||||||
|
};
|
||||||
|
|
||||||
|
void (* mVU_UPPER_FD_10_TABLE11 [32])() = {
|
||||||
|
mVU_ADDAz<1,1> , mVU_SUBAz<1,1> , mVU_MADDAz<1,1> , mVU_MSUBAz<1,1>,
|
||||||
|
mVU_ITOF12<1,1> , mVU_FTOI12<1,1> , mVU_MULAz<1,1> , mVU_MULAi<1,1>,
|
||||||
|
mVU_ADDAi<1,1> , mVU_SUBAi<1,1> , mVU_MULA<1,1> , mVU_OPMULA<1,1>,
|
||||||
|
mVUunknown<1,1> , mVUunknown<1,1> , mVUunknown<1,1> , mVUunknown<1,1>,
|
||||||
|
mVUunknown<1,1> , mVUunknown<1,1> , mVUunknown<1,1> , mVUunknown<1,1>,
|
||||||
|
mVUunknown<1,1> , mVUunknown<1,1> , mVUunknown<1,1> , mVUunknown<1,1>,
|
||||||
|
mVUunknown<1,1> , mVUunknown<1,1> , mVUunknown<1,1> , mVUunknown<1,1>,
|
||||||
|
mVUunknown<1,1> , mVUunknown<1,1> , mVUunknown<1,1> , mVUunknown<1,1>,
|
||||||
|
};
|
||||||
|
//------------------------------------------------------------------
|
||||||
|
|
||||||
|
//------------------------------------------------------------------
|
||||||
|
// mVU_UPPER_FD_11_TABLE
|
||||||
|
//------------------------------------------------------------------
|
||||||
|
void (* mVU_UPPER_FD_11_TABLE00 [32])() = {
|
||||||
|
mVU_ADDAw<0,0> , mVU_SUBAw<0,0> , mVU_MADDAw<0,0> , mVU_MSUBAw<0,0>,
|
||||||
|
mVU_ITOF15<0,0> , mVU_FTOI15<0,0> , mVU_MULAw<0,0> , mVU_CLIP<0,0>,
|
||||||
|
mVU_MADDAi<0,0> , mVU_MSUBAi<0,0> , mVUunknown<0,0> , mVU_NOP<0,0>,
|
||||||
|
mVUunknown<0,0> , mVUunknown<0,0> , mVUunknown<0,0> , mVUunknown<0,0>,
|
||||||
|
mVUunknown<0,0> , mVUunknown<0,0> , mVUunknown<0,0> , mVUunknown<0,0>,
|
||||||
|
mVUunknown<0,0> , mVUunknown<0,0> , mVUunknown<0,0> , mVUunknown<0,0>,
|
||||||
|
mVUunknown<0,0> , mVUunknown<0,0> , mVUunknown<0,0> , mVUunknown<0,0>,
|
||||||
|
mVUunknown<0,0> , mVUunknown<0,0> , mVUunknown<0,0> , mVUunknown<0,0>,
|
||||||
|
};
|
||||||
|
|
||||||
|
void (* mVU_UPPER_FD_11_TABLE01 [32])() = {
|
||||||
|
mVU_ADDAw<0,1> , mVU_SUBAw<0,1> , mVU_MADDAw<0,1> , mVU_MSUBAw<0,1>,
|
||||||
|
mVU_ITOF15<0,1> , mVU_FTOI15<0,1> , mVU_MULAw<0,1> , mVU_CLIP<0,1>,
|
||||||
|
mVU_MADDAi<0,1> , mVU_MSUBAi<0,1> , mVUunknown<0,1> , mVU_NOP<0,1>,
|
||||||
|
mVUunknown<0,1> , mVUunknown<0,1> , mVUunknown<0,1> , mVUunknown<0,1>,
|
||||||
|
mVUunknown<0,1> , mVUunknown<0,1> , mVUunknown<0,1> , mVUunknown<0,1>,
|
||||||
|
mVUunknown<0,1> , mVUunknown<0,1> , mVUunknown<0,1> , mVUunknown<0,1>,
|
||||||
|
mVUunknown<0,1> , mVUunknown<0,1> , mVUunknown<0,1> , mVUunknown<0,1>,
|
||||||
|
mVUunknown<0,1> , mVUunknown<0,1> , mVUunknown<0,1> , mVUunknown<0,1>,
|
||||||
|
};
|
||||||
|
|
||||||
|
void (* mVU_UPPER_FD_11_TABLE10 [32])() = {
|
||||||
|
mVU_ADDAw<1,0> , mVU_SUBAw<1,0> , mVU_MADDAw<1,0> , mVU_MSUBAw<1,0>,
|
||||||
|
mVU_ITOF15<1,0> , mVU_FTOI15<1,0> , mVU_MULAw<1,0> , mVU_CLIP<1,0>,
|
||||||
|
mVU_MADDAi<1,0> , mVU_MSUBAi<1,0> , mVUunknown<1,0> , mVU_NOP<1,0>,
|
||||||
|
mVUunknown<1,0> , mVUunknown<1,0> , mVUunknown<1,0> , mVUunknown<1,0>,
|
||||||
|
mVUunknown<1,0> , mVUunknown<1,0> , mVUunknown<1,0> , mVUunknown<1,0>,
|
||||||
|
mVUunknown<1,0> , mVUunknown<1,0> , mVUunknown<1,0> , mVUunknown<1,0>,
|
||||||
|
mVUunknown<1,0> , mVUunknown<1,0> , mVUunknown<1,0> , mVUunknown<1,0>,
|
||||||
|
mVUunknown<1,0> , mVUunknown<1,0> , mVUunknown<1,0> , mVUunknown<1,0>,
|
||||||
|
};
|
||||||
|
|
||||||
|
void (* mVU_UPPER_FD_11_TABLE11 [32])() = {
|
||||||
|
mVU_ADDAw<1,1> , mVU_SUBAw<1,1> , mVU_MADDAw<1,1> , mVU_MSUBAw<1,1>,
|
||||||
|
mVU_ITOF15<1,1> , mVU_FTOI15<1,1> , mVU_MULAw<1,1> , mVU_CLIP<1,1>,
|
||||||
|
mVU_MADDAi<1,1> , mVU_MSUBAi<1,1> , mVUunknown<1,1> , mVU_NOP<1,1>,
|
||||||
|
mVUunknown<1,1> , mVUunknown<1,1> , mVUunknown<1,1> , mVUunknown<1,1>,
|
||||||
|
mVUunknown<1,1> , mVUunknown<1,1> , mVUunknown<1,1> , mVUunknown<1,1>,
|
||||||
|
mVUunknown<1,1> , mVUunknown<1,1> , mVUunknown<1,1> , mVUunknown<1,1>,
|
||||||
|
mVUunknown<1,1> , mVUunknown<1,1> , mVUunknown<1,1> , mVUunknown<1,1>,
|
||||||
|
mVUunknown<1,1> , mVUunknown<1,1> , mVUunknown<1,1> , mVUunknown<1,1>,
|
||||||
|
};
|
||||||
|
//------------------------------------------------------------------
|
||||||
|
|
||||||
|
//------------------------------------------------------------------
|
||||||
|
// Table Functions
|
||||||
|
//------------------------------------------------------------------
|
||||||
|
#define doTableStuff(tableName, args) { \
|
||||||
|
if (recPass) { \
|
||||||
|
if (vuIndex) tableName##11[ args ](); \
|
||||||
|
else tableName##01[ args ](); \
|
||||||
|
} \
|
||||||
|
else { \
|
||||||
|
if (vuIndex) tableName##10[ args ](); \
|
||||||
|
else tableName##00[ args ](); \
|
||||||
|
} \
|
||||||
}
|
}
|
||||||
|
|
||||||
#endif
|
microVUf(void) mVU_UPPER_FD_00() { doTableStuff(mVU_UPPER_FD_00_TABLE, ((mVUgetCode >> 6) & 0x1f)); }
|
||||||
|
microVUf(void) mVU_UPPER_FD_01() { doTableStuff(mVU_UPPER_FD_01_TABLE, ((mVUgetCode >> 6) & 0x1f)); }
|
||||||
|
microVUf(void) mVU_UPPER_FD_10() { doTableStuff(mVU_UPPER_FD_10_TABLE, ((mVUgetCode >> 6) & 0x1f)); }
|
||||||
|
microVUf(void) mVU_UPPER_FD_11() { doTableStuff(mVU_UPPER_FD_11_TABLE, ((mVUgetCode >> 6) & 0x1f)); }
|
||||||
|
microVUf(void) mVULowerOP() { doTableStuff(mVULowerOP_OPCODE, (mVUgetCode & 0x3f)); }
|
||||||
|
microVUf(void) mVULowerOP_T3_00() { doTableStuff(mVULowerOP_T3_00_OPCODE, ((mVUgetCode >> 6) & 0x1f)); }
|
||||||
|
microVUf(void) mVULowerOP_T3_01() { doTableStuff(mVULowerOP_T3_01_OPCODE, ((mVUgetCode >> 6) & 0x1f)); }
|
||||||
|
microVUf(void) mVULowerOP_T3_10() { doTableStuff(mVULowerOP_T3_10_OPCODE, ((mVUgetCode >> 6) & 0x1f)); }
|
||||||
|
microVUf(void) mVULowerOP_T3_11() { doTableStuff(mVULowerOP_T3_11_OPCODE, ((mVUgetCode >> 6) & 0x1f)); }
|
||||||
|
microVUf(void) mVUunknown() { SysPrintf("mVUunknown<%d,%d> : Unknown Micro VU opcode called\n", vuIndex, recPass); }
|
||||||
|
#endif //PCSX2_MICROVU
|
||||||
|
|
|
@ -18,178 +18,180 @@
|
||||||
|
|
||||||
#pragma once
|
#pragma once
|
||||||
|
|
||||||
|
#define microVUf(aType) template<int vuIndex, int recPass> aType
|
||||||
|
|
||||||
//------------------------------------------------------------------
|
//------------------------------------------------------------------
|
||||||
// Micro VU Micromode Upper instructions
|
// Micro VU Micromode Upper instructions
|
||||||
//------------------------------------------------------------------
|
//------------------------------------------------------------------
|
||||||
|
|
||||||
void mVU_ABS(VURegs *vuRegs, int info);
|
microVUf(void) mVU_ABS();
|
||||||
void mVU_ADD(VURegs *vuRegs, int info);
|
microVUf(void) mVU_ADD();
|
||||||
void mVU_ADDi(VURegs *vuRegs, int info);
|
microVUf(void) mVU_ADDi();
|
||||||
void mVU_ADDq(VURegs *vuRegs, int info);
|
microVUf(void) mVU_ADDq();
|
||||||
void mVU_ADDx(VURegs *vuRegs, int info);
|
microVUf(void) mVU_ADDx();
|
||||||
void mVU_ADDy(VURegs *vuRegs, int info);
|
microVUf(void) mVU_ADDy();
|
||||||
void mVU_ADDz(VURegs *vuRegs, int info);
|
microVUf(void) mVU_ADDz();
|
||||||
void mVU_ADDw(VURegs *vuRegs, int info);
|
microVUf(void) mVU_ADDw();
|
||||||
void mVU_ADDA(VURegs *vuRegs, int info);
|
microVUf(void) mVU_ADDA();
|
||||||
void mVU_ADDAi(VURegs *vuRegs, int info);
|
microVUf(void) mVU_ADDAi();
|
||||||
void mVU_ADDAq(VURegs *vuRegs, int info);
|
microVUf(void) mVU_ADDAq();
|
||||||
void mVU_ADDAx(VURegs *vuRegs, int info);
|
microVUf(void) mVU_ADDAx();
|
||||||
void mVU_ADDAy(VURegs *vuRegs, int info);
|
microVUf(void) mVU_ADDAy();
|
||||||
void mVU_ADDAz(VURegs *vuRegs, int info);
|
microVUf(void) mVU_ADDAz();
|
||||||
void mVU_ADDAw(VURegs *vuRegs, int info);
|
microVUf(void) mVU_ADDAw();
|
||||||
void mVU_SUB(VURegs *vuRegs, int info);
|
microVUf(void) mVU_SUB();
|
||||||
void mVU_SUBi(VURegs *vuRegs, int info);
|
microVUf(void) mVU_SUBi();
|
||||||
void mVU_SUBq(VURegs *vuRegs, int info);
|
microVUf(void) mVU_SUBq();
|
||||||
void mVU_SUBx(VURegs *vuRegs, int info);
|
microVUf(void) mVU_SUBx();
|
||||||
void mVU_SUBy(VURegs *vuRegs, int info);
|
microVUf(void) mVU_SUBy();
|
||||||
void mVU_SUBz(VURegs *vuRegs, int info);
|
microVUf(void) mVU_SUBz();
|
||||||
void mVU_SUBw(VURegs *vuRegs, int info);
|
microVUf(void) mVU_SUBw();
|
||||||
void mVU_SUBA(VURegs *vuRegs, int info);
|
microVUf(void) mVU_SUBA();
|
||||||
void mVU_SUBAi(VURegs *vuRegs, int info);
|
microVUf(void) mVU_SUBAi();
|
||||||
void mVU_SUBAq(VURegs *vuRegs, int info);
|
microVUf(void) mVU_SUBAq();
|
||||||
void mVU_SUBAx(VURegs *vuRegs, int info);
|
microVUf(void) mVU_SUBAx();
|
||||||
void mVU_SUBAy(VURegs *vuRegs, int info);
|
microVUf(void) mVU_SUBAy();
|
||||||
void mVU_SUBAz(VURegs *vuRegs, int info);
|
microVUf(void) mVU_SUBAz();
|
||||||
void mVU_SUBAw(VURegs *vuRegs, int info);
|
microVUf(void) mVU_SUBAw();
|
||||||
void mVU_MUL(VURegs *vuRegs, int info);
|
microVUf(void) mVU_MUL();
|
||||||
void mVU_MULi(VURegs *vuRegs, int info);
|
microVUf(void) mVU_MULi();
|
||||||
void mVU_MULq(VURegs *vuRegs, int info);
|
microVUf(void) mVU_MULq();
|
||||||
void mVU_MULx(VURegs *vuRegs, int info);
|
microVUf(void) mVU_MULx();
|
||||||
void mVU_MULy(VURegs *vuRegs, int info);
|
microVUf(void) mVU_MULy();
|
||||||
void mVU_MULz(VURegs *vuRegs, int info);
|
microVUf(void) mVU_MULz();
|
||||||
void mVU_MULw(VURegs *vuRegs, int info);
|
microVUf(void) mVU_MULw();
|
||||||
void mVU_MULA(VURegs *vuRegs, int info);
|
microVUf(void) mVU_MULA();
|
||||||
void mVU_MULAi(VURegs *vuRegs, int info);
|
microVUf(void) mVU_MULAi();
|
||||||
void mVU_MULAq(VURegs *vuRegs, int info);
|
microVUf(void) mVU_MULAq();
|
||||||
void mVU_MULAx(VURegs *vuRegs, int info);
|
microVUf(void) mVU_MULAx();
|
||||||
void mVU_MULAy(VURegs *vuRegs, int info);
|
microVUf(void) mVU_MULAy();
|
||||||
void mVU_MULAz(VURegs *vuRegs, int info);
|
microVUf(void) mVU_MULAz();
|
||||||
void mVU_MULAw(VURegs *vuRegs, int info);
|
microVUf(void) mVU_MULAw();
|
||||||
void mVU_MADD(VURegs *vuRegs, int info);
|
microVUf(void) mVU_MADD();
|
||||||
void mVU_MADDi(VURegs *vuRegs, int info);
|
microVUf(void) mVU_MADDi();
|
||||||
void mVU_MADDq(VURegs *vuRegs, int info);
|
microVUf(void) mVU_MADDq();
|
||||||
void mVU_MADDx(VURegs *vuRegs, int info);
|
microVUf(void) mVU_MADDx();
|
||||||
void mVU_MADDy(VURegs *vuRegs, int info);
|
microVUf(void) mVU_MADDy();
|
||||||
void mVU_MADDz(VURegs *vuRegs, int info);
|
microVUf(void) mVU_MADDz();
|
||||||
void mVU_MADDw(VURegs *vuRegs, int info);
|
microVUf(void) mVU_MADDw();
|
||||||
void mVU_MADDA(VURegs *vuRegs, int info);
|
microVUf(void) mVU_MADDA();
|
||||||
void mVU_MADDAi(VURegs *vuRegs, int info);
|
microVUf(void) mVU_MADDAi();
|
||||||
void mVU_MADDAq(VURegs *vuRegs, int info);
|
microVUf(void) mVU_MADDAq();
|
||||||
void mVU_MADDAx(VURegs *vuRegs, int info);
|
microVUf(void) mVU_MADDAx();
|
||||||
void mVU_MADDAy(VURegs *vuRegs, int info);
|
microVUf(void) mVU_MADDAy();
|
||||||
void mVU_MADDAz(VURegs *vuRegs, int info);
|
microVUf(void) mVU_MADDAz();
|
||||||
void mVU_MADDAw(VURegs *vuRegs, int info);
|
microVUf(void) mVU_MADDAw();
|
||||||
void mVU_MSUB(VURegs *vuRegs, int info);
|
microVUf(void) mVU_MSUB();
|
||||||
void mVU_MSUBi(VURegs *vuRegs, int info);
|
microVUf(void) mVU_MSUBi();
|
||||||
void mVU_MSUBq(VURegs *vuRegs, int info);
|
microVUf(void) mVU_MSUBq();
|
||||||
void mVU_MSUBx(VURegs *vuRegs, int info);
|
microVUf(void) mVU_MSUBx();
|
||||||
void mVU_MSUBy(VURegs *vuRegs, int info);
|
microVUf(void) mVU_MSUBy();
|
||||||
void mVU_MSUBz(VURegs *vuRegs, int info);
|
microVUf(void) mVU_MSUBz();
|
||||||
void mVU_MSUBw(VURegs *vuRegs, int info);
|
microVUf(void) mVU_MSUBw();
|
||||||
void mVU_MSUBA(VURegs *vuRegs, int info);
|
microVUf(void) mVU_MSUBA();
|
||||||
void mVU_MSUBAi(VURegs *vuRegs, int info);
|
microVUf(void) mVU_MSUBAi();
|
||||||
void mVU_MSUBAq(VURegs *vuRegs, int info);
|
microVUf(void) mVU_MSUBAq();
|
||||||
void mVU_MSUBAx(VURegs *vuRegs, int info);
|
microVUf(void) mVU_MSUBAx();
|
||||||
void mVU_MSUBAy(VURegs *vuRegs, int info);
|
microVUf(void) mVU_MSUBAy();
|
||||||
void mVU_MSUBAz(VURegs *vuRegs, int info);
|
microVUf(void) mVU_MSUBAz();
|
||||||
void mVU_MSUBAw(VURegs *vuRegs, int info);
|
microVUf(void) mVU_MSUBAw();
|
||||||
void mVU_MAX(VURegs *vuRegs, int info);
|
microVUf(void) mVU_MAX();
|
||||||
void mVU_MAXi(VURegs *vuRegs, int info);
|
microVUf(void) mVU_MAXi();
|
||||||
void mVU_MAXx(VURegs *vuRegs, int info);
|
microVUf(void) mVU_MAXx();
|
||||||
void mVU_MAXy(VURegs *vuRegs, int info);
|
microVUf(void) mVU_MAXy();
|
||||||
void mVU_MAXz(VURegs *vuRegs, int info);
|
microVUf(void) mVU_MAXz();
|
||||||
void mVU_MAXw(VURegs *vuRegs, int info);
|
microVUf(void) mVU_MAXw();
|
||||||
void mVU_MINI(VURegs *vuRegs, int info);
|
microVUf(void) mVU_MINI();
|
||||||
void mVU_MINIi(VURegs *vuRegs, int info);
|
microVUf(void) mVU_MINIi();
|
||||||
void mVU_MINIx(VURegs *vuRegs, int info);
|
microVUf(void) mVU_MINIx();
|
||||||
void mVU_MINIy(VURegs *vuRegs, int info);
|
microVUf(void) mVU_MINIy();
|
||||||
void mVU_MINIz(VURegs *vuRegs, int info);
|
microVUf(void) mVU_MINIz();
|
||||||
void mVU_MINIw(VURegs *vuRegs, int info);
|
microVUf(void) mVU_MINIw();
|
||||||
void mVU_OPMULA(VURegs *vuRegs, int info);
|
microVUf(void) mVU_OPMULA();
|
||||||
void mVU_OPMSUB(VURegs *vuRegs, int info);
|
microVUf(void) mVU_OPMSUB();
|
||||||
void mVU_NOP(VURegs *vuRegs, int info);
|
microVUf(void) mVU_NOP();
|
||||||
void mVU_FTOI0(VURegs *vuRegs, int info);
|
microVUf(void) mVU_FTOI0();
|
||||||
void mVU_FTOI4(VURegs *vuRegs, int info);
|
microVUf(void) mVU_FTOI4();
|
||||||
void mVU_FTOI12(VURegs *vuRegs, int info);
|
microVUf(void) mVU_FTOI12();
|
||||||
void mVU_FTOI15(VURegs *vuRegs, int info);
|
microVUf(void) mVU_FTOI15();
|
||||||
void mVU_ITOF0(VURegs *vuRegs, int info);
|
microVUf(void) mVU_ITOF0();
|
||||||
void mVU_ITOF4(VURegs *vuRegs, int info);
|
microVUf(void) mVU_ITOF4();
|
||||||
void mVU_ITOF12(VURegs *vuRegs, int info);
|
microVUf(void) mVU_ITOF12();
|
||||||
void mVU_ITOF15(VURegs *vuRegs, int info);
|
microVUf(void) mVU_ITOF15();
|
||||||
void mVU_CLIP(VURegs *vuRegs, int info);
|
microVUf(void) mVU_CLIP();
|
||||||
|
|
||||||
//------------------------------------------------------------------
|
//------------------------------------------------------------------
|
||||||
// Micro VU Micromode Lower instructions
|
// Micro VU Micromode Lower instructions
|
||||||
//------------------------------------------------------------------
|
//------------------------------------------------------------------
|
||||||
|
|
||||||
void mVU_DIV(VURegs *vuRegs, int info);
|
microVUf(void) mVU_DIV();
|
||||||
void mVU_SQRT(VURegs *vuRegs, int info);
|
microVUf(void) mVU_SQRT();
|
||||||
void mVU_RSQRT(VURegs *vuRegs, int info);
|
microVUf(void) mVU_RSQRT();
|
||||||
void mVU_IADD(VURegs *vuRegs, int info);
|
microVUf(void) mVU_IADD();
|
||||||
void mVU_IADDI(VURegs *vuRegs, int info);
|
microVUf(void) mVU_IADDI();
|
||||||
void mVU_IADDIU(VURegs *vuRegs, int info);
|
microVUf(void) mVU_IADDIU();
|
||||||
void mVU_IAND(VURegs *vuRegs, int info);
|
microVUf(void) mVU_IAND();
|
||||||
void mVU_IOR(VURegs *vuRegs, int info);
|
microVUf(void) mVU_IOR();
|
||||||
void mVU_ISUB(VURegs *vuRegs, int info);
|
microVUf(void) mVU_ISUB();
|
||||||
void mVU_ISUBIU(VURegs *vuRegs, int info);
|
microVUf(void) mVU_ISUBIU();
|
||||||
void mVU_MOVE(VURegs *vuRegs, int info);
|
microVUf(void) mVU_MOVE();
|
||||||
void mVU_MFIR(VURegs *vuRegs, int info);
|
microVUf(void) mVU_MFIR();
|
||||||
void mVU_MTIR(VURegs *vuRegs, int info);
|
microVUf(void) mVU_MTIR();
|
||||||
void mVU_MR32(VURegs *vuRegs, int info);
|
microVUf(void) mVU_MR32();
|
||||||
void mVU_LQ(VURegs *vuRegs, int info);
|
microVUf(void) mVU_LQ();
|
||||||
void mVU_LQD(VURegs *vuRegs, int info);
|
microVUf(void) mVU_LQD();
|
||||||
void mVU_LQI(VURegs *vuRegs, int info);
|
microVUf(void) mVU_LQI();
|
||||||
void mVU_SQ(VURegs *vuRegs, int info);
|
microVUf(void) mVU_SQ();
|
||||||
void mVU_SQD(VURegs *vuRegs, int info);
|
microVUf(void) mVU_SQD();
|
||||||
void mVU_SQI(VURegs *vuRegs, int info);
|
microVUf(void) mVU_SQI();
|
||||||
void mVU_ILW(VURegs *vuRegs, int info);
|
microVUf(void) mVU_ILW();
|
||||||
void mVU_ISW(VURegs *vuRegs, int info);
|
microVUf(void) mVU_ISW();
|
||||||
void mVU_ILWR(VURegs *vuRegs, int info);
|
microVUf(void) mVU_ILWR();
|
||||||
void mVU_ISWR(VURegs *vuRegs, int info);
|
microVUf(void) mVU_ISWR();
|
||||||
void mVU_LOI(VURegs *vuRegs, int info);
|
microVUf(void) mVU_LOI();
|
||||||
void mVU_RINIT(VURegs *vuRegs, int info);
|
microVUf(void) mVU_RINIT();
|
||||||
void mVU_RGET(VURegs *vuRegs, int info);
|
microVUf(void) mVU_RGET();
|
||||||
void mVU_RNEXT(VURegs *vuRegs, int info);
|
microVUf(void) mVU_RNEXT();
|
||||||
void mVU_RXOR(VURegs *vuRegs, int info);
|
microVUf(void) mVU_RXOR();
|
||||||
void mVU_WAITQ(VURegs *vuRegs, int info);
|
microVUf(void) mVU_WAITQ();
|
||||||
void mVU_FSAND(VURegs *vuRegs, int info);
|
microVUf(void) mVU_FSAND();
|
||||||
void mVU_FSEQ(VURegs *vuRegs, int info);
|
microVUf(void) mVU_FSEQ();
|
||||||
void mVU_FSOR(VURegs *vuRegs, int info);
|
microVUf(void) mVU_FSOR();
|
||||||
void mVU_FSSET(VURegs *vuRegs, int info);
|
microVUf(void) mVU_FSSET();
|
||||||
void mVU_FMAND(VURegs *vuRegs, int info);
|
microVUf(void) mVU_FMAND();
|
||||||
void mVU_FMEQ(VURegs *vuRegs, int info);
|
microVUf(void) mVU_FMEQ();
|
||||||
void mVU_FMOR(VURegs *vuRegs, int info);
|
microVUf(void) mVU_FMOR();
|
||||||
void mVU_FCAND(VURegs *vuRegs, int info);
|
microVUf(void) mVU_FCAND();
|
||||||
void mVU_FCEQ(VURegs *vuRegs, int info);
|
microVUf(void) mVU_FCEQ();
|
||||||
void mVU_FCOR(VURegs *vuRegs, int info);
|
microVUf(void) mVU_FCOR();
|
||||||
void mVU_FCSET(VURegs *vuRegs, int info);
|
microVUf(void) mVU_FCSET();
|
||||||
void mVU_FCGET(VURegs *vuRegs, int info);
|
microVUf(void) mVU_FCGET();
|
||||||
void mVU_IBEQ(VURegs *vuRegs, int info);
|
microVUf(void) mVU_IBEQ();
|
||||||
void mVU_IBGEZ(VURegs *vuRegs, int info);
|
microVUf(void) mVU_IBGEZ();
|
||||||
void mVU_IBGTZ(VURegs *vuRegs, int info);
|
microVUf(void) mVU_IBGTZ();
|
||||||
void mVU_IBLTZ(VURegs *vuRegs, int info);
|
microVUf(void) mVU_IBLTZ();
|
||||||
void mVU_IBLEZ(VURegs *vuRegs, int info);
|
microVUf(void) mVU_IBLEZ();
|
||||||
void mVU_IBNE(VURegs *vuRegs, int info);
|
microVUf(void) mVU_IBNE();
|
||||||
void mVU_B(VURegs *vuRegs, int info);
|
microVUf(void) mVU_B();
|
||||||
void mVU_BAL(VURegs *vuRegs, int info);
|
microVUf(void) mVU_BAL();
|
||||||
void mVU_JR(VURegs *vuRegs, int info);
|
microVUf(void) mVU_JR();
|
||||||
void mVU_JALR(VURegs *vuRegs, int info);
|
microVUf(void) mVU_JALR();
|
||||||
void mVU_MFP(VURegs *vuRegs, int info);
|
microVUf(void) mVU_MFP();
|
||||||
void mVU_WAITP(VURegs *vuRegs, int info);
|
microVUf(void) mVU_WAITP();
|
||||||
void mVU_ESADD(VURegs *vuRegs, int info);
|
microVUf(void) mVU_ESADD();
|
||||||
void mVU_ERSADD(VURegs *vuRegs, int info);
|
microVUf(void) mVU_ERSADD();
|
||||||
void mVU_ELENG(VURegs *vuRegs, int info);
|
microVUf(void) mVU_ELENG();
|
||||||
void mVU_ERLENG(VURegs *vuRegs, int info);
|
microVUf(void) mVU_ERLENG();
|
||||||
void mVU_EATANxy(VURegs *vuRegs, int info);
|
microVUf(void) mVU_EATANxy();
|
||||||
void mVU_EATANxz(VURegs *vuRegs, int info);
|
microVUf(void) mVU_EATANxz();
|
||||||
void mVU_ESUM(VURegs *vuRegs, int info);
|
microVUf(void) mVU_ESUM();
|
||||||
void mVU_ERCPR(VURegs *vuRegs, int info);
|
microVUf(void) mVU_ERCPR();
|
||||||
void mVU_ESQRT(VURegs *vuRegs, int info);
|
microVUf(void) mVU_ESQRT();
|
||||||
void mVU_ERSQRT(VURegs *vuRegs, int info);
|
microVUf(void) mVU_ERSQRT();
|
||||||
void mVU_ESIN(VURegs *vuRegs, int info);
|
microVUf(void) mVU_ESIN();
|
||||||
void mVU_EATAN(VURegs *vuRegs, int info);
|
microVUf(void) mVU_EATAN();
|
||||||
void mVU_EEXP(VURegs *vuRegs, int info);
|
microVUf(void) mVU_EEXP();
|
||||||
void mVU_XGKICK(VURegs *vuRegs, int info);
|
microVUf(void) mVU_XGKICK();
|
||||||
void mVU_XTOP(VURegs *vuRegs, int info);
|
microVUf(void) mVU_XTOP();
|
||||||
void mVU_XITOP(VURegs *vuRegs, int info);
|
microVUf(void) mVU_XITOP();
|
||||||
void mVU_XTOP( VURegs *VU , int info);
|
|
||||||
|
|
|
@ -15,8 +15,10 @@
|
||||||
* along with this program; if not, write to the Free Software
|
* along with this program; if not, write to the Free Software
|
||||||
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
|
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
|
||||||
*/
|
*/
|
||||||
|
#pragma once
|
||||||
#include "PrecompiledHeader.h"
|
#include "PrecompiledHeader.h"
|
||||||
|
#include "microVU.h"
|
||||||
|
#ifdef PCSX2_MICROVU
|
||||||
|
|
||||||
/*
|
/*
|
||||||
Cotton's Notes on how things will work (*experimental*, subject to change if I get different ideas):
|
Cotton's Notes on how things will work (*experimental*, subject to change if I get different ideas):
|
||||||
|
@ -68,4 +70,105 @@ The biggest problem I think I'll have is xgkick opcode having variable timing/st
|
||||||
Other Notes:
|
Other Notes:
|
||||||
These notes are mostly to help me (cottonvibes) remember good ideas and to help confused devs to
|
These notes are mostly to help me (cottonvibes) remember good ideas and to help confused devs to
|
||||||
have an idea of how things work. Right now its all theoretical and I'll change things once implemented ;p
|
have an idea of how things work. Right now its all theoretical and I'll change things once implemented ;p
|
||||||
*/
|
*/
|
||||||
|
|
||||||
|
//------------------------------------------------------------------
|
||||||
|
// Micro VU Micromode Upper instructions
|
||||||
|
//------------------------------------------------------------------
|
||||||
|
|
||||||
|
microVUf(void) mVU_ABS(){}
|
||||||
|
microVUf(void) mVU_ADD(){}
|
||||||
|
microVUf(void) mVU_ADDi(){}
|
||||||
|
microVUf(void) mVU_ADDq(){}
|
||||||
|
microVUf(void) mVU_ADDx(){}
|
||||||
|
microVUf(void) mVU_ADDy(){}
|
||||||
|
microVUf(void) mVU_ADDz(){}
|
||||||
|
microVUf(void) mVU_ADDw(){}
|
||||||
|
microVUf(void) mVU_ADDA(){}
|
||||||
|
microVUf(void) mVU_ADDAi(){}
|
||||||
|
microVUf(void) mVU_ADDAq(){}
|
||||||
|
microVUf(void) mVU_ADDAx(){}
|
||||||
|
microVUf(void) mVU_ADDAy(){}
|
||||||
|
microVUf(void) mVU_ADDAz(){}
|
||||||
|
microVUf(void) mVU_ADDAw(){}
|
||||||
|
microVUf(void) mVU_SUB(){}
|
||||||
|
microVUf(void) mVU_SUBi(){}
|
||||||
|
microVUf(void) mVU_SUBq(){}
|
||||||
|
microVUf(void) mVU_SUBx(){}
|
||||||
|
microVUf(void) mVU_SUBy(){}
|
||||||
|
microVUf(void) mVU_SUBz(){}
|
||||||
|
microVUf(void) mVU_SUBw(){}
|
||||||
|
microVUf(void) mVU_SUBA(){}
|
||||||
|
microVUf(void) mVU_SUBAi(){}
|
||||||
|
microVUf(void) mVU_SUBAq(){}
|
||||||
|
microVUf(void) mVU_SUBAx(){}
|
||||||
|
microVUf(void) mVU_SUBAy(){}
|
||||||
|
microVUf(void) mVU_SUBAz(){}
|
||||||
|
microVUf(void) mVU_SUBAw(){}
|
||||||
|
microVUf(void) mVU_MUL(){}
|
||||||
|
microVUf(void) mVU_MULi(){}
|
||||||
|
microVUf(void) mVU_MULq(){}
|
||||||
|
microVUf(void) mVU_MULx(){}
|
||||||
|
microVUf(void) mVU_MULy(){}
|
||||||
|
microVUf(void) mVU_MULz(){}
|
||||||
|
microVUf(void) mVU_MULw(){}
|
||||||
|
microVUf(void) mVU_MULA(){}
|
||||||
|
microVUf(void) mVU_MULAi(){}
|
||||||
|
microVUf(void) mVU_MULAq(){}
|
||||||
|
microVUf(void) mVU_MULAx(){}
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microVUf(void) mVU_MULAy(){}
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microVUf(void) mVU_MULAz(){}
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microVUf(void) mVU_MULAw(){}
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microVUf(void) mVU_MADD(){}
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microVUf(void) mVU_MADDi(){}
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microVUf(void) mVU_MADDq(){}
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microVUf(void) mVU_MADDx(){}
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microVUf(void) mVU_MADDy(){}
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microVUf(void) mVU_MADDz(){}
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microVUf(void) mVU_MADDw(){}
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microVUf(void) mVU_MADDA(){}
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microVUf(void) mVU_MADDAi(){}
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microVUf(void) mVU_MADDAq(){}
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microVUf(void) mVU_MADDAx(){}
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microVUf(void) mVU_MADDAy(){}
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microVUf(void) mVU_MADDAz(){}
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microVUf(void) mVU_MADDAw(){}
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microVUf(void) mVU_MSUB(){}
|
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microVUf(void) mVU_MSUBi(){}
|
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microVUf(void) mVU_MSUBq(){}
|
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microVUf(void) mVU_MSUBx(){}
|
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microVUf(void) mVU_MSUBy(){}
|
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microVUf(void) mVU_MSUBz(){}
|
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microVUf(void) mVU_MSUBw(){}
|
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microVUf(void) mVU_MSUBA(){}
|
||||||
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microVUf(void) mVU_MSUBAi(){}
|
||||||
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microVUf(void) mVU_MSUBAq(){}
|
||||||
|
microVUf(void) mVU_MSUBAx(){}
|
||||||
|
microVUf(void) mVU_MSUBAy(){}
|
||||||
|
microVUf(void) mVU_MSUBAz(){}
|
||||||
|
microVUf(void) mVU_MSUBAw(){}
|
||||||
|
microVUf(void) mVU_MAX(){}
|
||||||
|
microVUf(void) mVU_MAXi(){}
|
||||||
|
microVUf(void) mVU_MAXx(){}
|
||||||
|
microVUf(void) mVU_MAXy(){}
|
||||||
|
microVUf(void) mVU_MAXz(){}
|
||||||
|
microVUf(void) mVU_MAXw(){}
|
||||||
|
microVUf(void) mVU_MINI(){}
|
||||||
|
microVUf(void) mVU_MINIi(){}
|
||||||
|
microVUf(void) mVU_MINIx(){}
|
||||||
|
microVUf(void) mVU_MINIy(){}
|
||||||
|
microVUf(void) mVU_MINIz(){}
|
||||||
|
microVUf(void) mVU_MINIw(){}
|
||||||
|
microVUf(void) mVU_OPMULA(){}
|
||||||
|
microVUf(void) mVU_OPMSUB(){}
|
||||||
|
microVUf(void) mVU_NOP(){}
|
||||||
|
microVUf(void) mVU_FTOI0(){}
|
||||||
|
microVUf(void) mVU_FTOI4(){}
|
||||||
|
microVUf(void) mVU_FTOI12(){}
|
||||||
|
microVUf(void) mVU_FTOI15(){}
|
||||||
|
microVUf(void) mVU_ITOF0(){}
|
||||||
|
microVUf(void) mVU_ITOF4(){}
|
||||||
|
microVUf(void) mVU_ITOF12(){}
|
||||||
|
microVUf(void) mVU_ITOF15(){}
|
||||||
|
microVUf(void) mVU_CLIP(){}
|
||||||
|
#endif //PCSX2_MICROVU
|
||||||
|
|
Loading…
Reference in New Issue