mirror of https://github.com/PCSX2/pcsx2.git
Merge pull request #541 from TheLastRar/master
DEV9ghzdrk - thread safer calls to DEV9irq
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c3dc51826f
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@ -702,6 +702,7 @@ typedef void (CALLBACK* _DEV9writeDMA8Mem)(u32 *pMem, int size);
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#endif
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typedef void (CALLBACK* _DEV9irqCallback)(DEV9callback callback);
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typedef DEV9handler (CALLBACK* _DEV9irqHandler)(void);
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typedef void (CALLBACK* _DEV9async)(u32 cycles);
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// USB
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// NOTE: The read/write functions CANNOT use XMM/MMX regs
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@ -820,6 +821,7 @@ extern _DEV9writeDMA8Mem DEV9writeDMA8Mem;
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#endif
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extern _DEV9irqCallback DEV9irqCallback;
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extern _DEV9irqHandler DEV9irqHandler;
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extern _DEV9async DEV9async;
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// USB
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extern _USBopen USBopen;
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@ -453,7 +453,10 @@ void psxRcntUpdate()
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else c -= difference;
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psxNextCounter = c;
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}
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if (DEV9async)
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{
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DEV9async(1);
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}
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if(USBasync)
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{
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const s32 difference = psxRegs.cycle - psxCounters[7].sCycleT;
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@ -320,6 +320,7 @@ _DEV9writeDMA8Mem DEV9writeDMA8Mem;
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#endif
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_DEV9irqCallback DEV9irqCallback;
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_DEV9irqHandler DEV9irqHandler;
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_DEV9async DEV9async;
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// USB
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_USBopen USBopen;
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@ -630,6 +631,7 @@ static const LegacyApi_ReqMethod s_MethMessReq_DEV9[] =
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static const LegacyApi_OptMethod s_MethMessOpt_DEV9[] =
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{
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{ "DEV9async", (vMeth**)&DEV9async },
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{ NULL }
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};
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@ -600,6 +600,10 @@ void CALLBACK DEV9irqCallback(void (*callback)(int cycles)) {
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DEV9irq = callback;
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}
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void CALLBACK DEV9async(u32 cycles)
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{
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smap_async(cycles);
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}
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// extended funcs
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@ -24,5 +24,6 @@ EXPORTS
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DEV9about @19
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DEV9irqCallback @20
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DEV9irqHandler @21
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DEV9async @22
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DEV9setSettingsDir
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@ -23,6 +23,7 @@
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#include <fcntl.h>
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#include <windows.h>
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#include <stdarg.h>
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#include <mutex>
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#include "smap.h"
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#include "net.h"
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@ -31,6 +32,9 @@
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#include "tap.h"
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bool has_link=true;
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volatile bool fireIntR = false;
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std::mutex frame_counter_mutex;
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std::mutex reset_mutex;
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/*
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#define SMAP_BASE 0xb0000000
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#define SMAP_REG8(Offset) (*(u8 volatile*)(SMAP_BASE+(Offset)))
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@ -81,6 +85,7 @@ bool rx_fifo_can_rx()
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//we can recv a packet !
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return true;
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}
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void rx_process(NetPacket* pk)
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{
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if (!rx_fifo_can_rx())
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@ -107,6 +112,7 @@ void rx_process(NetPacket* pk)
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}
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//increase RXBD
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std::unique_lock<std::mutex> reset_lock(reset_mutex);
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dev9.rxbdi++;
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dev9.rxbdi&=(SMAP_BD_SIZE/8)-1;
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@ -116,9 +122,13 @@ void rx_process(NetPacket* pk)
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pbd->ctrl_stat&= ~SMAP_BD_RX_EMPTY;
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//increase frame count
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std::unique_lock<std::mutex> counter_lock(frame_counter_mutex);
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dev9Ru8(SMAP_R_RXFIFO_FRAME_CNT)++;
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counter_lock.unlock();
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reset_lock.unlock();
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//spams// emu_printf("Got packet, %d bytes (%d fifo)\n", pk->size,bytes);
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_DEV9irq(SMAP_INTR_RXEND,0);//now ? or when the fifo is full ? i guess now atm
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fireIntR = true;
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//_DEV9irq(SMAP_INTR_RXEND,0);//now ? or when the fifo is full ? i guess now atm
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//note that this _is_ wrong since the IOP interrupt system is not thread safe.. but nothing i can do about that
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}
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@ -528,6 +538,8 @@ u32 CALLBACK smap_read32(u32 addr)
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}
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void CALLBACK smap_write8(u32 addr, u8 value)
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{
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std::unique_lock<std::mutex> reset_lock(reset_mutex, std::defer_lock);
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std::unique_lock<std::mutex> counter_lock(frame_counter_mutex, std::defer_lock);
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switch(addr)
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{
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case SMAP_R_TXFIFO_FRAME_INC:
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@ -539,10 +551,12 @@ void CALLBACK smap_write8(u32 addr, u8 value)
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case SMAP_R_RXFIFO_FRAME_DEC:
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DEV9_LOG("SMAP_R_RXFIFO_FRAME_DEC 8bit write %x\n", value);
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counter_lock.lock();
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dev9Ru8(addr) = value;
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{
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dev9Ru8(SMAP_R_RXFIFO_FRAME_CNT)--;
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}
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counter_lock.unlock();
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return;
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case SMAP_R_TXFIFO_CTRL:
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@ -563,11 +577,15 @@ void CALLBACK smap_write8(u32 addr, u8 value)
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DEV9_LOG("SMAP_R_RXFIFO_CTRL 8bit write %x\n", value);
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if(value&SMAP_RXFIFO_RESET)
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{
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reset_lock.lock(); //lock reset mutex 1st
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counter_lock.lock();
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dev9.rxbdi=0;
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dev9.rxfifo_wr_ptr=0;
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dev9Ru8(SMAP_R_RXFIFO_FRAME_CNT)=0;
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dev9Ru32(SMAP_R_RXFIFO_RD_PTR)=0;
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dev9Ru32(SMAP_R_RXFIFO_SIZE)=16384;
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reset_lock.unlock();
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counter_lock.unlock();
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}
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value&= ~SMAP_RXFIFO_RESET;
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dev9Ru8(addr) = value;
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@ -840,3 +858,13 @@ void CALLBACK smap_writeDMA8Mem(u32* pMem, int size)
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}
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}
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void CALLBACK smap_async(u32 cycles)
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{
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if (fireIntR)
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{
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fireIntR = false;
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//Is this used to signal each individual packet, or just when there are packets in the RX fifo?
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//I think it just signals when there are packets in the RX fifo
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_DEV9irq(SMAP_INTR_RXEND, 0); //Make the call to _DEV9irq in a thread safe way
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}
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}
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@ -25,4 +25,5 @@ void CALLBACK smap_write16(u32 addr, u16 value);
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void CALLBACK smap_write32(u32 addr, u32 value);
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void CALLBACK smap_readDMA8Mem(u32 *pMem, int size);
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void CALLBACK smap_writeDMA8Mem(u32 *pMem, int size);
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void CALLBACK smap_writeDMA8Mem(u32 *pMem, int size);
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void CALLBACK smap_async(u32 cycles);
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