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microVU: 

Saw that SSE4.1 has ptest, and I wanted to try it out xD
untested though cuz I don't have an SSE4.1 cpu :)


git-svn-id: http://pcsx2.googlecode.com/svn/trunk@1585 96395faa-99c1-11dd-bbfe-3dabce05a288
This commit is contained in:
cottonvibes 2009-07-30 01:35:25 +00:00
parent a0828bc8f9
commit b470a9ae31
3 changed files with 19 additions and 12 deletions
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1
pcsx2/x86/ix86/ix86_legacy_instructions.h
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@ -1364,6 +1364,7 @@ extern void SSE4_PMINSD_M128_to_XMM(x86SSERegType to, uptr from);
extern void SSE4_PMAXUD_M128_to_XMM(x86SSERegType to, uptr from); extern void SSE4_PMAXUD_M128_to_XMM(x86SSERegType to, uptr from);
extern void SSE4_PMINUD_M128_to_XMM(x86SSERegType to, uptr from); extern void SSE4_PMINUD_M128_to_XMM(x86SSERegType to, uptr from);
extern void SSE4_PMULDQ_XMM_to_XMM(x86SSERegType to, x86SSERegType from); extern void SSE4_PMULDQ_XMM_to_XMM(x86SSERegType to, x86SSERegType from);
extern void SSE4_PTEST_XMM_to_XMM(x86SSERegType to, x86SSERegType from);
//********************* //*********************
// 3DNOW instructions * // 3DNOW instructions *

1
pcsx2/x86/ix86/ix86_legacy_sse.cpp
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@ -374,6 +374,7 @@ emitterT void SSE4_BLENDVPS_XMM_to_XMM(x86SSERegType to, x86SSERegType from) {
emitterT void SSE4_BLENDVPS_M128_to_XMM(x86SSERegType to, uptr from) { xBLEND.VPS( xRegisterSSE(to), (void*)from ); } emitterT void SSE4_BLENDVPS_M128_to_XMM(x86SSERegType to, uptr from) { xBLEND.VPS( xRegisterSSE(to), (void*)from ); }
emitterT void SSE4_PMOVSXDQ_XMM_to_XMM(x86SSERegType to, x86SSERegType from) { xPMOVSX.DQ( xRegisterSSE(to), xRegisterSSE(from) ); } emitterT void SSE4_PMOVSXDQ_XMM_to_XMM(x86SSERegType to, x86SSERegType from) { xPMOVSX.DQ( xRegisterSSE(to), xRegisterSSE(from) ); }
emitterT void SSE4_PTEST_XMM_to_XMM(x86SSERegType to, x86SSERegType from) { xPTEST(xRegisterSSE(to), xRegisterSSE(from)); }
emitterT void SSE_LDMXCSR( uptr from ) { xLDMXCSR( (u32*)from ); } emitterT void SSE_LDMXCSR( uptr from ) { xLDMXCSR( (u32*)from ); }

29
pcsx2/x86/microVU_Lower.inl
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@ -26,20 +26,25 @@
// DIV/SQRT/RSQRT // DIV/SQRT/RSQRT
//------------------------------------------------------------------ //------------------------------------------------------------------
#define testZero(xmmReg, xmmTemp, gprTemp) { \ // Test if Vector is +/- Zero
SSE_XORPS_XMM_to_XMM(xmmTemp, xmmTemp); /* Clear xmmTemp (make it 0) */ \ #define testZero(xmmReg, xmmTemp, gprTemp) { \
SSE_CMPEQPS_XMM_to_XMM(xmmTemp, xmmReg); /* Set all F's if zero */ \ SSE_XORPS_XMM_to_XMM(xmmTemp, xmmTemp); \
SSE_MOVMSKPS_XMM_to_R32(gprTemp, xmmTemp); /* Move the sign bits */ \ SSE_CMPEQSS_XMM_to_XMM(xmmTemp, xmmReg); \
TEST32ItoR(gprTemp, 1); /* Test "Is Zero" bit */ \ if (!cpucaps.hasStreamingSIMD4Extensions) { \
SSE_MOVMSKPS_XMM_to_R32(gprTemp, xmmTemp); \
TEST32ItoR(gprTemp, 1); \
} \
else SSE4_PTEST_XMM_to_XMM(xmmTemp, xmmTemp); \
} }
#define testNeg(xmmReg, gprTemp, aJump) { \ // Test if Vector is Negative (Set Flags and Makes Positive)
SSE_MOVMSKPS_XMM_to_R32(gprTemp, xmmReg); \ #define testNeg(xmmReg, gprTemp, aJump) { \
TEST32ItoR(gprTemp, 1); /* Check sign bit */ \ SSE_MOVMSKPS_XMM_to_R32(gprTemp, xmmReg); \
aJump = JZ8(0); /* Skip if positive */ \ TEST32ItoR(gprTemp, 1); \
MOV32ItoM((uptr)&mVU->divFlag, divI); /* Set Invalid Flags */ \ aJump = JZ8(0); \
SSE_ANDPS_M128_to_XMM(xmmReg, (uptr)mVU_absclip); /* Abs(xmmReg) */ \ MOV32ItoM((uptr)&mVU->divFlag, divI); \
x86SetJ8(aJump); \ SSE_ANDPS_M128_to_XMM(xmmReg, (uptr)mVU_absclip); \
x86SetJ8(aJump); \
} }
mVUop(mVU_DIV) { mVUop(mVU_DIV) {