diff --git a/pcsx2/x86/ix86/ix86_legacy_instructions.h b/pcsx2/x86/ix86/ix86_legacy_instructions.h
index 1fe98cb92a..a026464e66 100644
--- a/pcsx2/x86/ix86/ix86_legacy_instructions.h
+++ b/pcsx2/x86/ix86/ix86_legacy_instructions.h
@@ -1364,6 +1364,7 @@ extern void SSE4_PMINSD_M128_to_XMM(x86SSERegType to, uptr from);
 extern void SSE4_PMAXUD_M128_to_XMM(x86SSERegType to, uptr from);
 extern void SSE4_PMINUD_M128_to_XMM(x86SSERegType to, uptr from);
 extern void SSE4_PMULDQ_XMM_to_XMM(x86SSERegType to, x86SSERegType from);
+extern void SSE4_PTEST_XMM_to_XMM(x86SSERegType to, x86SSERegType from);
 
 //*********************
 // 3DNOW instructions * 
diff --git a/pcsx2/x86/ix86/ix86_legacy_sse.cpp b/pcsx2/x86/ix86/ix86_legacy_sse.cpp
index 66074ca087..684316edaa 100644
--- a/pcsx2/x86/ix86/ix86_legacy_sse.cpp
+++ b/pcsx2/x86/ix86/ix86_legacy_sse.cpp
@@ -374,6 +374,7 @@ emitterT void SSE4_BLENDVPS_XMM_to_XMM(x86SSERegType to, x86SSERegType from)			{
 emitterT void SSE4_BLENDVPS_M128_to_XMM(x86SSERegType to, uptr from)					{ xBLEND.VPS( xRegisterSSE(to), (void*)from ); }
 
 emitterT void SSE4_PMOVSXDQ_XMM_to_XMM(x86SSERegType to, x86SSERegType from)			{ xPMOVSX.DQ( xRegisterSSE(to), xRegisterSSE(from) ); }
+emitterT void SSE4_PTEST_XMM_to_XMM(x86SSERegType to, x86SSERegType from)				{ xPTEST(xRegisterSSE(to), xRegisterSSE(from)); }
 
 emitterT void SSE_LDMXCSR( uptr from ) { xLDMXCSR( (u32*)from ); }
 
diff --git a/pcsx2/x86/microVU_Lower.inl b/pcsx2/x86/microVU_Lower.inl
index fb017f23e8..d760b0c4a7 100644
--- a/pcsx2/x86/microVU_Lower.inl
+++ b/pcsx2/x86/microVU_Lower.inl
@@ -26,20 +26,25 @@
 // DIV/SQRT/RSQRT
 //------------------------------------------------------------------
 
-#define testZero(xmmReg, xmmTemp, gprTemp) {										\
-	SSE_XORPS_XMM_to_XMM(xmmTemp, xmmTemp);		/* Clear xmmTemp (make it 0) */		\
-	SSE_CMPEQPS_XMM_to_XMM(xmmTemp, xmmReg);	/* Set all F's if zero */			\
-	SSE_MOVMSKPS_XMM_to_R32(gprTemp, xmmTemp);	/* Move the sign bits */			\
-	TEST32ItoR(gprTemp, 1);						/* Test "Is Zero" bit */			\
+// Test if Vector is +/- Zero
+#define testZero(xmmReg, xmmTemp, gprTemp) {				\
+	SSE_XORPS_XMM_to_XMM(xmmTemp, xmmTemp);					\
+	SSE_CMPEQSS_XMM_to_XMM(xmmTemp, xmmReg);				\
+	if (!cpucaps.hasStreamingSIMD4Extensions) {				\
+		SSE_MOVMSKPS_XMM_to_R32(gprTemp, xmmTemp);			\
+		TEST32ItoR(gprTemp, 1);								\
+	}														\
+	else SSE4_PTEST_XMM_to_XMM(xmmTemp, xmmTemp);			\
 }
 
-#define testNeg(xmmReg, gprTemp, aJump) {											\
-	SSE_MOVMSKPS_XMM_to_R32(gprTemp, xmmReg);										\
-	TEST32ItoR(gprTemp, 1);								  /* Check sign bit */		\
-	aJump = JZ8(0);										  /* Skip if positive */	\
-		MOV32ItoM((uptr)&mVU->divFlag, divI);			  /* Set Invalid Flags */	\
-		SSE_ANDPS_M128_to_XMM(xmmReg, (uptr)mVU_absclip); /* Abs(xmmReg) */			\
-	x86SetJ8(aJump);																\
+// Test if Vector is Negative (Set Flags and Makes Positive)
+#define testNeg(xmmReg, gprTemp, aJump) {					\
+	SSE_MOVMSKPS_XMM_to_R32(gprTemp, xmmReg);				\
+	TEST32ItoR(gprTemp, 1);									\
+	aJump = JZ8(0);											\
+		MOV32ItoM((uptr)&mVU->divFlag, divI);				\
+		SSE_ANDPS_M128_to_XMM(xmmReg, (uptr)mVU_absclip);	\
+	x86SetJ8(aJump);										\
 }
 
 mVUop(mVU_DIV) {