-Bumped savestate version, forgot to do that in my last commit.

-Fixed a bug stopping GT4 running.
-VIF now waits if the VU is busy rather than spinning, causing huge slowdowns.
-Filled in some bits i missed

git-svn-id: http://pcsx2.googlecode.com/svn/trunk@5149 96395faa-99c1-11dd-bbfe-3dabce05a288

pcsx2/SaveState.h

@@ -24,7 +24,7 @@
 //  the lower 16 bit value.  IF the change is breaking of all compatibility with old
 //  states, increment the upper 16 bit value, and clear the lower 16 bits to 0.
 
-static const u32 g_SaveVersion = (0x9A06 << 16) | 0x0000;
+static const u32 g_SaveVersion = (0x9A07 << 16) | 0x0000;
 
 // this function is meant to be used in the place of GSfreeze, and provides a safe layer
 // between the GS saving function and the MTGS's needs. :)

pcsx2/VU0.cpp

@@ -29,6 +29,7 @@
 
 #include "R5900OpcodeTables.h"
 #include "VUmicro.h"
+#include "Vif_Dma.h"
 
 #define _Ft_ _Rt_
 #define _Fs_ _Rd_
@@ -164,6 +165,7 @@ void CTC2() {
 		case REG_CMSAR1: // REG_CMSAR1
 			if (!(VU0.VI[REG_VPU_STAT].UL & 0x100) ) {
 				vu1ExecMicro(cpuRegs.GPR.r[_Rt_].US[0]);	// Execute VU1 Micro SubRoutine
+				vif1VUFinish();
 			}
 			break;
 		default:

pcsx2/Vif0_Dma.cpp

@@ -157,6 +157,9 @@ __fi void vif0VUFinish()
 	{
 		vif0.waitforvu = false;
 		ExecuteVU(0);
+		//Make sure VIF0 isnt already scheduled to spin.
+		if(!(cpuRegs.interrupt & 0x1))
+			vif0Interrupt();
 	}
 	//DevCon.Warning("VU0 state cleared");
 }
@@ -194,7 +197,7 @@ __fi void vif0Interrupt()
 	if(vif0.waitforvu == true)
 	{
 		//DevCon.Warning("Waiting on VU0");
-		CPU_INT(DMAC_VIF0, 16);
+		//CPU_INT(DMAC_VIF0, 16);
 		return;
 	}
 	//Must go after the Stall, incase it's still in progress, GTC africa likes to see it still transferring.

pcsx2/Vif1_Dma.cpp

@@ -229,6 +229,14 @@ __fi void vif1VUFinish()
 	{
 		vif1.waitforvu = false;
 		ExecuteVU(1);
+		//Check if VIF is already scheduled to interrupt, if it's waiting, kick it :P
+		if((cpuRegs.interrupt & (1<<DMAC_VIF1 | 1 << DMAC_MFIFO_VIF)) == 0 && vif1ch.chcr.STR == true)
+		{
+			if(dmacRegs.ctrl.MFD == MFD_VIF1)
+				vifMFIFOInterrupt();
+			else
+				vif1Interrupt();
+		}
 	}
 	
 	//DevCon.Warning("VU1 state cleared");
@@ -269,7 +277,7 @@ __fi void vif1Interrupt()
 	if(vif1.waitforvu == true)
 	{
 		//DevCon.Warning("Waiting on VU1");
-		CPU_INT(DMAC_VIF1, 16);
+		//CPU_INT(DMAC_VIF1, 16);
 		return;
 	}
 	if (!vif1ch.chcr.STR) Console.WriteLn("Vif1 running when CHCR == %x", vif1ch.chcr._u32);
@@ -316,6 +324,11 @@ __fi void vif1Interrupt()
 
 		if ((vif1.inprogress & 0x1) == 0) vif1SetupTransfer();
 		if (vif1ch.chcr.DIR) vif1Regs.stat.FQC = min(vif1ch.qwc, (u16)16);
+		if(vif1.waitforvu == true)
+		{
+			//DevCon.Warning("Waiting on VU1");
+			return;
+		}
 	}
 	
 

pcsx2/Vif1_MFIFO.cpp

@@ -266,7 +266,7 @@ void vifMFIFOInterrupt()
 	if(vif1.waitforvu == true)
 	{
 	//	DevCon.Warning("Waiting on VU1 MFIFO");
-		CPU_INT(DMAC_MFIFO_VIF, 16);
+		//CPU_INT(DMAC_MFIFO_VIF, 16);
 		return;
 	}
 

pcsx2/Vif_Codes.cpp

@@ -81,7 +81,7 @@ static __fi void vuExecMicro(int idx, u32 addr) {
 
 
 	//DevCon.Warning("Ran VU%x, VU0 Cycles %x, VU1 Cycles %x, start %x cycle %x", idx, g_vu0Cycles, g_vu1Cycles, startcycles, VU1.cycle);
-	//GetVifX.vifstalled = true;
+	GetVifX.vifstalled = true;
 }
 
 void ExecuteVU(int idx)

pcsx2/x86/microVU_Macro.inl

@@ -317,6 +317,7 @@ static void recCTC2() {
 			}
 			else xXOR(ecx, ecx);
 			xCALL(vu1ExecMicro);
+			xCALL(vif1VUFinish);
 			break;
 		case REG_FBRST:
 			if (!_Rt_) {