mirror of https://github.com/PCSX2/pcsx2.git
SIGNAL! Area 51 WORKS! Soul Calibur 3 WORKS! probably broke loads! :P But thats the first time Area 51 has worked in years.
Only kidding, it should be awsome now, Also added a debug message incase some Paths are queued on a FINISH, any broken graphics when this shows up (or failure to load) should be reported asap! Thanks to jake for his hard work getting signal and my optimizations working :) git-svn-id: http://pcsx2.googlecode.com/svn/trunk@3400 96395faa-99c1-11dd-bbfe-3dabce05a288
This commit is contained in:
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968eed2822
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18
pcsx2/GS.cpp
18
pcsx2/GS.cpp
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@ -113,12 +113,22 @@ static __forceinline void gsCSRwrite( const tGS_CSR& csr )
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// SIGNAL : What's not known here is whether or not the SIGID register should be updated
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// SIGNAL : What's not known here is whether or not the SIGID register should be updated
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// here or when the IMR is cleared (below).
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// here or when the IMR is cleared (below).
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GIF_LOG("GS SIGNAL (pending) data=%x_%x IMR=%x CSRr=%x\n",SIGNAL_Data_Pending[0], SIGNAL_Data_Pending[1], GSIMR, GSCSRr);
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if(SIGNAL_IMR_Pending == true)
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GSSIGLBLID.SIGID = (GSSIGLBLID.SIGID&~SIGNAL_Data_Pending[1])|(SIGNAL_Data_Pending[0]&SIGNAL_Data_Pending[1]);
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{
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//DevCon.Warning("Firing pending signal");
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GIF_LOG("GS SIGNAL (pending) data=%x_%x IMR=%x CSRr=%x\n",SIGNAL_Data_Pending[0], SIGNAL_Data_Pending[1], GSIMR, GSCSRr);
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GSSIGLBLID.SIGID = (GSSIGLBLID.SIGID&~SIGNAL_Data_Pending[1])|(SIGNAL_Data_Pending[0]&SIGNAL_Data_Pending[1]);
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CSRreg.SIGNAL = false;
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if (!(GSIMR&0x100))
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gsIrq();
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CSRreg.SIGNAL = true; //Just to be sure :P
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}
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else CSRreg.SIGNAL = false;
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// [TODO] (SIGNAL) : Re-enable GIFpath DMAs here!
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SIGNAL_IMR_Pending = false;
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if(gifRegs->stat.P1Q && gifRegs->stat.APATH <= GIF_APATH1) gsPath1Interrupt();
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}
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}
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if(csr.FINISH) CSRreg.FINISH = false;
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if(csr.FINISH) CSRreg.FINISH = false;
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@ -89,10 +89,20 @@ void gsPath1Interrupt()
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}
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}
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}
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}
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extern bool SIGNAL_IMR_Pending;
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__forceinline void gsInterrupt()
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__forceinline void gsInterrupt()
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{
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{
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GIF_LOG("gsInterrupt: %8.8x", cpuRegs.cycle);
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GIF_LOG("gsInterrupt: %8.8x", cpuRegs.cycle);
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if(SIGNAL_IMR_Pending == true)
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{
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//DevCon.Warning("Path 3 Paused");
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CPU_INT(DMAC_GIF, 128);
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return;
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}
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if(GSTransferStatus.PTH3 >= PENDINGSTOP_MODE && gifRegs->stat.APATH == GIF_APATH3 )
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if(GSTransferStatus.PTH3 >= PENDINGSTOP_MODE && gifRegs->stat.APATH == GIF_APATH3 )
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{
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{
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gifRegs->stat.OPH = false;
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gifRegs->stat.OPH = false;
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@ -100,6 +110,7 @@ __forceinline void gsInterrupt()
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gifRegs->stat.APATH = GIF_APATH_IDLE;
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gifRegs->stat.APATH = GIF_APATH_IDLE;
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if(gifRegs->stat.P1Q) gsPath1Interrupt();
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if(gifRegs->stat.P1Q) gsPath1Interrupt();
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}
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}
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if (!(gif->chcr.STR))
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if (!(gif->chcr.STR))
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{
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{
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@ -255,6 +255,8 @@ __forceinline void vif1SetupTransfer()
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}
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}
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}
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}
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extern bool SIGNAL_IMR_Pending;
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bool CheckPath2GIF(int channel)
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bool CheckPath2GIF(int channel)
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{
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{
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if ((vif1Regs->stat.VGW))
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if ((vif1Regs->stat.VGW))
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@ -327,6 +329,12 @@ bool CheckPath2GIF(int channel)
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}
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}
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}
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}
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}
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}
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if(SIGNAL_IMR_Pending == true && (vif1.cmd & 0x7e) == 0x50)
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{
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//DevCon.Warning("Path 2 Paused");
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CPU_INT(channel, 128);
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return false;
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}
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return true;
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return true;
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}
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}
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__forceinline void vif1Interrupt()
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__forceinline void vif1Interrupt()
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@ -114,6 +114,8 @@ vifOp(vifCode_Base) {
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return 0;
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return 0;
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}
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}
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extern bool SIGNAL_IMR_Pending;
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template<int idx> _f int _vifCode_Direct(int pass, u8* data, bool isDirectHL) {
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template<int idx> _f int _vifCode_Direct(int pass, u8* data, bool isDirectHL) {
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pass1 {
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pass1 {
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vif1Only();
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vif1Only();
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@ -150,13 +152,21 @@ template<int idx> _f int _vifCode_Direct(int pass, u8* data, bool isDirectHL) {
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return 0;
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return 0;
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}
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}
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}
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}
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if(SIGNAL_IMR_Pending == true)
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{
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DevCon.Warning("Path 2 Paused (At start)");
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vif1.vifstalled = true;
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return 0;
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}
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if (gifRegs->stat.PSE) // temporarily stop
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if (gifRegs->stat.PSE) // temporarily stop
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{
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{
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Console.WriteLn("Gif dma temp paused? VIF DIRECT");
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Console.WriteLn("Gif dma temp paused? VIF DIRECT");
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vif1.GifWaitState = 3;
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vif1.GifWaitState = 3;
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vif1.vifstalled = true;
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vif1Regs->stat.VGW = true;
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vif1Regs->stat.VGW = true;
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return 0;
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return 0;
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}
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}
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gifRegs->stat.clear_flags(GIF_STAT_P2Q);
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gifRegs->stat.clear_flags(GIF_STAT_P2Q);
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@ -147,7 +147,7 @@ static void __fastcall RegHandlerSIGNAL(const u32* data)
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// Time to ignore all subsequent drawing operations. (which is not yet supported)
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// Time to ignore all subsequent drawing operations. (which is not yet supported)
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if (!SIGNAL_IMR_Pending)
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if (!SIGNAL_IMR_Pending)
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{
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{
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DevCon.WriteLn( Color_StrongOrange, "GS SIGNAL double throw encountered!" );
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//DevCon.WriteLn( Color_StrongOrange, "GS SIGNAL double throw encountered!" );
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SIGNAL_IMR_Pending = true;
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SIGNAL_IMR_Pending = true;
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SIGNAL_Data_Pending[0] = data[0];
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SIGNAL_Data_Pending[0] = data[0];
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SIGNAL_Data_Pending[1] = data[1];
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SIGNAL_Data_Pending[1] = data[1];
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@ -572,7 +572,7 @@ __forceinline int GIFPath::ParseTag(GIF_PATH pathidx, const u8* pMem, u32 size)
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gsHandler(pMem);
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gsHandler(pMem);
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}
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}
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incTag(16, 1);
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incTag(16, 1);
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} while(StepReg() && size > 0);
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} while(StepReg() && size > 0 && SIGNAL_IMR_Pending == false);
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}
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}
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else
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else
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{
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{
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@ -680,6 +680,7 @@ __forceinline int GIFPath::ParseTag(GIF_PATH pathidx, const u8* pMem, u32 size)
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// FINISH is *not* a per-path register, and it seems to pretty clearly indicate that all active
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// FINISH is *not* a per-path register, and it seems to pretty clearly indicate that all active
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// drawing *and* image transfer actions must be finished before the IRQ raises.
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// drawing *and* image transfer actions must be finished before the IRQ raises.
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if(gifRegs->stat.P1Q || gifRegs->stat.P2Q || gifRegs->stat.P3Q) DevCon.Warning("Early FINISH signal! P1 %x P2 %x P3 %x", gifRegs->stat.P1Q, gifRegs->stat.P2Q, gifRegs->stat.P3Q);
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if (!(GSIMR&0x200) && !s_gifPath.path[0].IsActive() && !s_gifPath.path[1].IsActive() && !s_gifPath.path[2].IsActive())
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if (!(GSIMR&0x200) && !s_gifPath.path[0].IsActive() && !s_gifPath.path[1].IsActive() && !s_gifPath.path[2].IsActive())
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{
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{
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gsIrq();
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gsIrq();
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@ -687,6 +688,11 @@ __forceinline int GIFPath::ParseTag(GIF_PATH pathidx, const u8* pMem, u32 size)
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}
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}
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break;
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break;
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}
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}
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if(SIGNAL_IMR_Pending == true)
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{
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//DevCon.Warning("Path %x", pathidx + 1);
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break;
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}
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}
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}
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size = (startSize - size);
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size = (startSize - size);
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@ -1101,7 +1101,10 @@ mVUop(mVU_XITOP) {
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//------------------------------------------------------------------
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//------------------------------------------------------------------
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// XGkick
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// XGkick
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//------------------------------------------------------------------
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//------------------------------------------------------------------
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extern void gsPath1Interrupt();
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extern void gsPath1Interrupt();
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extern bool SIGNAL_IMR_Pending;
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void __fastcall mVU_XGKICK_(u32 addr) {
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void __fastcall mVU_XGKICK_(u32 addr) {
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addr &= 0x3ff;
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addr &= 0x3ff;
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u8* data = microVU1.regs->Mem + (addr*16);
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u8* data = microVU1.regs->Mem + (addr*16);
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@ -1109,7 +1112,7 @@ void __fastcall mVU_XGKICK_(u32 addr) {
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u32 size;
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u32 size;
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u8* pDest;
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u8* pDest;
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if(gifRegs->stat.APATH <= GIF_APATH1 || (gifRegs->stat.APATH == GIF_APATH3 && gifRegs->stat.IP3 == true))
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if(gifRegs->stat.APATH <= GIF_APATH1 || (gifRegs->stat.APATH == GIF_APATH3 && gifRegs->stat.IP3 == true) && SIGNAL_IMR_Pending == false)
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{
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{
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if(Path1WritePos != 0)
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if(Path1WritePos != 0)
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@ -1970,6 +1970,8 @@ void recVUMI_XTOP( VURegs *VU, int info )
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//------------------------------------------------------------------
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//------------------------------------------------------------------
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// VU1XGKICK_MTGSTransfer() - Called by ivuZerorec.cpp
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// VU1XGKICK_MTGSTransfer() - Called by ivuZerorec.cpp
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//------------------------------------------------------------------
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//------------------------------------------------------------------
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extern bool SIGNAL_IMR_Pending;
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void __fastcall VU1XGKICK_MTGSTransfer(u32 *pMem, u32 addr)
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void __fastcall VU1XGKICK_MTGSTransfer(u32 *pMem, u32 addr)
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{
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{
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addr &= 0x3fff;
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addr &= 0x3fff;
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@ -1978,7 +1980,7 @@ void __fastcall VU1XGKICK_MTGSTransfer(u32 *pMem, u32 addr)
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u32 size;
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u32 size;
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u8* pDest;
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u8* pDest;
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if(gifRegs->stat.APATH <= GIF_APATH1 || (gifRegs->stat.APATH == GIF_APATH3 && gifRegs->stat.IP3 == true))
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if(gifRegs->stat.APATH <= GIF_APATH1 || (gifRegs->stat.APATH == GIF_APATH3 && gifRegs->stat.IP3 == true) && SIGNAL_IMR_Pending == false)
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{
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{
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if(Path1WritePos != 0)
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if(Path1WritePos != 0)
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