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x86/microVU: Flush register cache before T/D-bit 

Saves flushing in both execution paths.
This commit is contained in:
Stenzek 2022-12-25 22:14:25 +10:00 committed by refractionpcsx2
parent 4f65ef4d33
commit afd8ff1435
1 changed files with 12 additions and 1 deletions
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13
pcsx2/x86/microVU_Branch.inl
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@ -343,10 +343,12 @@ void normJumpCompile(mV, microFlagCycles& mFC, bool isEvilJump)
void normBranch(mV, microFlagCycles& mFC)
{
// E-bit or T-Bit or D-Bit Branch
if (mVUup.dBit && doDBitHandling)
{
// Flush register cache early to avoid double flush on both paths
mVU.regAlloc->flushAll(false);
u32 tempPC = iPC;
if (mVU.index && THREAD_VU1)
xTEST(ptr32[&vu1Thread.vuFBRST], (isVU1 ? 0x400 : 0x4));
@ -365,6 +367,9 @@ void normBranch(mV, microFlagCycles& mFC)
}
if (mVUup.tBit)
{
// Flush register cache early to avoid double flush on both paths
mVU.regAlloc->flushAll(false);
u32 tempPC = iPC;
if (mVU.index && THREAD_VU1)
xTEST(ptr32[&vu1Thread.vuFBRST], (isVU1 ? 0x800 : 0x8));
@ -584,6 +589,9 @@ void normJump(mV, microFlagCycles& mFC)
}
if (mVUup.dBit && doDBitHandling)
{
// Flush register cache early to avoid double flush on both paths
mVU.regAlloc->flushAll(false);
if (THREAD_VU1)
xTEST(ptr32[&vu1Thread.vuFBRST], (isVU1 ? 0x400 : 0x4));
else
@ -602,6 +610,9 @@ void normJump(mV, microFlagCycles& mFC)
}
if (mVUup.tBit)
{
// Flush register cache early to avoid double flush on both paths
mVU.regAlloc->flushAll(false);
if (mVU.index && THREAD_VU1)
xTEST(ptr32[&vu1Thread.vuFBRST], (isVU1 ? 0x800 : 0x8));
else