From afd8ff14350ebd2e62fa1a4ccfc09bdd7619a202 Mon Sep 17 00:00:00 2001 From: Stenzek Date: Sun, 25 Dec 2022 22:14:25 +1000 Subject: [PATCH] x86/microVU: Flush register cache before T/D-bit Saves flushing in both execution paths. --- pcsx2/x86/microVU_Branch.inl | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/pcsx2/x86/microVU_Branch.inl b/pcsx2/x86/microVU_Branch.inl index 106b8e07dd..bec40e3731 100644 --- a/pcsx2/x86/microVU_Branch.inl +++ b/pcsx2/x86/microVU_Branch.inl @@ -343,10 +343,12 @@ void normJumpCompile(mV, microFlagCycles& mFC, bool isEvilJump) void normBranch(mV, microFlagCycles& mFC) { - // E-bit or T-Bit or D-Bit Branch if (mVUup.dBit && doDBitHandling) { + // Flush register cache early to avoid double flush on both paths + mVU.regAlloc->flushAll(false); + u32 tempPC = iPC; if (mVU.index && THREAD_VU1) xTEST(ptr32[&vu1Thread.vuFBRST], (isVU1 ? 0x400 : 0x4)); @@ -365,6 +367,9 @@ void normBranch(mV, microFlagCycles& mFC) } if (mVUup.tBit) { + // Flush register cache early to avoid double flush on both paths + mVU.regAlloc->flushAll(false); + u32 tempPC = iPC; if (mVU.index && THREAD_VU1) xTEST(ptr32[&vu1Thread.vuFBRST], (isVU1 ? 0x800 : 0x8)); @@ -584,6 +589,9 @@ void normJump(mV, microFlagCycles& mFC) } if (mVUup.dBit && doDBitHandling) { + // Flush register cache early to avoid double flush on both paths + mVU.regAlloc->flushAll(false); + if (THREAD_VU1) xTEST(ptr32[&vu1Thread.vuFBRST], (isVU1 ? 0x400 : 0x4)); else @@ -602,6 +610,9 @@ void normJump(mV, microFlagCycles& mFC) } if (mVUup.tBit) { + // Flush register cache early to avoid double flush on both paths + mVU.regAlloc->flushAll(false); + if (mVU.index && THREAD_VU1) xTEST(ptr32[&vu1Thread.vuFBRST], (isVU1 ? 0x800 : 0x8)); else