mirror of https://github.com/PCSX2/pcsx2.git
Recompilers:
* Removed EBP push/pop stuff from the recExecute of the R5900 and R3000A both (not needed anymore since we disabled EBP in iCore). * Moved the legacy j8ptr and j32ptr buffers to iCore, since they'll go obsolete at the same time iCore does; and nothing outside PCSX2 references them. git-svn-id: http://pcsx2.googlecode.com/svn/trunk@2009 96395faa-99c1-11dd-bbfe-3dabce05a288
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@ -28,8 +28,6 @@ enum XMMSSEType
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};
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};
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extern __threadlocal u8 *x86Ptr;
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extern __threadlocal u8 *x86Ptr;
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extern __threadlocal u8 *j8Ptr[32]; // depreciated item. use local u8* vars instead.
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extern __threadlocal u32 *j32Ptr[32]; // depreciated item. use local u32* vars instead.
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extern __threadlocal XMMSSEType g_xmmtypes[iREGCNT_XMM];
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extern __threadlocal XMMSSEType g_xmmtypes[iREGCNT_XMM];
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@ -43,22 +43,27 @@ extern __aligned16 u64 g_globalXMMData[2*iREGCNT_XMM];
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// generally identical.
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// generally identical.
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//
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//
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// Performance Considerations:
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// Performance Considerations:
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// * GCC's implementation involves an extra dereference from normal storage.
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// * GCC's implementation involves an extra dereference from normal storage (possibly
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// applies to x86-32 only -- x86-64 is untested).
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//
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//
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// * MSVC's implementation involves *two* extra dereferences from normal storage because
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// * MSVC's implementation involves *two* extra dereferences from normal storage because
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// it has to look up the TLS heap pointer from the Windows Thread Storage Area. (in
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// it has to look up the TLS heap pointer from the Windows Thread Storage Area. (in
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// generated ASM code, this dereference is denoted by access to the fs:[2ch] address).
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// generated ASM code, this dereference is denoted by access to the fs:[2ch] address),
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//
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//
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// * However, in either case, the optimizer usually optimizes it to a register so the
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// * However, in either case, the optimizer usually optimizes it to a register so the
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// extra overhead is minimal over a series of instructions. (Note!! the Full Opt-
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// extra overhead is minimal over a series of instructions.
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// imization [/Ox] option effectively disables TLS optimizations in MSVC, causing
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//
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// generally significant code bloat).
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// MSVC Notes:
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// * Important!! the Full Optimization [/Ox] option effectively disables TLS optimizations
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// in MSVC 2008 and earlier, causing generally significant code bloat. Not tested in
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// VC2010 yet.
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//
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// * VC2010 generally does a superior job of optimizing TLS across inlined functions and
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// class methods, compared to predecessors.
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//
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//
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__threadlocal u8 *x86Ptr;
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__threadlocal u8 *x86Ptr;
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__threadlocal u8 *j8Ptr[32];
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__threadlocal u32 *j32Ptr[32];
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__threadlocal XMMSSEType g_xmmtypes[iREGCNT_XMM] = { XMMT_INT };
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__threadlocal XMMSSEType g_xmmtypes[iREGCNT_XMM] = { XMMT_INT };
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@ -22,6 +22,9 @@
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#include "VU.h"
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#include "VU.h"
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#include "R3000A.h"
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#include "R3000A.h"
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__threadlocal u8 *j8Ptr[32];
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__threadlocal u32 *j32Ptr[32];
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u16 g_x86AllocCounter = 0;
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u16 g_x86AllocCounter = 0;
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u16 g_xmmAllocCounter = 0;
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u16 g_xmmAllocCounter = 0;
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@ -303,6 +303,9 @@ extern u32 g_cpuRegHasSignExt, g_cpuPrevRegHasSignExt;
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extern _xmmregs xmmregs[iREGCNT_XMM], s_saveXMMregs[iREGCNT_XMM];
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extern _xmmregs xmmregs[iREGCNT_XMM], s_saveXMMregs[iREGCNT_XMM];
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extern __threadlocal u8 *j8Ptr[32]; // depreciated item. use local u8* vars instead.
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extern __threadlocal u32 *j32Ptr[32]; // depreciated item. use local u32* vars instead.
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extern u16 g_x86AllocCounter;
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extern u16 g_x86AllocCounter;
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extern u16 g_xmmAllocCounter;
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extern u16 g_xmmAllocCounter;
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@ -616,8 +616,6 @@ static void recShutdown()
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s_nInstCacheSize = 0;
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s_nInstCacheSize = 0;
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}
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}
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#pragma warning(disable:4731) // frame pointer register 'ebp' modified by inline assembly code
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u32 g_psxlastpc = 0;
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u32 g_psxlastpc = 0;
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static void iopClearRecLUT(BASEBLOCK* base, int count)
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static void iopClearRecLUT(BASEBLOCK* base, int count)
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@ -647,11 +645,9 @@ static __forceinline s32 recExecuteBlock( s32 eeCycles )
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push ebx
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push ebx
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push esi
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push esi
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push edi
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push edi
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push ebp
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call iopDispatcherReg
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call iopDispatcherReg
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pop ebp
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pop edi
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pop edi
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pop esi
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pop esi
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pop ebx
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pop ebx
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@ -661,20 +657,14 @@ static __forceinline s32 recExecuteBlock( s32 eeCycles )
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(
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(
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// We should be able to rely on GAS syntax (the register clobber list) as a
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// We should be able to rely on GAS syntax (the register clobber list) as a
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// replacement for manual push/pop of unpreserved registers.
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// replacement for manual push/pop of unpreserved registers.
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//
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// EBP note: As I feared, EBP is "required" for C++ exception handling in Linux, and trying
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// to issue a clobber specifier for it causes an error. We really need to find a way to
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// disable EBP regalloc in iCore. --air
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".intel_syntax noprefix\n"
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".intel_syntax noprefix\n"
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//"push ebx\n"
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//"push ebx\n"
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//"push esi\n"
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//"push esi\n"
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//"push edi\n"
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//"push edi\n"
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"push ebp\n"
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"call iopDispatcherReg\n"
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"call iopDispatcherReg\n"
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"pop ebp\n"
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//"pop edi\n"
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//"pop edi\n"
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//"pop esi\n"
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//"pop esi\n"
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//"pop ebx\n"
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//"pop ebx\n"
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@ -475,10 +475,6 @@ static void recShutdown( void )
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s_nInstCacheSize = 0;
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s_nInstCacheSize = 0;
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}
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}
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#ifdef _MSC_VER
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#pragma warning(disable:4731) // frame pointer register 'ebp' modified by inline assembly code
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#endif
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void recStep( void )
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void recStep( void )
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{
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{
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}
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}
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@ -509,7 +505,6 @@ void recEventTest()
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////////////////////////////////////////////////////
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////////////////////////////////////////////////////
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static u32 g_lastpc = 0;
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static u32 g_lastpc = 0;
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u32 g_EEDispatchTemp;
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#ifdef _MSC_VER
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#ifdef _MSC_VER
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@ -570,30 +565,28 @@ static void recExecute()
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// invoking DispatcherReg. These things are code bits which are called infrequently,
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// invoking DispatcherReg. These things are code bits which are called infrequently,
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// such as dyna_block_discard and dyna_page_reset.
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// such as dyna_block_discard and dyna_page_reset.
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// Optimization note:
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// Compared pushad against manually pushing the regs one-by-one.
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// Manually pushing is faster, especially on Core2's and such. :)
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g_EEFreezeRegs = true;
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try
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try
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{
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{
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while( true )
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while( true )
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{
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{
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// Note: make sure the FreezeRegs boolean is reset to true here, because
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// it might be set to false, depending on if the rec exits from the context of
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// an EventTest or not.
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g_EEFreezeRegs = true;
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try
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try
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{
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{
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#ifdef _MSC_VER
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#ifdef _MSC_VER
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__asm
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__asm
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{
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{
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push ebx
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push ebx
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push esi
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push esi
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push edi
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push edi
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push ebp
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call DispatcherReg
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call DispatcherReg
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pop ebp
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pop edi
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pop edi
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pop esi
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pop esi
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pop ebx
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pop ebx
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@ -800,12 +800,13 @@ void _saveEAX(VURegs *VU, int x86reg, uptr offset, int info)
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// (this is one of my test cases for the new emitter --air)
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// (this is one of my test cases for the new emitter --air)
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using namespace x86Emitter;
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using namespace x86Emitter;
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xAddressReg thisreg( x86reg );
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xAddressInfo indexer( offset );
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if( x86reg != -1 ) indexer.Add( xAddressReg( x86reg ) );
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if ( _X ) xMOV(ptr32[thisreg+offset], 0x00000000);
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if ( _X ) xMOV(ptr32[indexer], 0x00000000);
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if ( _Y ) xMOV(ptr32[thisreg+offset+4], 0x00000000);
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if ( _Y ) xMOV(ptr32[indexer+4], 0x00000000);
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if ( _Z ) xMOV(ptr32[thisreg+offset+8], 0x00000000);
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if ( _Z ) xMOV(ptr32[indexer+8], 0x00000000);
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if ( _W ) xMOV(ptr32[thisreg+offset+12], 0x3f800000);
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if ( _W ) xMOV(ptr32[indexer+12], 0x3f800000);
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}
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}
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return;
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return;
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}
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}
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