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pcsx2
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Code cleanup Revision: Implemented COP0 and COP1 (FPU) opcodes in the new opcode table system, rearranged namespaces to (hopefully!) make more sense, deleted a bunch of unused or duplicated prototypes in headers, and separated a few sections of general code into their own modules (such as XMMfreezeRegs/MMXfreezeRegs found in iCore and iR5900-32 modules, and some COP2-specific functions in VU0) 

git-svn-id: http://pcsx2-playground.googlecode.com/svn/trunk@566 a6443dda-0b58-4228-96e9-037be469359c
This commit is contained in:
Jake.Stine 2009-01-09 07:40:26 +00:00 committed by Gregory Hainaut
parent cfa967bdf7
commit adf070f8ea
117 changed files with 4137 additions and 5558 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

238
pcsx2/COP0.cpp
View File

@ -22,20 +22,10 @@
#include "R5900.h"
#include "InterTables.h"
void COP0_BC0() {
COP0_LOG("%s\n", disR5900Current.getString());
Int_COP0BC0PrintTable[(cpuRegs.code >> 16) & 0x03]();
}
void COP0_Func() {
COP0_LOG("%s\n", disR5900Current.getString());
Int_COP0C0PrintTable[_Funct_]();
}
void COP0_Unknown() {
CPU_LOG("COP0 Unknown opcode called\n");
}
namespace R5900
{
u32 s_iLastCOP0Cycle = 0;
u32 s_iLastPERFCycle[2] = { 0, 0 };
void UpdateCP0Status() {
u32 value = cpuRegs.CP0.n.Status.val;
@ -54,12 +44,118 @@ void WriteCP0Status(u32 value) {
UpdateCP0Status();
}
extern u32 s_iLastCOP0Cycle;
extern u32 s_iLastPERFCycle[2];
void MapTLB(int i)
{
u32 mask, addr;
u32 saddr, eaddr;
#ifndef PCSX2_VIRTUAL_MEM
DevCon::WriteLn("MAP TLB %d: %08x-> [%08x %08x] S=%d G=%d ASID=%d Mask= %03X", params
i,tlb[i].VPN2,tlb[i].PFN0,tlb[i].PFN1,tlb[i].S,tlb[i].G,tlb[i].ASID,tlb[i].Mask);
if (tlb[i].S)
{
SysPrintf("OMG SPRAM MAPPING %08X %08X\n",tlb[i].VPN2,tlb[i].Mask);
vtlb_VMapBuffer(tlb[i].VPN2,psS,0x4000);
}
#endif
if (tlb[i].VPN2 == 0x70000000) return; //uh uhh right ...
if (tlb[i].EntryLo0 & 0x2) {
mask = ((~tlb[i].Mask) << 1) & 0xfffff;
saddr = tlb[i].VPN2 >> 12;
eaddr = saddr + tlb[i].Mask + 1;
for (addr=saddr; addr<eaddr; addr++) {
if ((addr & mask) == ((tlb[i].VPN2 >> 12) & mask)) { //match
memSetPageAddr(addr << 12, tlb[i].PFN0 + ((addr - saddr) << 12));
Cpu->Clear(addr << 12, 1);
}
}
}
if (tlb[i].EntryLo1 & 0x2) {
mask = ((~tlb[i].Mask) << 1) & 0xfffff;
saddr = (tlb[i].VPN2 >> 12) + tlb[i].Mask + 1;
eaddr = saddr + tlb[i].Mask + 1;
for (addr=saddr; addr<eaddr; addr++) {
if ((addr & mask) == ((tlb[i].VPN2 >> 12) & mask)) { //match
memSetPageAddr(addr << 12, tlb[i].PFN1 + ((addr - saddr) << 12));
Cpu->Clear(addr << 12, 1);
}
}
}
}
void UnmapTLB(int i)
{
//SysPrintf("Clear TLB %d: %08x-> [%08x %08x] S=%d G=%d ASID=%d Mask= %03X\n",i,tlb[i].VPN2,tlb[i].PFN0,tlb[i].PFN1,tlb[i].S,tlb[i].G,tlb[i].ASID,tlb[i].Mask);
u32 mask, addr;
u32 saddr, eaddr;
#ifndef PCSX2_VIRTUAL_MEM
if (tlb[i].S)
{
vtlb_VMapUnmap(tlb[i].VPN2,0x4000);
return;
}
#endif
if (tlb[i].EntryLo0 & 0x2)
{
mask = ((~tlb[i].Mask) << 1) & 0xfffff;
saddr = tlb[i].VPN2 >> 12;
eaddr = saddr + tlb[i].Mask + 1;
// SysPrintf("Clear TLB: %08x ~ %08x\n",saddr,eaddr-1);
for (addr=saddr; addr<eaddr; addr++) {
if ((addr & mask) == ((tlb[i].VPN2 >> 12) & mask)) { //match
memClearPageAddr(addr << 12);
Cpu->Clear(addr << 12, 1);
}
}
}
if (tlb[i].EntryLo1 & 0x2) {
mask = ((~tlb[i].Mask) << 1) & 0xfffff;
saddr = (tlb[i].VPN2 >> 12) + tlb[i].Mask + 1;
eaddr = saddr + tlb[i].Mask + 1;
// SysPrintf("Clear TLB: %08x ~ %08x\n",saddr,eaddr-1);
for (addr=saddr; addr<eaddr; addr++) {
if ((addr & mask) == ((tlb[i].VPN2 >> 12) & mask)) { //match
memClearPageAddr(addr << 12);
Cpu->Clear(addr << 12, 1);
}
}
}
}
void WriteTLB(int i)
{
tlb[i].PageMask = cpuRegs.CP0.n.PageMask;
tlb[i].EntryHi = cpuRegs.CP0.n.EntryHi;
tlb[i].EntryLo0 = cpuRegs.CP0.n.EntryLo0;
tlb[i].EntryLo1 = cpuRegs.CP0.n.EntryLo1;
tlb[i].Mask = (cpuRegs.CP0.n.PageMask >> 13) & 0xfff;
tlb[i].nMask = (~tlb[i].Mask) & 0xfff;
tlb[i].VPN2 = ((cpuRegs.CP0.n.EntryHi >> 13) & (~tlb[i].Mask)) << 13;
tlb[i].ASID = cpuRegs.CP0.n.EntryHi & 0xfff;
tlb[i].G = cpuRegs.CP0.n.EntryLo0 & cpuRegs.CP0.n.EntryLo1 & 0x1;
tlb[i].PFN0 = (((cpuRegs.CP0.n.EntryLo0 >> 6) & 0xFFFFF) & (~tlb[i].Mask)) << 12;
tlb[i].PFN1 = (((cpuRegs.CP0.n.EntryLo1 >> 6) & 0xFFFFF) & (~tlb[i].Mask)) << 12;
#ifndef PCSX2_VIRTUAL_MEM
tlb[i].S = cpuRegs.CP0.n.EntryLo0&0x80000000;
#endif
MapTLB(i);
}
namespace Interpreter {
namespace OpcodeImpl
{
void MFC0() {
if (!_Rt_) return;
if (_Rd_ != 9) { COP0_LOG("%s\n", disR5900Current.getString()); }
if (_Rd_ != 9) { COP0_LOG("%s\n", disR5900Current.getCString() ); }
//if(bExecBIOS == FALSE && _Rd_ == 25) SysPrintf("MFC0 _Rd_ %x = %x\n", _Rd_, cpuRegs.CP0.r[_Rd_]);
switch (_Rd_) {
@ -99,7 +195,7 @@ void MFC0() {
}
void MTC0() {
COP0_LOG("%s\n", disR5900Current.getString());
COP0_LOG("%s\n", disR5900Current.getCString());
//if(bExecBIOS == FALSE && _Rd_ == 25) SysPrintf("MTC0 _Rd_ %x = %x\n", _Rd_, cpuRegs.CP0.r[_Rd_]);
switch (_Rd_) {
case 25:
@ -178,111 +274,6 @@ void TLBR() {
cpuRegs.CP0.n.EntryLo1 =(tlb[i].EntryLo1&~1)|((tlb[i].EntryHi>>12)&1);
}
void UnmapTLB(int i)
{
//SysPrintf("Clear TLB %d: %08x-> [%08x %08x] S=%d G=%d ASID=%d Mask= %03X\n",i,tlb[i].VPN2,tlb[i].PFN0,tlb[i].PFN1,tlb[i].S,tlb[i].G,tlb[i].ASID,tlb[i].Mask);
u32 mask, addr;
u32 saddr, eaddr;
#ifndef PCSX2_VIRTUAL_MEM
if (tlb[i].S)
{
vtlb_VMapUnmap(tlb[i].VPN2,0x4000);
return;
}
#endif
if (tlb[i].EntryLo0 & 0x2)
{
mask = ((~tlb[i].Mask) << 1) & 0xfffff;
saddr = tlb[i].VPN2 >> 12;
eaddr = saddr + tlb[i].Mask + 1;
// SysPrintf("Clear TLB: %08x ~ %08x\n",saddr,eaddr-1);
for (addr=saddr; addr<eaddr; addr++) {
if ((addr & mask) == ((tlb[i].VPN2 >> 12) & mask)) { //match
memClearPageAddr(addr << 12);
Cpu->Clear(addr << 12, 1);
}
}
}
if (tlb[i].EntryLo1 & 0x2) {
mask = ((~tlb[i].Mask) << 1) & 0xfffff;
saddr = (tlb[i].VPN2 >> 12) + tlb[i].Mask + 1;
eaddr = saddr + tlb[i].Mask + 1;
// SysPrintf("Clear TLB: %08x ~ %08x\n",saddr,eaddr-1);
for (addr=saddr; addr<eaddr; addr++) {
if ((addr & mask) == ((tlb[i].VPN2 >> 12) & mask)) { //match
memClearPageAddr(addr << 12);
Cpu->Clear(addr << 12, 1);
}
}
}
}
void MapTLB(int i)
{
u32 mask, addr;
u32 saddr, eaddr;
#ifndef PCSX2_VIRTUAL_MEM
DevCon::WriteLn("MAP TLB %d: %08x-> [%08x %08x] S=%d G=%d ASID=%d Mask= %03X", params
i,tlb[i].VPN2,tlb[i].PFN0,tlb[i].PFN1,tlb[i].S,tlb[i].G,tlb[i].ASID,tlb[i].Mask);
if (tlb[i].S)
{
SysPrintf("OMG SPRAM MAPPING %08X %08X\n",tlb[i].VPN2,tlb[i].Mask);
vtlb_VMapBuffer(tlb[i].VPN2,psS,0x4000);
}
#endif
if (tlb[i].VPN2 == 0x70000000) return; //uh uhh right ...
if (tlb[i].EntryLo0 & 0x2) {
mask = ((~tlb[i].Mask) << 1) & 0xfffff;
saddr = tlb[i].VPN2 >> 12;
eaddr = saddr + tlb[i].Mask + 1;
for (addr=saddr; addr<eaddr; addr++) {
if ((addr & mask) == ((tlb[i].VPN2 >> 12) & mask)) { //match
memSetPageAddr(addr << 12, tlb[i].PFN0 + ((addr - saddr) << 12));
Cpu->Clear(addr << 12, 1);
}
}
}
if (tlb[i].EntryLo1 & 0x2) {
mask = ((~tlb[i].Mask) << 1) & 0xfffff;
saddr = (tlb[i].VPN2 >> 12) + tlb[i].Mask + 1;
eaddr = saddr + tlb[i].Mask + 1;
for (addr=saddr; addr<eaddr; addr++) {
if ((addr & mask) == ((tlb[i].VPN2 >> 12) & mask)) { //match
memSetPageAddr(addr << 12, tlb[i].PFN1 + ((addr - saddr) << 12));
Cpu->Clear(addr << 12, 1);
}
}
}
}
void WriteTLB(int i)
{
tlb[i].PageMask = cpuRegs.CP0.n.PageMask;
tlb[i].EntryHi = cpuRegs.CP0.n.EntryHi;
tlb[i].EntryLo0 = cpuRegs.CP0.n.EntryLo0;
tlb[i].EntryLo1 = cpuRegs.CP0.n.EntryLo1;
tlb[i].Mask = (cpuRegs.CP0.n.PageMask >> 13) & 0xfff;
tlb[i].nMask = (~tlb[i].Mask) & 0xfff;
tlb[i].VPN2 = ((cpuRegs.CP0.n.EntryHi >> 13) & (~tlb[i].Mask)) << 13;
tlb[i].ASID = cpuRegs.CP0.n.EntryHi & 0xfff;
tlb[i].G = cpuRegs.CP0.n.EntryLo0 & cpuRegs.CP0.n.EntryLo1 & 0x1;
tlb[i].PFN0 = (((cpuRegs.CP0.n.EntryLo0 >> 6) & 0xFFFFF) & (~tlb[i].Mask)) << 12;
tlb[i].PFN1 = (((cpuRegs.CP0.n.EntryLo1 >> 6) & 0xFFFFF) & (~tlb[i].Mask)) << 12;
#ifndef PCSX2_VIRTUAL_MEM
tlb[i].S = cpuRegs.CP0.n.EntryLo0&0x80000000;
#endif
MapTLB(i);
}
void TLBWI() {
int j = cpuRegs.CP0.n.Index & 0x3f;
@ -367,3 +358,4 @@ void EI() {
}
}
} } } // end namespace R5900::Interpreter::OpcodeImpl

13
pcsx2/COP0.h
View File

@ -19,10 +19,13 @@
#ifndef __COP0_H__
#define __COP0_H__
void WriteCP0Status(u32 value);
void UpdateCP0Status();
void WriteTLB(int i);
void UnmapTLB(int i);
void MapTLB(int i);
namespace R5900
{
void WriteCP0Status(u32 value);
void UpdateCP0Status();
void WriteTLB(int i);
void UnmapTLB(int i);
void MapTLB(int i);
}
#endif /* __COP0_H__ */

89
pcsx2/COP2.cpp Normal file
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@ -0,0 +1,89 @@
/* Pcsx2 - Pc Ps2 Emulator
* Copyright (C) 2002-2008 Pcsx2 Team
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
*/
#include "PrecompiledHeader.h"
#include "Common.h"
#include "DebugTools/Debug.h"
#include "R5900.h"
#include "InterTables.h"
#include "VUops.h"
#include "VUmicro.h"
//namespace R5900 {
//namespace Interpreter {
//namespace OpcodeImpl{
using namespace R5900;
using namespace R5900::Interpreter;
#define CP2COND (((VU0.VI[REG_VPU_STAT].US[0] >> 8) & 1))
void VCALLMS() {
vu0Finish();
vu0ExecMicro(((cpuRegs.code >> 6) & 0x7FFF) * 8);
}
void VCALLMSR() {
vu0Finish();
vu0ExecMicro(VU0.VI[REG_CMSAR0].US[0] * 8);
}
void BC2F()
{
if (CP2COND == 0)
{
SysPrintf("VU0 Macro Branch \n");
intDoBranch(_BranchTarget_);
}
}
void BC2T()
{
if (CP2COND == 1)
{
SysPrintf("VU0 Macro Branch \n");
intDoBranch(_BranchTarget_);
}
}
void BC2FL()
{
if (CP2COND == 0)
{
SysPrintf("VU0 Macro Branch \n");
intDoBranch(_BranchTarget_);
}
else
{
cpuRegs.pc+= 4;
}
}
void BC2TL()
{
if (CP2COND == 1)
{
SysPrintf("VU0 Macro Branch \n");
intDoBranch(_BranchTarget_);
}
else
{
cpuRegs.pc+= 4;
}
}
//}}}

13
pcsx2/Cache.cpp
View File

@ -23,7 +23,8 @@
_cacheS pCache[64];
namespace EE { namespace Interpreter { namespace OpcodeImpl
namespace R5900{
namespace Interpreter
{
#ifdef PCSX2_CACHE_EMU_MEM
@ -147,6 +148,9 @@ u8 *readCache(u32 mem) {
return pCache[i].data[number][(mem>>4) & 0x3].b8._8;
}
namespace OpcodeImpl
{
extern int Dcache;
void CACHE() {
u32 addr;
@ -381,11 +385,16 @@ void CACHE() {
}
}
}
} // end namespace OpcodeImpl
#else
namespace OpcodeImpl
{
void CACHE() {
}
}
#endif
}}} // end namespace EE::Interpeter::OpcodeImpl
}}

2
pcsx2/Console.cpp
View File

@ -23,7 +23,7 @@
using namespace std;
VARG_PARAM va_arg_dummy;
const VARG_PARAM va_arg_dummy = { 0 };
// Methods of the Console namespace not defined here are to be found in the platform
// dependent implementations in WinConsole.cpp and LnxConsole.cpp.

26
pcsx2/Counters.cpp
View File

@ -27,11 +27,19 @@
using namespace Threading;
extern u8 psxhblankgate;
u32 g_vu1SkipCount; // number of frames to disable/skip VU1
static void (*s_prevExecuteVU1Block)() = NULL; // old VU1 block (either Int or Rec)
extern void DummyExecuteVU1Block(void);
namespace R5900
{
u64 profile_starttick = 0;
u64 profile_totalticks = 0;
int gates = 0;
extern u8 psxhblankgate;
// Counter 4 takes care of scanlines - hSync/hBlanks
// Counter 5 takes care of vSync/vBlanks
@ -42,11 +50,6 @@ s32 nextCounter; // delta from nextsCounter, in cycles, until the next rcntUpdat
// VUSkip Locals and Globals
u32 g_vu1SkipCount; // number of frames to disable/skip VU1
static void (*s_prevExecuteVU1Block)() = NULL; // old VU1 block (either Int or Rec)
extern void DummyExecuteVU1Block(void);
void rcntReset(int index) {
counters[index].count = 0;
counters[index].sCycleT = cpuRegs.cycle;
@ -259,12 +262,6 @@ extern u32 vu0time;
void vSyncDebugStuff() {
#ifdef EE_PROFILING
if( (iFrame%20) == 0 ) {
SysPrintf("Profiled Cycles at %d frames %d\n", iFrame, profile_totalticks);
CLEAR_EE_PROFILE();
}
#endif
#ifdef PCSX2_DEVBUILD
if( g_TestRun.enabled && g_TestRun.frame > 0 ) {
@ -832,6 +829,10 @@ u32 rcntCycle(int index)
return counters[index].count;
}
} // End namespace R5900!
using namespace R5900;
void SaveState::rcntFreeze()
{
Freeze(counters);
@ -865,4 +866,3 @@ void SaveState::rcntFreeze()
iopBranchAction = 1; // probably not needed but won't hurt anything either.
}
}

7
pcsx2/Counters.h
View File

@ -19,6 +19,8 @@
#ifndef __COUNTERS_H__
#define __COUNTERS_H__
namespace R5900
{
struct EECNT_MODE
{
// 0 - BUSCLK
@ -127,8 +129,6 @@ struct Counter {
extern Counter counters[6];
extern s32 nextCounter; // delta until the next counter event (must be signed)
extern u32 nextsCounter;
extern u32 g_lastVSyncCycle;
extern u32 g_deltaVSyncCycle;
extern void rcntUpdate_hScanline();
extern void rcntUpdate_vSync();
@ -145,5 +145,8 @@ u32 rcntRcount(int index);
u32 rcntCycle(int index);
u32 UpdateVSyncRate();
void frameLimitReset();
} // End namespace R5900!
#endif /* __COUNTERS_H__ */

69
pcsx2/DebugTools/Debug.h
View File

@ -24,43 +24,52 @@
extern FILE *emuLog;
void disR5900F( std::string& output, u32 code, u32 pc);
void disR5900Fasm( std::string& output, u32 code, u32 pc);
char* disR3000Fasm(u32 code, u32 pc);
extern char* disR3000Fasm(u32 code, u32 pc);
extern char* disR3000AF(u32 code, u32 pc);
void disR5900AddSym(u32 addr, const char *name);
const char* disR5900GetSym(u32 addr);
const char* disR5900GetUpperSym(u32 addr);
void disR5900FreeSyms();
void dFindSym( std::string& output, u32 addr );
extern char* disVU0MicroUF(u32 code, u32 pc);
extern char* disVU0MicroLF(u32 code, u32 pc);
extern char* disVU1MicroUF(u32 code, u32 pc);
extern char* disVU1MicroLF(u32 code, u32 pc);
void strAppend( std::string& output, const char *fmt, ... );
extern const char * const CP2VFnames[];
extern const char * const disRNameCP2f[];
extern const char * const disRNameCP2i[];
char* disVU0MicroUF(u32 code, u32 pc);
char* disVU0MicroLF(u32 code, u32 pc);
char* disVU1MicroUF(u32 code, u32 pc);
char* disVU1MicroLF(u32 code, u32 pc);
char* disR3000AF(u32 code, u32 pc);
extern const char *CP2VFnames[];
extern const char *disRNameCP2f[];
extern const char *disRNameCP2i[];
// A helper class for getting a quick and efficient string representation of the
// R5900's current instruction. This class is *not* thread safe!
class DisR5900CurrentState
namespace R5900
{
protected:
std::string result;
// [TODO] : These function names can be de-obfuscated with the help of a little namespace love.
public:
const char* getString();
};
void disR5900F( std::string& output, u32 code, u32 pc);
void disR5900Fasm( std::string& output, u32 code, u32 pc);
void disR5900AddSym(u32 addr, const char *name);
const char* disR5900GetSym(u32 addr);
const char* disR5900GetUpperSym(u32 addr);
void disR5900FreeSyms();
void dFindSym( std::string& output, u32 addr );
extern DisR5900CurrentState disR5900Current;
extern const char * const disRNameGPR[];
// A helper class for getting a quick and efficient string representation of the
// R5900's current instruction. This class is *not* thread safe!
class DisR5900CurrentState
{
protected:
std::string result;
public:
const std::string& getString();
const char* getCString();
};
extern DisR5900CurrentState disR5900Current;
}
namespace R3000a
{
extern const char * const disRNameGPR[];
}
//that way is slower but you now not need to compile every time ;P
#ifdef PCSX2_DEVBUILD
extern u32 varLog;

24
pcsx2/DebugTools/DisR3000A.cpp
View File

@ -23,18 +23,22 @@
static char ostr[1024];
// Names of registers
static const char *disRNameGPR[] = {
"r0", "at", "v0", "v1", "a0", "a1","a2", "a3",
"t0", "t1", "t2", "t3", "t4", "t5","t6", "t7",
"s0", "s1", "s2", "s3", "s4", "s5","s6", "s7",
"t8", "t9", "k0", "k1", "gp", "sp","fp", "ra"};
namespace IOP
{
const char * const disRNameGPR[] = {
"r0", "at", "v0", "v1", "a0", "a1","a2", "a3",
"t0", "t1", "t2", "t3", "t4", "t5","t6", "t7",
"s0", "s1", "s2", "s3", "s4", "s5","s6", "s7",
"t8", "t9", "k0", "k1", "gp", "sp","fp", "ra"};
static const char *disRNameCP0[] = {
"Index" , "Random" , "EntryLo0", "EntryLo1", "Context" , "PageMask" , "Wired" , "*Check me*",
"BadVAddr" , "Count" , "EntryHi" , "Compare" , "Status" , "Cause" , "ExceptPC" , "PRevID" ,
"Config" , "LLAddr" , "WatchLo" , "WatchHi" , "XContext", "*RES*" , "*RES*" , "*RES*" ,
"*RES*" , "*RES* " , "PErr" , "CacheErr", "TagLo" , "TagHi" , "ErrorEPC" , "*RES*" };
const char * const disRNameCP0[] = {
"Index" , "Random" , "EntryLo0", "EntryLo1", "Context" , "PageMask" , "Wired" , "*Check me*",
"BadVAddr" , "Count" , "EntryHi" , "Compare" , "Status" , "Cause" , "ExceptPC" , "PRevID" ,
"Config" , "LLAddr" , "WatchLo" , "WatchHi" , "XContext", "*RES*" , "*RES*" , "*RES*" ,
"*RES*" , "*RES* " , "PErr" , "CacheErr", "TagLo" , "TagHi" , "ErrorEPC" , "*RES*" };
}
using namespace IOP;
// Type definition of our functions

135
pcsx2/DebugTools/DisR5900.cpp
View File

@ -24,46 +24,47 @@ using namespace std;
#include "R5900.h"
#include "VU.h"
//static char ostr[1024];
// Names of registers
const char *disRNameGPR[] = {
"r0", "at", "v0", "v1", "a0", "a1","a2", "a3",
"t0", "t1", "t2", "t3", "t4", "t5","t6", "t7",
"s0", "s1", "s2", "s3", "s4", "s5","s6", "s7",
"t8", "t9", "k0", "k1", "gp", "sp","fp", "ra", "hi", "lo"}; // lo,hi used in rec
const char *disRNameCP0[] = {
"Index" , "Random" , "EntryLo0" , "EntryLo1", "Context" , "PageMask" , "Wired" , "*RES*",
"BadVAddr" , "Count" , "EntryHi" , "Compare" , "Status" , "Cause" , "ExceptPC" , "PRevID",
"Config" , "LLAddr" , "WatchLo" , "WatchHi" , "*RES*" , "*RES*" , "*RES*" , "Debug",
"DEPC" , "PerfCnt" , "ErrCtl" , "CacheErr", "TagLo" , "TagHi" , "ErrorEPC" , "DESAVE"};
const char *disRNameCP1[] = {
"FPR0" , "FPR1" , "FPR2" , "FPR3" , "FPR4" , "FPR5" , "FPR6" , "FPR7",
"FPR8" , "FPR9" , "FPR10", "FPR11", "FPR12", "FPR13", "FPR14", "FPR15",
"FPR16", "FPR17", "FPR18", "FPR19", "FPR20", "FPR21", "FPR22", "FPR23",
"FPR24", "FPR25", "FPR26", "FPR27", "FPR28", "FPR29", "FPR30", "FPR31"};
const char *disRNameCP1c[] = {
"FRevID", "*RES*", "*RES*", "*RES*", "*RES*", "*RES*", "*RES*", "*RES*",
"*RES*", "*RES*", "*RES*", "*RES*", "*RES*", "*RES*", "*RES*", "*RES*",
"*RES*", "*RES*", "*RES*", "*RES*", "*RES*", "*RES*", "*RES*", "*RES*",
"*RES*", "*RES*", "*RES*", "*RES*", "*RES*", "*RES*", "*RES*", "FStatus"};
const char *disRNameCP2f[] = {
static const char * const disRNameCP2f[] = {
"VF00", "VF01", "VF02", "VF03", "VF04", "VF05", "VF06", "VF07",
"VF08", "VF09", "VF10", "VF11", "VF12", "VF13", "VF14", "VF15",
"VF16", "VF17", "VF18", "VF19", "VF20", "VF21", "VF22", "VF23",
"VF24", "VF25", "VF26", "VF27", "VF28", "VF29", "VF30", "VF31"};
const char *disRNameCP2i[] = {
static const char * const disRNameCP2i[] = {
"VI00", "VI01", "VI02", "VI03", "VI04", "VI05", "VI06", "VI07",
"VI08", "VI09", "VI10", "VI11", "VI12", "VI13", "VI14", "VI15",
"Status", "MAC", "Clip", "*RES*", "R", "I", "Q", "*RES*",
"*RES*", "*RES*", "TPC", "CMSAR0", "FBRST", "VPU-STAT", "*RES*", "CMSAR1"};
const char *CP2VFnames[] = { "x", "y", "z", "w" };
static const char * const CP2VFnames[] = { "x", "y", "z", "w" };
namespace R5900
{
// Names of registers
const char * const disRNameGPR[] = {
"r0", "at", "v0", "v1", "a0", "a1","a2", "a3",
"t0", "t1", "t2", "t3", "t4", "t5","t6", "t7",
"s0", "s1", "s2", "s3", "s4", "s5","s6", "s7",
"t8", "t9", "k0", "k1", "gp", "sp","fp", "ra", "hi", "lo"}; // lo,hi used in rec
const char * const disRNameCP0[] = {
"Index" , "Random" , "EntryLo0" , "EntryLo1", "Context" , "PageMask" , "Wired" , "*RES*",
"BadVAddr" , "Count" , "EntryHi" , "Compare" , "Status" , "Cause" , "ExceptPC" , "PRevID",
"Config" , "LLAddr" , "WatchLo" , "WatchHi" , "*RES*" , "*RES*" , "*RES*" , "Debug",
"DEPC" , "PerfCnt" , "ErrCtl" , "CacheErr", "TagLo" , "TagHi" , "ErrorEPC" , "DESAVE"};
static const char * const disRNameCP1[] = {
"FPR0" , "FPR1" , "FPR2" , "FPR3" , "FPR4" , "FPR5" , "FPR6" , "FPR7",
"FPR8" , "FPR9" , "FPR10", "FPR11", "FPR12", "FPR13", "FPR14", "FPR15",
"FPR16", "FPR17", "FPR18", "FPR19", "FPR20", "FPR21", "FPR22", "FPR23",
"FPR24", "FPR25", "FPR26", "FPR27", "FPR28", "FPR29", "FPR30", "FPR31"};
static const char * const disRNameCP1c[] = {
"FRevID", "*RES*", "*RES*", "*RES*", "*RES*", "*RES*", "*RES*", "*RES*",
"*RES*", "*RES*", "*RES*", "*RES*", "*RES*", "*RES*", "*RES*", "*RES*",
"*RES*", "*RES*", "*RES*", "*RES*", "*RES*", "*RES*", "*RES*", "*RES*",
"*RES*", "*RES*", "*RES*", "*RES*", "*RES*", "*RES*", "*RES*", "FStatus"};
// Type definition of our functions
#define DisFInterface (string& output, u32 code, u32 pc)
@ -130,38 +131,42 @@ typedef void (*TdisR5900F)DisFInterface;
#define _Fsf_ ((code >> 21) & 0x03)
#define _Ftf_ ((code >> 23) & 0x03)
#define dName(i) strAppend(output, "%-7s,", i);
#define dGPR128(i) strAppend(output, "%8.8x_%8.8x_%8.8x_%8.8x (%s),", cpuRegs.GPR.r[i].UL[3], cpuRegs.GPR.r[i].UL[2], cpuRegs.GPR.r[i].UL[1], cpuRegs.GPR.r[i].UL[0], disRNameGPR[i])
#define dGPR64(i) strAppend(output, "%8.8x_%8.8x (%s),", cpuRegs.GPR.r[i].UL[1], cpuRegs.GPR.r[i].UL[0], disRNameGPR[i])
#define dGPR64U(i) strAppend(output, "%8.8x_%8.8x (%s),", cpuRegs.GPR.r[i].UL[3], cpuRegs.GPR.r[i].UL[2], disRNameGPR[i])
#define dGPR32(i) strAppend(output, "%8.8x (%s),", cpuRegs.GPR.r[i].UL[0], disRNameGPR[i])
// sap! it stands for string append. It's not a friendly name but for now it makes
// the copy-paste marathon of code below more readable!
#define _sap( str ) ssappendf( output, str, params
#define dCP032(i) strAppend(output, "%8.8x (%s),", cpuRegs.CP0.r[i], disRNameCP0[i])
#define dName(i) _sap("%-7s,") i);
#define dGPR128(i) _sap("%8.8x_%8.8x_%8.8x_%8.8x (%s),") cpuRegs.GPR.r[i].UL[3], cpuRegs.GPR.r[i].UL[2], cpuRegs.GPR.r[i].UL[1], cpuRegs.GPR.r[i].UL[0], disRNameGPR[i])
#define dGPR64(i) _sap("%8.8x_%8.8x (%s),") cpuRegs.GPR.r[i].UL[1], cpuRegs.GPR.r[i].UL[0], disRNameGPR[i])
#define dGPR64U(i) _sap("%8.8x_%8.8x (%s),") cpuRegs.GPR.r[i].UL[3], cpuRegs.GPR.r[i].UL[2], disRNameGPR[i])
#define dGPR32(i) _sap("%8.8x (%s),") cpuRegs.GPR.r[i].UL[0], disRNameGPR[i])
#define dCP132(i) strAppend(output, "%f (%s),", fpuRegs.fpr[i].f, disRNameCP1[i])
#define dCP1c32(i) strAppend(output, "%8.8x (%s),", fpuRegs.fprc[i], disRNameCP1c[i])
#define dCP1acc() strAppend(output, "%f (ACC),", fpuRegs.ACC.f)
#define dCP032(i) _sap("%8.8x (%s),") cpuRegs.CP0.r[i], disRNameCP0[i])
#define dCP2128f(i) strAppend(output, "w=%f z=%f y=%f x=%f (%s),", VU0.VF[i].f.w, VU0.VF[i].f.z, VU0.VF[i].f.y, VU0.VF[i].f.x, disRNameCP2f[i])
#define dCP232x(i) strAppend(output, "x=%f (%s),", VU0.VF[i].f.x, disRNameCP2f[i])
#define dCP232y(i) strAppend(output, "y=%f (%s),", VU0.VF[i].f.y, disRNameCP2f[i])
#define dCP232z(i) strAppend(output, "z=%f (%s),", VU0.VF[i].f.z, disRNameCP2f[i])
#define dCP232w(i) strAppend(output, "w=%f (%s),", VU0.VF[i].f.w, disRNameCP2f[i])
#define dCP2ACCf() strAppend(output, "w=%f z=%f y=%f x=%f (ACC),", VU0.ACC.f.w, VU0.ACC.f.z, VU0.ACC.f.y, VU0.ACC.f.x)
#define dCP232i(i) strAppend(output, "%8.8x (%s),", VU0.VI[i].UL, disRNameCP2i[i])
#define dCP232iF(i) strAppend(output, "%f (%s),", VU0.VI[i].F, disRNameCP2i[i])
#define dCP232f(i, j) strAppend(output, "Q %s=%f (%s),", CP2VFnames[j], VU0.VF[i].F[j], disRNameCP2f[i])
#define dCP132(i) _sap("%f (%s),") fpuRegs.fpr[i].f, disRNameCP1[i])
#define dCP1c32(i) _sap("%8.8x (%s),") fpuRegs.fprc[i], disRNameCP1c[i])
#define dCP1acc() _sap("%f (ACC),") fpuRegs.ACC.f)
#define dHI64() strAppend(output, "%8.8x_%8.8x (%s),", cpuRegs.HI.UL[1], cpuRegs.HI.UL[0], "hi")
#define dLO64() strAppend(output, "%8.8x_%8.8x (%s),", cpuRegs.LO.UL[1], cpuRegs.LO.UL[0], "lo")
#define dImm() strAppend(output, "%4.4x (%d),", _Im_, _Im_)
#define dTarget() strAppend(output, "%8.8x,", _Target_)
#define dSa() strAppend(output, "%2.2x (%d),", _Sa_, _Sa_)
#define dSa32() strAppend(output, "%2.2x (%d),", _Sa_+32, _Sa_+32)
#define dOfB() strAppend(output, "%4.4x (%8.8x (%s)),", _Im_, cpuRegs.GPR.r[_Rs_].UL[0], disRNameGPR[_Rs_])
#define dOffset() strAppend(output, "%8.8x,", _Branch_)
#define dCode() strAppend(output, "%8.8x,", (code >> 6) & 0xffffff)
#define dSaR() strAppend(output, "%8.8x,", cpuRegs.sa)
#define dCP2128f(i) _sap("w=%f z=%f y=%f x=%f (%s),") VU0.VF[i].f.w, VU0.VF[i].f.z, VU0.VF[i].f.y, VU0.VF[i].f.x, disRNameCP2f[i])
#define dCP232x(i) _sap("x=%f (%s),") VU0.VF[i].f.x, disRNameCP2f[i])
#define dCP232y(i) _sap("y=%f (%s),") VU0.VF[i].f.y, disRNameCP2f[i])
#define dCP232z(i) _sap("z=%f (%s),") VU0.VF[i].f.z, disRNameCP2f[i])
#define dCP232w(i) _sap("w=%f (%s),") VU0.VF[i].f.w, disRNameCP2f[i])
#define dCP2ACCf() _sap("w=%f z=%f y=%f x=%f (ACC),") VU0.ACC.f.w, VU0.ACC.f.z, VU0.ACC.f.y, VU0.ACC.f.x)
#define dCP232i(i) _sap("%8.8x (%s),") VU0.VI[i].UL, disRNameCP2i[i])
#define dCP232iF(i) _sap("%f (%s),") VU0.VI[i].F, disRNameCP2i[i])
#define dCP232f(i, j) _sap("Q %s=%f (%s),") CP2VFnames[j], VU0.VF[i].F[j], disRNameCP2f[i])
#define dHI64() _sap("%8.8x_%8.8x (%s),") cpuRegs.HI.UL[1], cpuRegs.HI.UL[0], "hi")
#define dLO64() _sap("%8.8x_%8.8x (%s),") cpuRegs.LO.UL[1], cpuRegs.LO.UL[0], "lo")
#define dImm() _sap("%4.4x (%d),") _Im_, _Im_)
#define dTarget() _sap("%8.8x,") _Target_)
#define dSa() _sap("%2.2x (%d),") _Sa_, _Sa_)
#define dSa32() _sap("%2.2x (%d),") _Sa_+32, _Sa_+32)
#define dOfB() _sap("%4.4x (%8.8x (%s)),") _Im_, cpuRegs.GPR.r[_Rs_].UL[0], disRNameGPR[_Rs_])
#define dOffset() _sap("%8.8x,") _Branch_)
#define dCode() _sap("%8.8x,") (code >> 6) & 0xffffff)
#define dSaR() _sap("%8.8x,") cpuRegs.sa)
struct sSymbol {
u32 addr;
@ -1010,10 +1015,20 @@ MakeDisF(disR5900F, disR5900[code >> 26] DisFInterfaceN)
// returns a string representation of the cpuRegs current instruction.
// The return value of this method is *not* thread safe!
const char* DisR5900CurrentState::getString()
const string& DisR5900CurrentState::getString()
{
result.clear();
disR5900F( result, cpuRegs.code, cpuRegs.pc );
return result;
}
const char* DisR5900CurrentState::getCString()
{
result.clear();
disR5900F( result, cpuRegs.code, cpuRegs.pc );
return result.c_str();
}
DisR5900CurrentState disR5900Current;
DisR5900CurrentState disR5900Current;
}

1035
pcsx2/DebugTools/DisR5900asm.cpp
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1064
pcsx2/DebugTools/cpuopsDebug.cpp
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456
pcsx2/DebugTools/cpuopsDebug.h
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@ -1,456 +0,0 @@
/* Pcsx2 - Pc Ps2 Emulator
* Copyright (C) 2002-2008 Pcsx2 Team
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
*/
void UpdateR5900op();
extern void (*LT_OpcodePrintTable[64])();
extern void (*LT_SpecialPrintTable[64])();
extern void (*LT_REGIMMPrintTable[32])();
extern void (*LT_MMIPrintTable[64])();
extern void (*LT_MMI0PrintTable[32])();
extern void (*LT_MMI1PrintTable[32])();
extern void (*LT_MMI2PrintTable[32])();
extern void (*LT_MMI3PrintTable[32])();
extern void (*LT_COP0PrintTable[32])();
extern void (*LT_COP0BC0PrintTable[32])();
extern void (*LT_COP0C0PrintTable[64])();
extern void (*LT_COP1PrintTable[32])();
extern void (*LT_COP1BC1PrintTable[32])();
extern void (*LT_COP1SPrintTable[64])();
extern void (*LT_COP1WPrintTable[64])();
extern void (*LT_COP2PrintTable[32])();
extern void (*LT_COP2BC2PrintTable[32])();
extern void (*LT_COP2SPECIAL1PrintTable[64])();
extern void (*LT_COP2SPECIAL2PrintTable[128])();
// **********************Standard Opcodes**************************
int L_ADD=0;
int L_ADDI=0;
int L_ADDIU=0;
int L_ADDU=0;
int L_AND=0;
int L_ANDI=0;
int L_BEQ=0;
int L_BEQL=0;
int L_BGEZ=0;
int L_BGEZAL=0;
int L_BGEZALL=0;
int L_BGEZL=0;
int L_BGTZ=0;
int L_BGTZL=0;
int L_BLEZ=0;
int L_BLEZL=0;
int L_BLTZ=0;
int L_BLTZAL=0;
int L_BLTZALL=0;
int L_BLTZL=0;
int L_BNE=0;
int L_BNEL=0;
int L_BREAK=0;
int L_CACHE=0;
int L_DADD=0;
int L_DADDI=0;
int L_DADDIU=0;
int L_DADDU=0;
int L_DIV=0;
int L_DIVU=0;
int L_DSLL=0;
int L_DSLL32=0;
int L_DSLLV=0;
int L_DSRA=0;
int L_DSRA32=0;
int L_DSRAV=0;
int L_DSRL=0;
int L_DSRL32=0;
int L_DSRLV=0;
int L_DSUB=0;
int L_DSUBU=0;
int L_J=0;
int L_JAL=0;
int L_JALR=0;
int L_JR=0;
int L_LB=0;
int L_LBU=0;
int L_LD=0;
int L_LDL=0;
int L_LDR=0;
int L_LH=0;
int L_LHU=0;
int L_LQ=0;
int L_LQC2=0;
int L_LUI=0;
int L_LW=0;
int L_LWC1=0;
int L_LWL=0;
int L_LWR=0;
int L_LWU=0;
int L_MFHI=0;
int L_MFLO=0;
int L_MFSA=0;
int L_MOVN=0;
int L_MOVZ=0;
int L_MTHI=0;
int L_MTLO=0;
int L_MTSA=0;
int L_MTSAB=0;
int L_MTSAH=0;
int L_MULT=0;
int L_MULTU=0;
int L_NOR=0;
int L_OR=0;
int L_ORI=0;
int L_PREF=0;
int L_SB=0;
int L_SD=0;
int L_SDL=0;
int L_SDR=0;
int L_SH=0;
int L_SLL=0;
int L_SLLV=0;
int L_SLT=0;
int L_SLTI=0;
int L_SLTIU=0;
int L_SLTU=0;
int L_SQ=0;
int L_SQC2=0;
int L_SRA=0;
int L_SRAV=0;
int L_SRL=0;
int L_SRLV=0;
int L_SUB=0;
int L_SUBU=0;
int L_SW=0;
int L_SWC1=0;
int L_SWL=0;
int L_SWR=0;
int L_SYNC=0;
int L_SYSCALL=0;
int L_TEQ=0;
int L_TEQI=0;
int L_TGE=0;
int L_TGEI=0;
int L_TGEIU=0;
int L_TGEU=0;
int L_TLT=0;
int L_TLTI=0;
int L_TLTIU=0;
int L_TLTU=0;
int L_TNE=0;
int L_TNEI=0;
int L_XOR=0;
int L_XORI=0;
//*****************MMI OPCODES*********************************
int L_MADD=0;
int L_MADDU=0;
int L_PLZCW=0;
int L_MADD1=0;
int L_MADDU1=0;
int L_MFHI1=0;
int L_MTHI1=0;
int L_MFLO1=0;
int L_MTLO1=0;
int L_MULT1=0;
int L_MULTU1=0;
int L_DIV1=0;
int L_DIVU1=0;
int L_PMFHL=0;
int L_PMTHL=0;
int L_PSLLH=0;
int L_PSRLH=0;
int L_PSRAH=0;
int L_PSLLW=0;
int L_PSRLW=0;
int L_PSRAW=0;
//*****************END OF MMI OPCODES**************************
//*************************MMI0 OPCODES************************
int L_PADDW=0;
int L_PSUBW=0;
int L_PCGTW=0;
int L_PMAXW=0;
int L_PADDH=0;
int L_PSUBH=0;
int L_PCGTH=0;
int L_PMAXH=0;
int L_PADDB=0;
int L_PSUBB=0;
int L_PCGTB=0;
int L_PADDSW=0;
int L_PSUBSW=0;
int L_PEXTLW=0;
int L_PPACW=0;
int L_PADDSH=0;
int L_PSUBSH=0;
int L_PEXTLH=0;
int L_PPACH=0;
int L_PADDSB=0;
int L_PSUBSB=0;
int L_PEXTLB=0;
int L_PPACB=0;
int L_PEXT5=0;
int L_PPAC5=0;
//***END OF MMI0 OPCODES******************************************
//**********MMI1 OPCODES**************************************
int L_PABSW=0;
int L_PCEQW=0;
int L_PMINW=0;
int L_PADSBH=0;
int L_PABSH=0;
int L_PCEQH=0;
int L_PMINH=0;
int L_PCEQB=0;
int L_PADDUW=0;
int L_PSUBUW=0;
int L_PEXTUW=0;
int L_PADDUH=0;
int L_PSUBUH=0;
int L_PEXTUH=0;
int L_PADDUB=0;
int L_PSUBUB=0;
int L_PEXTUB=0;
int L_QFSRV=0;
//********END OF MMI1 OPCODES***********************************
//*********MMI2 OPCODES***************************************
int L_PMADDW=0;
int L_PSLLVW=0;
int L_PSRLVW=0;
int L_PMSUBW=0;
int L_PMFHI=0;
int L_PMFLO=0;
int L_PINTH=0;
int L_PMULTW=0;
int L_PDIVW=0;
int L_PCPYLD=0;
int L_PMADDH=0;
int L_PHMADH=0;
int L_PAND=0;
int L_PXOR=0;
int L_PMSUBH=0;
int L_PHMSBH=0;
int L_PEXEH=0;
int L_PREVH=0;
int L_PMULTH=0;
int L_PDIVBW=0;
int L_PEXEW=0;
int L_PROT3W=0;
//*****END OF MMI2 OPCODES***********************************
//*************************MMI3 OPCODES************************
int L_PMADDUW=0;
int L_PSRAVW=0;
int L_PMTHI=0;
int L_PMTLO=0;
int L_PINTEH=0;
int L_PMULTUW=0;
int L_PDIVUW=0;
int L_PCPYUD=0;
int L_POR=0;
int L_PNOR=0;
int L_PEXCH=0;
int L_PCPYH=0;
int L_PEXCW=0;
//**********************END OF MMI3 OPCODES********************
//****************************************************************************
//** COP0 **
//****************************************************************************
int L_MFC0=0;
int L_MTC0=0;
int L_BC0F=0;
int L_BC0T=0;
int L_BC0FL=0;
int L_BC0TL=0;
int L_TLBR=0;
int L_TLBWI=0;
int L_TLBWR=0;
int L_TLBP=0;
int L_ERET=0;
int L_DI=0;
int L_EI=0;
//****************************************************************************
//** END OF COP0 **
//****************************************************************************
//****************************************************************************
//** COP1 - Floating Point Unit (FPU) **
//****************************************************************************
int L_MFC1=0;
int L_CFC1=0;
int L_MTC1=0;
int L_CTC1=0;
int L_BC1F=0;
int L_BC1T=0;
int L_BC1FL=0;
int L_BC1TL=0;
int L_ADD_S=0;
int L_SUB_S=0;
int L_MUL_S=0;
int L_DIV_S=0;
int L_SQRT_S=0;
int L_ABS_S=0;
int L_MOV_S=0;
int L_NEG_S=0;
int L_RSQRT_S=0;
int L_ADDA_S=0;
int L_SUBA_S=0;
int L_MULA_S=0;
int L_MADD_S=0;
int L_MSUB_S=0;
int L_MADDA_S=0;
int L_MSUBA_S=0;
int L_CVT_W=0;
int L_MAX_S=0;
int L_MIN_S=0;
int L_C_F=0;
int L_C_EQ=0;
int L_C_LT=0;
int L_C_LE=0;
int L_CVT_S=0;
//****************************************************************************
//** END OF COP1 **
//****************************************************************************
//****************************************************************************
//** COP2 - (VU0) **
//****************************************************************************
int L_QMFC2=0;
int L_CFC2=0;
int L_QMTC2=0;
int L_CTC2=0;
int L_BC2F=0;
int L_BC2T=0;
int L_BC2FL=0;
int L_BC2TL=0;
int L_VADDx=0;
int L_VADDy=0;
int L_VADDz=0;
int L_VADDw=0;
int L_VSUBx=0;
int L_VSUBy=0;
int L_VSUBz=0;
int L_VSUBw=0;
int L_VMADDx=0;
int L_VMADDy=0;
int L_VMADDz=0;
int L_VMADDw=0;
int L_VMSUBx=0;
int L_VMSUBy=0;
int L_VMSUBz=0;
int L_VMSUBw=0;
int L_VMAXx=0;
int L_VMAXy=0;
int L_VMAXz=0;
int L_VMAXw=0;
int L_VMINIx=0;
int L_VMINIy=0;
int L_VMINIz=0;
int L_VMINIw=0;
int L_VMULx=0;
int L_VMULy=0;
int L_VMULz=0;
int L_VMULw=0;
int L_VMULq=0;
int L_VMAXi=0;
int L_VMULi=0;
int L_VMINIi=0;
int L_VADDq=0;
int L_VMADDq=0;
int L_VADDi=0;
int L_VMADDi=0;
int L_VSUBq=0;
int L_VMSUBq=0;
int L_VSUBi=0;
int L_VMSUBi=0;
int L_VADD=0;
int L_VMADD=0;
int L_VMUL=0;
int L_VMAX=0;
int L_VSUB=0;
int L_VMSUB=0;
int L_VOPMSUB=0;
int L_VMINI=0;
int L_VIADD=0;
int L_VISUB=0;
int L_VIADDI=0;
int L_VIAND=0;
int L_VIOR=0;
int L_VCALLMS=0;
int L_VCALLMSR=0;
int L_VADDAx=0;
int L_VADDAy=0;
int L_VADDAz=0;
int L_VADDAw=0;
int L_VSUBAx=0;
int L_VSUBAy=0;
int L_VSUBAz=0;
int L_VSUBAw=0;
int L_VMADDAx=0;
int L_VMADDAy=0;
int L_VMADDAz=0;
int L_VMADDAw=0;
int L_VMSUBAx=0;
int L_VMSUBAy=0;
int L_VMSUBAz=0;
int L_VMSUBAw=0;
int L_VITOF0=0;
int L_VITOF4=0;
int L_VITOF12=0;
int L_VITOF15=0;
int L_VFTOI0=0;
int L_VFTOI4=0;
int L_VFTOI12=0;
int L_VFTOI15=0;
int L_VMULAx=0;
int L_VMULAy=0;
int L_VMULAz=0;
int L_VMULAw=0;
int L_VMULAq=0;
int L_VABS=0;
int L_VMULAi=0;
int L_VCLIPw=0;
int L_VADDAq=0;
int L_VMADDAq=0;
int L_VADDAi=0;
int L_VMADDAi=0;
int L_VSUBAq=0;
int L_VMSUBAq=0;
int L_VSUBAi=0;
int L_VMSUBAi=0;
int L_VADDA=0;
int L_VMADDA=0;
int L_VMULA=0;
int L_VSUBA=0;
int L_VMSUBA=0;
int L_VOPMULA=0;
int L_VNOP=0;
int L_VMOVE=0;
int L_VMR32=0;
int L_VLQI=0;
int L_VSQI=0;
int L_VLQD=0;
int L_VSQD=0;
int L_VDIV=0;
int L_VSQRT=0;
int L_VRSQRT=0;
int L_VWAITQ=0;
int L_VMTIR=0;
int L_VMFIR=0;
int L_VILWR=0;
int L_VISWR=0;
int L_VRNEXT=0;
int L_VRGET=0;
int L_VRINIT=0;
int L_VRXOR=0;

3
pcsx2/Elfheader.cpp
View File

@ -22,6 +22,7 @@
#include "CDVDisodrv.h"
using namespace std;
using namespace R5900;
#ifdef _MSC_VER
#pragma warning(disable:4996) //ignore the stricmp deprecated warning
@ -506,7 +507,7 @@ void ElfApplyPatches()
ssprintf( filename, "%8.8x", params ElfCRC );
// if patches found the following status msg will be overwritten
Console::SetTitle( fmt_string( "Game running without patches. [CRC=%S]", params &filename ) );
Console::SetTitle( fmt_string( "Game running without patches. [CRC=%hs]", params &filename ) );
if(LoadPatch( filename ) != 0)
{

37
pcsx2/FPU.cpp
View File

@ -148,6 +148,10 @@ using namespace std; // for min / max
intDoBranch( _BranchTarget_ ); \
} else cpuRegs.pc += 4;
namespace R5900 {
namespace Interpreter {
namespace OpcodeImpl
{
//****************************************************************
// FPU Opcodes
@ -359,19 +363,24 @@ void SUBA_S() {
checkUnderflow( _FAValUl_, FPUflagU | FPUflagSU, 1 );
}
namespace EE { namespace Interpreter{ namespace OpcodeImpl
{
void LWC1() {
u32 addr;
addr = cpuRegs.GPR.r[_Rs_].UL[0] + (s32)(s16)(cpuRegs.code & 0xffff);
if (addr & 0x00000003) { SysPrintf( "FPU (LWC1 Opcode): Invalid Memory Address\n" ); return; } // Should signal an exception?
memRead32(addr, &fpuRegs.fpr[_Rt_].UL);
}
/////////////////////////////////////////////////////////////////////
// COP1 (FPU) Load/Store Instructions
// These are actually EE opcodes but since they're related to FPU registers and such they
// seem more appropriately located here.
void LWC1() {
u32 addr;
addr = cpuRegs.GPR.r[_Rs_].UL[0] + (s32)(s16)(cpuRegs.code & 0xffff);
if (addr & 0x00000003) { Console::Error( "FPU (LWC1 Opcode): Invalid Memory Address" ); return; } // Should signal an exception?
memRead32(addr, &fpuRegs.fpr[_Rt_].UL);
}
void SWC1() {
u32 addr;
addr = cpuRegs.GPR.r[_Rs_].UL[0] + (s32)(s16)(cpuRegs.code & 0xffff);
if (addr & 0x00000003) { Console::Error( "FPU (SWC1 Opcode): Invalid Memory Address" ); return; } // Should signal an exception?
memWrite32(addr, fpuRegs.fpr[_Rt_].UL);
}
void SWC1() {
u32 addr;
addr = cpuRegs.GPR.r[_Rs_].UL[0] + (s32)(s16)(cpuRegs.code & 0xffff);
if (addr & 0x00000003) { SysPrintf( "FPU (SWC1 Opcode): Invalid Memory Address\n" ); return; } // Should signal an exception?
memWrite32(addr, fpuRegs.fpr[_Rt_].UL);
}
}}}

3
pcsx2/GS.cpp
View File

@ -28,6 +28,8 @@
using namespace Threading;
using namespace std;
using namespace R5900;
#ifdef DEBUG
#define MTGS_LOG SysPrintf
#else
@ -1228,7 +1230,6 @@ void gsResetFrameSkip()
_gs_ResetFrameskip();
}
void frameLimitReset(); // defined in Counters.c
void gsDynamicSkipEnable()
{
if( !m_StrictSkipping ) return;

25
pcsx2/GS.h
View File

@ -265,22 +265,25 @@ void gsWrite16(u32 mem, u16 value);
void gsWrite32(u32 mem, u32 value);
void gsWrite64(u32 mem, u64 value);
void gsConstWrite8(u32 mem, int mmreg);
void gsConstWrite16(u32 mem, int mmreg);
void gsConstWrite32(u32 mem, int mmreg);
void gsConstWrite64(u32 mem, int mmreg);
void gsConstWrite128(u32 mem, int mmreg);
u8 gsRead8(u32 mem);
u16 gsRead16(u32 mem);
u32 gsRead32(u32 mem);
u64 gsRead64(u32 mem);
int gsConstRead8(u32 x86reg, u32 mem, u32 sign);
int gsConstRead16(u32 x86reg, u32 mem, u32 sign);
int gsConstRead32(u32 x86reg, u32 mem);
void gsConstRead64(u32 mem, int mmreg);
void gsConstRead128(u32 mem, int xmmreg);
namespace Dynarec
{
void gsConstWrite8(u32 mem, int mmreg);
void gsConstWrite16(u32 mem, int mmreg);
void gsConstWrite32(u32 mem, int mmreg);
void gsConstWrite64(u32 mem, int mmreg);
void gsConstWrite128(u32 mem, int mmreg);
int gsConstRead8(u32 x86reg, u32 mem, u32 sign);
int gsConstRead16(u32 x86reg, u32 mem, u32 sign);
int gsConstRead32(u32 x86reg, u32 mem);
void gsConstRead64(u32 mem, int mmreg);
void gsConstRead128(u32 mem, int xmmreg);
}
void gsIrq();
extern void gsInterrupt();

3
pcsx2/Hw.cpp
View File

@ -28,6 +28,9 @@
#include <assert.h>
using namespace Dynarec;
using namespace Dynarec::R5900;
#ifndef PCSX2_VIRTUAL_MEM
u8 *psH; // hw mem
u16 *psHW;

10
pcsx2/Hw.h
View File

@ -38,13 +38,11 @@ extern u64 *psHD;
#define psHu32(mem) (*(u32*)&PS2MEM_HW[(mem) & 0xffff])
#define psHu64(mem) (*(u64*)&PS2MEM_HW[(mem) & 0xffff])
extern u32 g_nextBranchCycle;
extern int cpuSetNextBranch( u32 startCycle, s32 delta );
extern int cpuSetNextBranchDelta( s32 delta );
extern int cpuTestCycle( u32 startCycle, s32 delta );
extern void cpuSetBranch();
namespace R5900{
extern void CPU_INT( u32 n, s32 ecycle );
}
using R5900::CPU_INT;
// VIF0 -- 0x10004000 -- psH[0x4000]
// VIF1 -- 0x10005000 -- psH[0x5000]

3
pcsx2/IPU/IPU.cpp
View File

@ -30,6 +30,9 @@
using namespace std; // for min / max
using namespace Dynarec;
using namespace Dynarec::R5900;
// Zero cycle IRQ schedules aren't really good, but the IPU uses them.
// Better to throw the IRQ inline:

313
pcsx2/InterTables.cpp
View File

@ -19,39 +19,79 @@
//all tables for R5900 are define here..
#include "InterTables.h"
#include "R5900.h"
namespace EE
#include "x86/iR5900AritImm.h"
#include "x86/iR5900Arit.h"
#include "x86/iR5900MultDiv.h"
#include "x86/iR5900Shift.h"
#include "x86/iR5900Branch.h"
#include "x86/iR5900Jump.h"
#include "x86/iR5900LoadStore.h"
#include "x86/iR5900Move.h"
#include "x86/iMMI.h"
#include "x86/iCP0.h"
#include "x86/iFPU.h"
namespace R5900
{
namespace Opcodes
{
// Generates an entry for the given opcode name.
// Assumes the default function naming schemes for interpreter and recompiler functions.
# define MakeOpcode( name, cycles ) \
static const OPCODE name = { \
#name, \
cycles, \
NULL, \
R5900::Interpreter::OpcodeImpl::name, \
Dynarec::R5900::OpcodeImpl::rec##name, \
R5900::OpcodeDisasm::name \
}
# define MakeOpcodeClass( name ) \
static const OPCODE name = { \
#name, \
0, \
R5900::Opcodes::Class_##name, \
NULL, \
NULL, \
NULL \
}
// We're working on new hopefully better cycle ratios, but they're still a WIP.
// And yes this whole thing is an ugly hack. I'll clean it up once we have
// a better idea how exactly the cycle ratios will work best.
static const int Cycles_Default = 9;
static const int Cycles_Branch = 12;
namespace Cycles
{
static const int Default = 9;
static const int Branch = 11;
static const int CopDefault = 7;
static const int Cycles_Mult = 2*8;
static const int Cycles_Div = 13*8;
static const int Cycles_FPU_Sqrt = 4*8;
static const int Cycles_MMI_Mult = 3*8;
static const int Cycles_MMI_Div = 22*8;
static const int Mult = 2*8;
static const int Div = 14*8;
static const int MMI_Mult = 3*8;
static const int MMI_Div = 22*8;
static const int Cycles_Store = 20; // 21 for snes emu
static const int Cycles_Load = 11; // 13 for snes emu
static const int FPU_Mult = 12;
static const int Cycles_Misc = 7;
static const int Store = 21;
static const int Load = 11;
}
using namespace Cycles;
MakeOpcode( Unknown, Default );
MakeOpcode( MMI_Unknown, Default );
MakeOpcode( COP0_Unknown, Default );
MakeOpcode( COP1_Unknown, Default );
// Class Subset Opcodes
// (not really opcodes, but rather entire subsets of other opcode classes)
MakeOpcodeClass( SPECIAL );
MakeOpcodeClass( REGIMM );
//MakeOpcodeClass( COP0 );
//MakeOpcodeClass( COP1 );
//MakeOpcodeClass( COP2 );
MakeOpcodeClass( MMI );
MakeOpcodeClass( MMI0 );
@ -59,11 +99,12 @@ namespace EE
MakeOpcodeClass( MMI1 );
MakeOpcodeClass( MMI3 );
MakeOpcodeClass( COP0 );
MakeOpcodeClass( COP1 );
// Misc Junk
MakeOpcode( COP0, Misc );
MakeOpcode( COP1, Misc );
MakeOpcode( COP2, Misc );
MakeOpcode( COP2, Default );
MakeOpcode( CACHE, Default );
MakeOpcode( PREF, Default );
@ -308,25 +349,92 @@ namespace EE
MakeOpcode( PCPYH, Default );
MakeOpcode( PEXCW, Default );
//////////////////////////////////////////////////////////
// COP0 Instructions
MakeOpcodeClass( COP0_C0 );
MakeOpcodeClass( COP0_BC0 );
MakeOpcode( MFC0, CopDefault );
MakeOpcode( MTC0, CopDefault );
MakeOpcode( BC0F, Branch );
MakeOpcode( BC0T, Branch );
MakeOpcode( BC0FL, Branch );
MakeOpcode( BC0TL, Branch );
MakeOpcode( TLBR, CopDefault );
MakeOpcode( TLBWI, CopDefault );
MakeOpcode( TLBWR, CopDefault );
MakeOpcode( TLBP, CopDefault );
MakeOpcode( ERET, CopDefault );
MakeOpcode( EI, CopDefault );
MakeOpcode( DI, CopDefault );
//////////////////////////////////////////////////////////
// COP1 Instructions!
MakeOpcodeClass( COP1_BC1 );
MakeOpcodeClass( COP1_S );
MakeOpcodeClass( COP1_W ); // contains CVT_S instruction *only*
MakeOpcode( MFC1, CopDefault );
MakeOpcode( CFC1, CopDefault );
MakeOpcode( MTC1, CopDefault );
MakeOpcode( CTC1, CopDefault );
MakeOpcode( BC1F, Branch );
MakeOpcode( BC1T, Branch );
MakeOpcode( BC1FL, Branch );
MakeOpcode( BC1TL, Branch );
MakeOpcode( ADD_S, CopDefault );
MakeOpcode( ADDA_S, CopDefault );
MakeOpcode( SUB_S, CopDefault );
MakeOpcode( SUBA_S, CopDefault );
MakeOpcode( ABS_S, CopDefault );
MakeOpcode( MOV_S, CopDefault );
MakeOpcode( NEG_S, CopDefault );
MakeOpcode( MAX_S, CopDefault );
MakeOpcode( MIN_S, CopDefault );
MakeOpcode( MUL_S, FPU_Mult );
MakeOpcode( DIV_S, 3*8 );
MakeOpcode( SQRT_S, 3*8 );
MakeOpcode( RSQRT_S, 4*8 );
MakeOpcode( MULA_S, FPU_Mult );
MakeOpcode( MADD_S, FPU_Mult );
MakeOpcode( MSUB_S, FPU_Mult );
MakeOpcode( MADDA_S, FPU_Mult );
MakeOpcode( MSUBA_S, FPU_Mult );
MakeOpcode( C_F, CopDefault );
MakeOpcode( C_EQ, CopDefault );
MakeOpcode( C_LT, CopDefault );
MakeOpcode( C_LE, CopDefault );
MakeOpcode( CVT_S, CopDefault );
MakeOpcode( CVT_W, CopDefault );
}
namespace OpcodeTables
{
using namespace Opcodes;
const OPCODE Standard[64] =
const OPCODE tbl_Standard[64] =
{
SPECIAL, REGIMM, J, JAL, BEQ, BNE, BLEZ, BGTZ,
ADDI, ADDIU, SLTI, SLTIU, ANDI, ORI, XORI, LUI,
COP0, COP1, COP2, Unknown, BEQL, BNEL, BLEZL, BGTZL,
DADDI, DADDIU, LDL, LDR, Opcodes::MMI, Unknown, LQ, SQ,
DADDI, DADDIU, LDL, LDR, MMI, Unknown, LQ, SQ,
LB, LH, LWL, LW, LBU, LHU, LWR, LWU,
SB, SH, SWL, SW, SDL, SDR, SWR, CACHE,
Unknown, LWC1, Unknown, PREF, Unknown, Unknown, LQC2, LD,
Unknown, SWC1, Unknown, Unknown, Unknown, Unknown, SQC2, SD
};
const OPCODE Special[64] =
static const OPCODE tbl_Special[64] =
{
SLL, Unknown, SRL, SRA, SLLV, Unknown, SRLV, SRAV,
JR, JALR, MOVZ, MOVN, SYSCALL, BREAK, Unknown, SYNC,
@ -338,26 +446,26 @@ namespace EE
DSLL, Unknown, DSRL, DSRA, DSLL32, Unknown, DSRL32, DSRA32
};
const OPCODE RegImm[32] = {
static const OPCODE tbl_RegImm[32] = {
BLTZ, BGEZ, BLTZL, BGEZL, Unknown, Unknown, Unknown, Unknown,
TGEI, TGEIU, TLTI, TLTIU, TEQI, Unknown, TNEI, Unknown,
BLTZAL, BGEZAL, BLTZALL, BGEZALL, Unknown, Unknown, Unknown, Unknown,
MTSAB, MTSAH , Unknown, Unknown, Unknown, Unknown, Unknown, Unknown,
};
const OPCODE MMI[64] =
static const OPCODE tbl_MMI[64] =
{
MADD, MADDU, MMI_Unknown, MMI_Unknown, PLZCW, MMI_Unknown, MMI_Unknown, MMI_Unknown,
Opcodes::MMI0, Opcodes::MMI2, MMI_Unknown, MMI_Unknown, MMI_Unknown, MMI_Unknown, MMI_Unknown, MMI_Unknown,
MMI0, MMI2, MMI_Unknown, MMI_Unknown, MMI_Unknown, MMI_Unknown, MMI_Unknown, MMI_Unknown,
MFHI1, MTHI1, MFLO1, MTLO1, MMI_Unknown, MMI_Unknown, MMI_Unknown, MMI_Unknown,
MULT1, MULTU1, DIV1, DIVU1, MMI_Unknown, MMI_Unknown, MMI_Unknown, MMI_Unknown,
MADD1, MADDU1, MMI_Unknown, MMI_Unknown, MMI_Unknown, MMI_Unknown, MMI_Unknown, MMI_Unknown,
Opcodes::MMI1, Opcodes::MMI3, MMI_Unknown, MMI_Unknown, MMI_Unknown, MMI_Unknown, MMI_Unknown, MMI_Unknown,
MMI1, MMI3, MMI_Unknown, MMI_Unknown, MMI_Unknown, MMI_Unknown, MMI_Unknown, MMI_Unknown,
PMFHL, PMTHL, MMI_Unknown, MMI_Unknown, PSLLH, MMI_Unknown, PSRLH, PSRAH,
MMI_Unknown, MMI_Unknown, MMI_Unknown, MMI_Unknown, PSLLW, MMI_Unknown, PSRLW, PSRAW,
};
const OPCODE MMI0[32] =
static const OPCODE tbl_MMI0[32] =
{
PADDW, PSUBW, PCGTW, PMAXW,
PADDH, PSUBH, PCGTH, PMAXH,
@ -369,7 +477,7 @@ namespace EE
MMI_Unknown, MMI_Unknown, PEXT5, PPAC5,
};
const OPCODE MMI1[32] =
static const OPCODE tbl_MMI1[32] =
{
MMI_Unknown, PABSW, PCEQW, PMINW,
PADSBH, PABSH, PCEQH, PMINH,
@ -382,7 +490,7 @@ namespace EE
};
const OPCODE MMI2[32] =
static const OPCODE tbl_MMI2[32] =
{
PMADDW, MMI_Unknown, PSLLVW, PSRLVW,
PMSUBW, MMI_Unknown, MMI_Unknown, MMI_Unknown,
@ -394,7 +502,7 @@ namespace EE
PMULTH, PDIVBW, PEXEW, PROT3W,
};
const OPCODE MMI3[32] =
static const OPCODE tbl_MMI3[32] =
{
PMADDUW, MMI_Unknown, MMI_Unknown, PSRAVW,
MMI_Unknown, MMI_Unknown, MMI_Unknown, MMI_Unknown,
@ -406,72 +514,105 @@ namespace EE
MMI_Unknown, MMI_Unknown, PEXCW, MMI_Unknown,
};
} // end namespace EE::OpcodeTables
} // end namespace EE
static const OPCODE tbl_COP0[32] =
{
MFC0, COP0_Unknown, COP0_Unknown, COP0_Unknown, MTC0, COP0_Unknown, COP0_Unknown, COP0_Unknown,
COP0_BC0, COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown,
COP0_C0, COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown,
COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown,
};
void (*Int_COP0PrintTable[32])() =
{
MFC0, COP0_Unknown, COP0_Unknown, COP0_Unknown, MTC0, COP0_Unknown, COP0_Unknown, COP0_Unknown,
COP0_BC0, COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown,
COP0_Func, COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown,
COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown,
};
static const OPCODE tbl_COP0_BC0[32] =
{
BC0F, BC0T, BC0FL, BC0TL, COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown,
COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown,
COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown,
COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown,
};
void (*Int_COP0BC0PrintTable[32])() =
{
BC0F, BC0T, BC0FL, BC0TL, COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown,
COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown,
COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown,
COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown,
};
static const OPCODE tbl_COP0_C0[64] =
{
COP0_Unknown, TLBR, TLBWI, COP0_Unknown, COP0_Unknown, COP0_Unknown, TLBWR, COP0_Unknown,
TLBP, COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown,
COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown,
ERET, COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown,
COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown,
COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown,
COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown,
EI, DI, COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown
};
void (*Int_COP0C0PrintTable[64])() = {
COP0_Unknown, TLBR, TLBWI, COP0_Unknown, COP0_Unknown, COP0_Unknown, TLBWR, COP0_Unknown,
TLBP, COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown,
COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown,
ERET, COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown,
COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown,
COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown,
COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown,
EI, DI, COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown
};
static const OPCODE tbl_COP1[32] =
{
MFC1, COP1_Unknown, CFC1, COP1_Unknown, MTC1, COP1_Unknown, CTC1, COP1_Unknown,
COP1_BC1, COP1_Unknown, COP1_Unknown, COP1_Unknown, COP1_Unknown, COP1_Unknown, COP1_Unknown, COP1_Unknown,
COP1_S, COP1_Unknown, COP1_Unknown, COP1_Unknown, COP1_W, COP1_Unknown, COP1_Unknown, COP1_Unknown,
COP1_Unknown, COP1_Unknown, COP1_Unknown, COP1_Unknown, COP1_Unknown, COP1_Unknown, COP1_Unknown, COP1_Unknown,
};
void (*Int_COP1PrintTable[32])() = {
MFC1, COP1_Unknown, CFC1, COP1_Unknown, MTC1, COP1_Unknown, CTC1, COP1_Unknown,
COP1_BC1, COP1_Unknown, COP1_Unknown, COP1_Unknown, COP1_Unknown, COP1_Unknown, COP1_Unknown, COP1_Unknown,
COP1_S, COP1_Unknown, COP1_Unknown, COP1_Unknown, COP1_W, COP1_Unknown, COP1_Unknown, COP1_Unknown,
COP1_Unknown, COP1_Unknown, COP1_Unknown, COP1_Unknown, COP1_Unknown, COP1_Unknown, COP1_Unknown, COP1_Unknown,
};
static const OPCODE tbl_COP1_BC1[32] =
{
BC1F, BC1T, BC1FL, BC1TL, COP1_Unknown, COP1_Unknown, COP1_Unknown, COP1_Unknown,
COP1_Unknown, COP1_Unknown, COP1_Unknown, COP1_Unknown, COP1_Unknown, COP1_Unknown, COP1_Unknown, COP1_Unknown,
COP1_Unknown, COP1_Unknown, COP1_Unknown, COP1_Unknown, COP1_Unknown, COP1_Unknown, COP1_Unknown, COP1_Unknown,
COP1_Unknown, COP1_Unknown, COP1_Unknown, COP1_Unknown, COP1_Unknown, COP1_Unknown, COP1_Unknown, COP1_Unknown,
};
void (*Int_COP1BC1PrintTable[32])() = {
BC1F, BC1T, BC1FL, BC1TL, COP1_Unknown, COP1_Unknown, COP1_Unknown, COP1_Unknown,
COP1_Unknown, COP1_Unknown, COP1_Unknown, COP1_Unknown, COP1_Unknown, COP1_Unknown, COP1_Unknown, COP1_Unknown,
COP1_Unknown, COP1_Unknown, COP1_Unknown, COP1_Unknown, COP1_Unknown, COP1_Unknown, COP1_Unknown, COP1_Unknown,
COP1_Unknown, COP1_Unknown, COP1_Unknown, COP1_Unknown, COP1_Unknown, COP1_Unknown, COP1_Unknown, COP1_Unknown,
};
static const OPCODE tbl_COP1_S[64] =
{
ADD_S, SUB_S, MUL_S, DIV_S, SQRT_S, ABS_S, MOV_S, NEG_S,
COP1_Unknown,COP1_Unknown,COP1_Unknown,COP1_Unknown,COP1_Unknown,COP1_Unknown,COP1_Unknown,COP1_Unknown,
COP1_Unknown,COP1_Unknown,COP1_Unknown,COP1_Unknown,COP1_Unknown,COP1_Unknown,RSQRT_S, COP1_Unknown,
ADDA_S, SUBA_S, MULA_S, COP1_Unknown,MADD_S, MSUB_S, MADDA_S, MSUBA_S,
COP1_Unknown,COP1_Unknown,COP1_Unknown,COP1_Unknown,CVT_W, COP1_Unknown,COP1_Unknown,COP1_Unknown,
MAX_S, MIN_S, COP1_Unknown,COP1_Unknown,COP1_Unknown,COP1_Unknown,COP1_Unknown,COP1_Unknown,
C_F, COP1_Unknown,C_EQ, COP1_Unknown,C_LT, COP1_Unknown,C_LE, COP1_Unknown,
COP1_Unknown,COP1_Unknown,COP1_Unknown,COP1_Unknown,COP1_Unknown,COP1_Unknown,COP1_Unknown,COP1_Unknown,
};
void (*Int_COP1SPrintTable[64])() = {
ADD_S, SUB_S, MUL_S, DIV_S, SQRT_S, ABS_S, MOV_S, NEG_S,
COP1_Unknown,COP1_Unknown,COP1_Unknown,COP1_Unknown,COP1_Unknown,COP1_Unknown,COP1_Unknown,COP1_Unknown,
COP1_Unknown,COP1_Unknown,COP1_Unknown,COP1_Unknown,COP1_Unknown,COP1_Unknown,RSQRT_S, COP1_Unknown,
ADDA_S, SUBA_S, MULA_S, COP1_Unknown,MADD_S, MSUB_S, MADDA_S, MSUBA_S,
COP1_Unknown,COP1_Unknown,COP1_Unknown,COP1_Unknown,CVT_W, COP1_Unknown,COP1_Unknown,COP1_Unknown,
MAX_S, MIN_S, COP1_Unknown,COP1_Unknown,COP1_Unknown,COP1_Unknown,COP1_Unknown,COP1_Unknown,
C_F, COP1_Unknown,C_EQ, COP1_Unknown,C_LT, COP1_Unknown,C_LE, COP1_Unknown,
COP1_Unknown,COP1_Unknown,COP1_Unknown,COP1_Unknown,COP1_Unknown,COP1_Unknown,COP1_Unknown,COP1_Unknown,
};
void (*Int_COP1WPrintTable[64])() = {
COP1_Unknown,COP1_Unknown,COP1_Unknown,COP1_Unknown,COP1_Unknown,COP1_Unknown,COP1_Unknown,COP1_Unknown,
COP1_Unknown,COP1_Unknown,COP1_Unknown,COP1_Unknown,COP1_Unknown,COP1_Unknown,COP1_Unknown,COP1_Unknown,
COP1_Unknown,COP1_Unknown,COP1_Unknown,COP1_Unknown,COP1_Unknown,COP1_Unknown,COP1_Unknown,COP1_Unknown,
COP1_Unknown,COP1_Unknown,COP1_Unknown,COP1_Unknown,COP1_Unknown,COP1_Unknown,COP1_Unknown,COP1_Unknown,
CVT_S, COP1_Unknown,COP1_Unknown,COP1_Unknown,COP1_Unknown,COP1_Unknown,COP1_Unknown,COP1_Unknown,
COP1_Unknown,COP1_Unknown,COP1_Unknown,COP1_Unknown,COP1_Unknown,COP1_Unknown,COP1_Unknown,COP1_Unknown,
COP1_Unknown,COP1_Unknown,COP1_Unknown,COP1_Unknown,COP1_Unknown,COP1_Unknown,COP1_Unknown,COP1_Unknown,
COP1_Unknown,COP1_Unknown,COP1_Unknown,COP1_Unknown,COP1_Unknown,COP1_Unknown,COP1_Unknown,COP1_Unknown,
};
static const OPCODE tbl_COP1_W[64] =
{
COP1_Unknown,COP1_Unknown,COP1_Unknown,COP1_Unknown,COP1_Unknown,COP1_Unknown,COP1_Unknown,COP1_Unknown,
COP1_Unknown,COP1_Unknown,COP1_Unknown,COP1_Unknown,COP1_Unknown,COP1_Unknown,COP1_Unknown,COP1_Unknown,
COP1_Unknown,COP1_Unknown,COP1_Unknown,COP1_Unknown,COP1_Unknown,COP1_Unknown,COP1_Unknown,COP1_Unknown,
COP1_Unknown,COP1_Unknown,COP1_Unknown,COP1_Unknown,COP1_Unknown,COP1_Unknown,COP1_Unknown,COP1_Unknown,
CVT_S, COP1_Unknown,COP1_Unknown,COP1_Unknown,COP1_Unknown,COP1_Unknown,COP1_Unknown,COP1_Unknown,
COP1_Unknown,COP1_Unknown,COP1_Unknown,COP1_Unknown,COP1_Unknown,COP1_Unknown,COP1_Unknown,COP1_Unknown,
COP1_Unknown,COP1_Unknown,COP1_Unknown,COP1_Unknown,COP1_Unknown,COP1_Unknown,COP1_Unknown,COP1_Unknown,
COP1_Unknown,COP1_Unknown,COP1_Unknown,COP1_Unknown,COP1_Unknown,COP1_Unknown,COP1_Unknown,COP1_Unknown,
};
} // end namespace R5900::OpcodeTables
namespace Opcodes
{
using namespace OpcodeTables;
const OPCODE& Class_SPECIAL() { return tbl_Special[_Funct_]; }
const OPCODE& Class_REGIMM() { return tbl_RegImm[_Rt_]; }
const OPCODE& Class_MMI() { return tbl_MMI[_Funct_]; }
const OPCODE& Class_MMI0() { return tbl_MMI0[_Sa_]; }
const OPCODE& Class_MMI1() { return tbl_MMI1[_Sa_]; }
const OPCODE& Class_MMI2() { return tbl_MMI2[_Sa_]; }
const OPCODE& Class_MMI3() { return tbl_MMI3[_Sa_]; }
const OPCODE& Class_COP0() { return tbl_COP0[_Rs_]; }
const OPCODE& Class_COP0_BC0() { return tbl_COP0_BC0[(cpuRegs.code >> 16) & 0x03]; }
const OPCODE& Class_COP0_C0() { return tbl_COP0_C0[_Funct_]; }
const OPCODE& Class_COP1() { return tbl_COP1[_Rs_]; }
const OPCODE& Class_COP1_BC1() { return tbl_COP1_BC1[_Rt_]; }
const OPCODE& Class_COP1_S() { return tbl_COP1_S[_Funct_]; }
const OPCODE& Class_COP1_W() { return tbl_COP1_W[_Funct_]; }
// These are for future use when the COP2 tables are completed.
//const OPCODE& Class_COP2() { return tbl_COP2[_Rs_]; }
//const OPCODE& Class_COP2_BC2() { return tbl_COP2_BC2[_Rt_]; }
//const OPCODE& Class_COP2_SPECIAL() { return tbl_COP2_SPECIAL[_Funct_]; }
//const OPCODE& Class_COP2_SPECIAL2() { return tbl_COP2_SPECIAL2[(cpuRegs.code & 0x3) | ((cpuRegs.code >> 4) & 0x7c)]; }
}
} // end namespace R5900
void (*Int_COP2PrintTable[32])() = {
COP2_Unknown, QMFC2, CFC2, COP2_Unknown, COP2_Unknown, QMTC2, CTC2, COP2_Unknown,

1285
pcsx2/InterTables.h
View File

File diff suppressed because it is too large Load Diff

208
pcsx2/Interpreter.cpp
View File

@ -26,55 +26,75 @@
#include <float.h>
const char *bios[256]={
//0x00
"RFU000_FullReset", "ResetEE", "SetGsCrt", "RFU003",
"Exit", "RFU005", "LoadExecPS2", "ExecPS2",
"RFU008", "RFU009", "AddSbusIntcHandler", "RemoveSbusIntcHandler",
"Interrupt2Iop", "SetVTLBRefillHandler", "SetVCommonHandler", "SetVInterruptHandler",
//0x10
"AddIntcHandler", "RemoveIntcHandler", "AddDmacHandler", "RemoveDmacHandler",
"_EnableIntc", "_DisableIntc", "_EnableDmac", "_DisableDmac",
"_SetAlarm", "_ReleaseAlarm", "_iEnableIntc", "_iDisableIntc",
"_iEnableDmac", "_iDisableDmac", "_iSetAlarm", "_iReleaseAlarm",
//0x20
"CreateThread", "DeleteThread", "StartThread", "ExitThread",
"ExitDeleteThread", "TerminateThread", "iTerminateThread", "DisableDispatchThread",
"EnableDispatchThread", "ChangeThreadPriority", "iChangeThreadPriority", "RotateThreadReadyQueue",
"iRotateThreadReadyQueue", "ReleaseWaitThread", "iReleaseWaitThread", "GetThreadId",
//0x30
"ReferThreadStatus","iReferThreadStatus", "SleepThread", "WakeupThread",
"_iWakeupThread", "CancelWakeupThread", "iCancelWakeupThread", "SuspendThread",
"iSuspendThread", "ResumeThread", "iResumeThread", "JoinThread",
"RFU060", "RFU061", "EndOfHeap", "RFU063",
//0x40
"CreateSema", "DeleteSema", "SignalSema", "iSignalSema",
"WaitSema", "PollSema", "iPollSema", "ReferSemaStatus",
"iReferSemaStatus", "RFU073", "SetOsdConfigParam", "GetOsdConfigParam",
"GetGsHParam", "GetGsVParam", "SetGsHParam", "SetGsVParam",
//0x50
"RFU080_CreateEventFlag", "RFU081_DeleteEventFlag",
"RFU082_SetEventFlag", "RFU083_iSetEventFlag",
"RFU084_ClearEventFlag", "RFU085_iClearEventFlag",
"RFU086_WaitEventFlag", "RFU087_PollEventFlag",
"RFU088_iPollEventFlag", "RFU089_ReferEventFlagStatus",
"RFU090_iReferEventFlagStatus", "RFU091_GetEntryAddress",
"EnableIntcHandler_iEnableIntcHandler",
"DisableIntcHandler_iDisableIntcHandler",
"EnableDmacHandler_iEnableDmacHandler",
"DisableDmacHandler_iDisableDmacHandler",
//0x60
"KSeg0", "EnableCache", "DisableCache", "GetCop0",
"FlushCache", "RFU101", "CpuConfig", "iGetCop0",
"iFlushCache", "RFU105", "iCpuConfig", "sceSifStopDma",
"SetCPUTimerHandler", "SetCPUTimer", "SetOsdConfigParam2", "SetOsdConfigParam2",
//0x70
"GsGetIMR_iGsGetIMR", "GsGetIMR_iGsPutIMR", "SetPgifHandler", "SetVSyncFlag",
"RFU116", "print", "sceSifDmaStat_isceSifDmaStat", "sceSifSetDma_isceSifSetDma",
"sceSifSetDChain_isceSifSetDChain", "sceSifSetReg", "sceSifGetReg", "ExecOSD",
"Deci2Call", "PSMode", "MachineType", "GetMemorySize",
};
extern void iDumpVU0Registers();
extern void iDumpVU1Registers();
extern u32 vudump;
extern int vu0branch, vu1branch;
namespace R5900
{
const char * const bios[256]=
{
//0x00
"RFU000_FullReset", "ResetEE", "SetGsCrt", "RFU003",
"Exit", "RFU005", "LoadExecPS2", "ExecPS2",
"RFU008", "RFU009", "AddSbusIntcHandler", "RemoveSbusIntcHandler",
"Interrupt2Iop", "SetVTLBRefillHandler", "SetVCommonHandler", "SetVInterruptHandler",
//0x10
"AddIntcHandler", "RemoveIntcHandler", "AddDmacHandler", "RemoveDmacHandler",
"_EnableIntc", "_DisableIntc", "_EnableDmac", "_DisableDmac",
"_SetAlarm", "_ReleaseAlarm", "_iEnableIntc", "_iDisableIntc",
"_iEnableDmac", "_iDisableDmac", "_iSetAlarm", "_iReleaseAlarm",
//0x20
"CreateThread", "DeleteThread", "StartThread", "ExitThread",
"ExitDeleteThread", "TerminateThread", "iTerminateThread", "DisableDispatchThread",
"EnableDispatchThread", "ChangeThreadPriority", "iChangeThreadPriority", "RotateThreadReadyQueue",
"iRotateThreadReadyQueue", "ReleaseWaitThread", "iReleaseWaitThread", "GetThreadId",
//0x30
"ReferThreadStatus","iReferThreadStatus", "SleepThread", "WakeupThread",
"_iWakeupThread", "CancelWakeupThread", "iCancelWakeupThread", "SuspendThread",
"iSuspendThread", "ResumeThread", "iResumeThread", "JoinThread",
"RFU060", "RFU061", "EndOfHeap", "RFU063",
//0x40
"CreateSema", "DeleteSema", "SignalSema", "iSignalSema",
"WaitSema", "PollSema", "iPollSema", "ReferSemaStatus",
"iReferSemaStatus", "RFU073", "SetOsdConfigParam", "GetOsdConfigParam",
"GetGsHParam", "GetGsVParam", "SetGsHParam", "SetGsVParam",
//0x50
"RFU080_CreateEventFlag", "RFU081_DeleteEventFlag",
"RFU082_SetEventFlag", "RFU083_iSetEventFlag",
"RFU084_ClearEventFlag", "RFU085_iClearEventFlag",
"RFU086_WaitEventFlag", "RFU087_PollEventFlag",
"RFU088_iPollEventFlag", "RFU089_ReferEventFlagStatus",
"RFU090_iReferEventFlagStatus", "RFU091_GetEntryAddress",
"EnableIntcHandler_iEnableIntcHandler",
"DisableIntcHandler_iDisableIntcHandler",
"EnableDmacHandler_iEnableDmacHandler",
"DisableDmacHandler_iDisableDmacHandler",
//0x60
"KSeg0", "EnableCache", "DisableCache", "GetCop0",
"FlushCache", "RFU101", "CpuConfig", "iGetCop0",
"iFlushCache", "RFU105", "iCpuConfig", "sceSifStopDma",
"SetCPUTimerHandler", "SetCPUTimer", "SetOsdConfigParam2", "SetOsdConfigParam2",
//0x70
"GsGetIMR_iGsGetIMR", "GsGetIMR_iGsPutIMR", "SetPgifHandler", "SetVSyncFlag",
"RFU116", "print", "sceSifDmaStat_isceSifDmaStat", "sceSifSetDma_isceSifSetDma",
"sceSifSetDChain_isceSifSetDChain", "sceSifSetReg", "sceSifGetReg", "ExecOSD",
"Deci2Call", "PSMode", "MachineType", "GetMemorySize",
};
const OPCODE& GetCurrentInstruction()
{
const OPCODE* opcode = &R5900::OpcodeTables::tbl_Standard[_Opcode_];
while( opcode->getsubclass != NULL )
opcode = &opcode->getsubclass();
return *opcode;
}
namespace Interpreter
{
int branch2 = 0;
static u32 branchPC;
@ -83,8 +103,8 @@ static u32 branchPC;
#ifdef PCSX2_DEVBUILD
static void debugI()
{
//CPU_LOG("%s\n", disR5900Current.getString());
if (cpuRegs.GPR.n.r0.UD[0] || cpuRegs.GPR.n.r0.UD[1]) SysPrintf("R0 is not zero!!!!\n");
//CPU_LOG("%s\n", disR5900Current.getCString());
if (cpuRegs.GPR.n.r0.UD[0] || cpuRegs.GPR.n.r0.UD[1]) Console::Error("R0 is not zero!!!!");
}
#else
static void debugI() {}
@ -92,19 +112,6 @@ static void debugI() {}
static u32 cpuBlockCycles = 0; // 3 bit fixed point version of cycle count
namespace EE
{
const OPCODE& GetCurrentInstruction()
{
const EE::OPCODE* opcode = &EE::OpcodeTables::Standard[_Opcode_];
while( opcode->getsubclass != NULL )
opcode = &opcode->getsubclass();
return *opcode;
}
}
static std::string disOut;
static __forceinline void execI()
@ -116,14 +123,9 @@ static __forceinline void execI()
cpuRegs.code = *(u32 *)PSM(cpuRegs.pc);
#endif
const EE::OPCODE& opcode = EE::GetCurrentInstruction();
/*disOut.assign( "\n" );
opcode.decode( disOut );
SysPrintf( disOut.c_str() );*/
const OPCODE& opcode = GetCurrentInstruction();
cpuBlockCycles += opcode.cycles;
//cpuRegs.cycle++;
cpuRegs.pc += 4;
opcode.interpret();
@ -150,58 +152,16 @@ void intSetBranch() {
branch2 = 1;
}
//****************************************************************
// Used to manage FPU Opcodes
//****************************************************************
void COP1_BC1() {
Int_COP1BC1PrintTable[_Rt_]();
}
void COP1_S() {
Int_COP1SPrintTable[_Funct_]();
}
void COP1_W() {
Int_COP1WPrintTable[_Funct_]();
}
void COP1_Unknown() {
FPU_LOG("Unknown FPU opcode called\n");
}
namespace EE { namespace Opcodes
{
const OPCODE& Class_SPECIAL() { return EE::OpcodeTables::Special[_Funct_]; }
const OPCODE& Class_REGIMM() { return EE::OpcodeTables::RegImm[_Rt_]; }
const OPCODE& Class_MMI() { return EE::OpcodeTables::MMI[_Funct_]; }
const OPCODE& Class_MMI0() { return EE::OpcodeTables::MMI0[_Sa_]; }
const OPCODE& Class_MMI1() { return EE::OpcodeTables::MMI1[_Sa_]; }
const OPCODE& Class_MMI2() { return EE::OpcodeTables::MMI2[_Sa_]; }
const OPCODE& Class_MMI3() { return EE::OpcodeTables::MMI3[_Sa_]; }
//const OPCODE& Class_COP0() { return EE::OpcodeTables::COP1[_Rs_]; }
//const OPCODE& Class_COP1() { return EE::OpcodeTables::COP1[_Rs_]; }
//const OPCODE& Class_COP2() { return EE::OpcodeTables::COP2[_Rs_]; }
} }
namespace EE { namespace Interpreter { namespace OpcodeImpl
{
void COP0()
{
Int_COP0PrintTable[_Rs_]();
void COP0_Unknown(){
CPU_LOG("COP0 Unknown opcode called\n");
}
void COP1()
namespace OpcodeImpl
{
FPU_LOG("%s\n", disR5900Current.getString() );
Int_COP1PrintTable[_Rs_]();
}
void COP2()
{
std::string disOut;
@ -215,6 +175,11 @@ void Unknown() {
CPU_LOG("%8.8lx: Unknown opcode called\n", cpuRegs.pc);
}
void MMI_Unknown() { Console::Notice("Unknown MMI opcode called"); }
void COP0_Unknown() { Console::Notice("Unknown COP0 opcode called"); }
void COP1_Unknown() { Console::Notice("Unknown FPU/COP1 opcode called"); }
/*********************************************************
* Arithmetic with immediate operand *
* Format: OP rt, rs, immediate *
@ -1014,9 +979,9 @@ void MTSAH() {
cpuRegs.sa = ((cpuRegs.GPR.r[_Rs_].UL[0] & 0x7) ^ (_Imm_ & 0x7)) << 4;
}
} } } // end EE::Interpreter::OpcodeImpl namespace
} // end namespace R5900::Interpreter::OpcodeImpl
///////////////////////////////////////////
////////////////////////////////////////////////////////
void intInit() {
//detect cpu for use the optimaze asm code
@ -1036,12 +1001,6 @@ static void intExecuteBlock() {
while (!branch2) execI();
}
extern void iDumpVU0Registers();
extern void iDumpVU1Registers();
extern u32 vudump;
extern int vu0branch, vu1branch;
void intExecuteVU0Block() {
int i;
@ -1124,6 +1083,10 @@ void intVU1Clear(u32 Addr, u32 Size) {
void intShutdown() {
}
}
using namespace Interpreter;
R5900cpu intCpu = {
intInit,
intReset,
@ -1140,3 +1103,4 @@ R5900cpu intCpu = {
intShutdown
};
}

8
pcsx2/MMI.cpp
View File

@ -23,11 +23,11 @@
#include "R5900.h"
#include "InterTables.h"
namespace EE { namespace Interpreter{ namespace OpcodeImpl
namespace R5900 {
namespace Interpreter {
namespace OpcodeImpl
{
void MMI_Unknown() { Console::Notice("Unknown MMI opcode called"); }
//*****************MMI OPCODES*********************************
void MADD() {
@ -1544,4 +1544,4 @@ void PEXCW() {
// obs:
// QFSRV not verified
}}} // end namespace EE::Interpreter::OpcodeImpl
}}} // end namespace R5900::Interpreter::OpcodeImpl

8
pcsx2/MTGS.cpp
View File

@ -51,7 +51,6 @@ using namespace std;
#define volatize(x) (*(u8* volatile*)&(x)) // for writepos
#define volatize_c(x) (*(u8 * volatile*)&(x)) // for readpos
/////////////////////////////////////////////////////////////////////////////
// BEGIN -- MTGS GIFtag Parse Implementation
//
@ -209,9 +208,6 @@ mtgsThreadObject::mtgsThreadObject() :
, m_lock_Stack()
#endif
{
memcpy_raz_( m_gsMem, PS2MEM_GS, sizeof(m_gsMem) );
GSsetBaseMem( m_gsMem );
// Wait for the thread to finish initialization (it runs GSinit, which can take
// some time since it's creating a new window and all), and then check for errors.
@ -432,6 +428,10 @@ __forceinline u32 mtgsThreadObject::_gifTransferDummy( GIF_PATH pathidx, const u
int mtgsThreadObject::Callback()
{
Console::WriteLn("MTGS > Thread Started, Opening GS Plugin...");
memcpy_raz_( m_gsMem, PS2MEM_GS, sizeof(m_gsMem) );
GSsetBaseMem( m_gsMem );
m_returncode = GSopen((void *)&pDsp, "PCSX2", 1);
GSCSRr = 0x551B400F; // 0x55190000
m_wait_InitDone.Set();

7
pcsx2/Memory.cpp
View File

@ -59,6 +59,9 @@ BIOS
#include "GS.h"
#include "vtlb.h"
using namespace Dynarec;
using namespace Dynarec::R5900;
#ifdef ENABLECACHE
#include "Cache.h"
#endif
@ -2721,13 +2724,13 @@ void loadBiosRom( const char *ext, u8 *dest, long maxSize )
Path::Combine( Bios, Config.BiosDir, Config.Bios );
ssprintf(Bios1, "%S.%s", params &Bios, ext);
ssprintf(Bios1, "%hs.%s", params &Bios, ext);
if( (filesize=Path::isFile( Bios1 ) ) <= 0 )
{
Path::ReplaceExtension( Bios1, Bios, ext );
if( (filesize=Path::isFile( Bios1 ) ) <= 0 )
{
// And this check is... well I'm not sure whf this check is trying to accomplish! (air)
// And this check is... well I'm not sure wtf this check is trying to accomplish! (air)
ssprintf( Bios1, "%s%s.bin", params Config.BiosDir, ext );
if( (filesize=Path::isFile( Bios1 ) ) <= 0 )
{

15
pcsx2/Misc.cpp
View File

@ -42,6 +42,8 @@
#include "Paths.h"
using namespace std;
using namespace Dynarec;
using namespace R5900;
PcsxConfig Config;
u32 BiosVersion;
@ -376,8 +378,6 @@ int GetPS2ElfName(char *name){
return 2;
}
extern u32 dumplog;
#ifdef PCSX2_DEVBUILD
void SaveGSState(const string& file)
@ -494,7 +494,7 @@ char *ParseLang(char *id) {
#define NUM_STATES 10
int StatesC = 0;
extern void iDumpRegisters(u32 startpc, u32 temp);
extern char strgametitle[256];
char* mystrlwr( char* string )
@ -553,7 +553,7 @@ void ProcessFKeys(int fkey, int shift)
{
SaveState::GetFilename( Text, StatesC );
gzLoadingState joe( Text ); // throws exception on version mismatch
cpuReset();
R5900::cpuReset();
joe.FreezeAll();
}
catch( Exception::StateLoadError_Recoverable& )
@ -576,7 +576,7 @@ void ProcessFKeys(int fkey, int shift)
"Pcsx2 encountered an error while trying to load the savestate\n"
"and emulation had to be aborted." );
cpuShutdown();
R5900::cpuShutdown();
ClosePlugins();
throw Exception::CpuStateShutdown(
@ -632,7 +632,8 @@ void ProcessFKeys(int fkey, int shift)
// [Air]: Do we really want to save runtime changes to frameskipping?
//SaveConfig();
}
break;
break;
// note: VK_F5-VK_F7 are reserved for GS
case 8:
GSmakeSnapshot("snap/");
@ -699,8 +700,8 @@ void ProcessFKeys(int fkey, int shift)
}
else {
if( GSsetupRecording != NULL ) GSsetupRecording(g_Pcsx2Recording, NULL);
if( SPU2setupRecording != NULL ) SPU2setupRecording(g_Pcsx2Recording, NULL);
}
if( SPU2setupRecording != NULL ) SPU2setupRecording(g_Pcsx2Recording, NULL);
}
break;
}

12
pcsx2/Misc.h
View File

@ -193,12 +193,20 @@ struct romdir{
u32 GetBiosVersion();
int IsBIOS(char *filename, char *description);
// check to see if needs freezing
extern u32 g_sseVUMXCSR, g_sseMXCSR;
void SetCPUState(u32 sseMXCSR, u32 sseVUMXCSR);
// when using mmx/xmm regs, use; 0 is load
// freezes no matter the state
extern void FreezeXMMRegs_(int save);
extern void FreezeMMXRegs_(int save);
extern bool g_EEFreezeRegs;
#define FreezeXMMRegs(save) if( g_EEFreezeRegs ) { FreezeXMMRegs_(save); }
extern u8 g_globalMMXSaved;
extern u8 g_globalXMMSaved;
// these macros check to see if needs freezing
#define FreezeXMMRegs(save) if( g_EEFreezeRegs ) { FreezeXMMRegs_(save); }
#define FreezeMMXRegs(save) if( g_EEFreezeRegs ) { FreezeMMXRegs_(save); }

4
pcsx2/Patch.cpp
View File

@ -567,14 +567,14 @@ void patchFunc_xkickdelay( char * cmd, char * param )
void patchFunc_fastmemory( char * cmd, char * param )
{
// only valid for recompilers
EE::Dynarec::SetFastMemory(1);
Dynarec::SetFastMemory(1);
}
void patchFunc_vunanmode( char * cmd, char * param )
{
// only valid for recompilers
SetVUNanMode(param != NULL ? atoi(param) : 1);
Dynarec::SetVUNanMode(param != NULL ? atoi(param) : 1);
}
void patchFunc_path3hack( char * cmd, char * param )

13
pcsx2/Patch.h
View File

@ -117,13 +117,11 @@ void resetpatch( void );
int AddPatch(int Mode, int Place, int Address, int Size, u64 data);
namespace EE { namespace Dynarec {
void SetFastMemory(int); // iR5900LoadStore.c
} }
void SetVUNanMemory(int); // iVUmicro.c
extern void SetVUNanMode(int mode);
namespace Dynarec {
extern void SetFastMemory(int); // iR5900LoadStore.c
extern void SetVUNanMemory(int); // iVUmicro.c
extern void SetVUNanMode(int mode);
}
extern int path3hack;
extern int g_FFXHack;
@ -132,7 +130,6 @@ extern int g_ZeroGSOptions;
extern u32 g_sseMXCSR;
extern u32 g_sseVUMXCSR;
void SetCPUState(u32 sseMXCSR, u32 sseVUMXCSR);
void SetRoundMode(u32 ee, u32 vu);
int LoadPatch(const std::string& patchfile);

20
pcsx2/Plugins.cpp
View File

@ -223,7 +223,7 @@ USBhandler usbHandler;
#define MapSymbolVar_Error(var,name) if((MapSymbolVar(var,name))==NULL) \
{ \
const char* errString = SysLibError(); \
Msgbox::Alert("%s: Error loading %S: %s", params &filename, #name, errString); \
Msgbox::Alert("%s: Error loading %hs: %s", params &filename, #name, errString); \
return -1; \
}
@ -251,7 +251,7 @@ int _TestPS2Esyms(void* drv, int type, int expected_version, const string& filen
int actual_version = ((PS2EgetLibVersion2(type) >> 16)&0xff);
if( actual_version != expected_version) {
Msgbox::Alert("Can't load '%S', wrong PS2E version (%x != %x)", params &filename, actual_version, expected_version);
Msgbox::Alert("Can't load '%hs', wrong PS2E version (%x != %x)", params &filename, actual_version, expected_version);
return -1;
}
@ -287,7 +287,7 @@ int LoadGSplugin(const string& filename)
void *drv;
GSplugin = SysLoadLibrary(filename.c_str());
if (GSplugin == NULL) { Msgbox::Alert ("Could Not Load GS Plugin '%S': %s", params &filename, SysLibError()); return -1; }
if (GSplugin == NULL) { Msgbox::Alert ("Could Not Load GS Plugin '%hs': %s", params &filename, SysLibError()); return -1; }
drv = GSplugin;
TestPS2Esyms(GS);
MapSymbol_Error(GSinit);
@ -339,7 +339,7 @@ int LoadPAD1plugin(const string& filename) {
void *drv;
PAD1plugin = SysLoadLibrary(filename.c_str());
if (PAD1plugin == NULL) { Msgbox::Alert("Could Not Load PAD1 Plugin '%S': %s", params &filename, SysLibError()); return -1; }
if (PAD1plugin == NULL) { Msgbox::Alert("Could Not Load PAD1 Plugin '%hs': %s", params &filename, SysLibError()); return -1; }
drv = PAD1plugin;
TestPS2Esyms(PAD);
MapSymbolPAD_Error(PAD1,PAD,init);
@ -370,7 +370,7 @@ int LoadPAD2plugin(const string& filename) {
void *drv;
PAD2plugin = SysLoadLibrary(filename.c_str());
if (PAD2plugin == NULL) { Msgbox::Alert("Could Not Load PAD2 Plugin '%S': %s", params &filename, SysLibError()); return -1; }
if (PAD2plugin == NULL) { Msgbox::Alert("Could Not Load PAD2 Plugin '%hs': %s", params &filename, SysLibError()); return -1; }
drv = PAD2plugin;
TestPS2Esyms(PAD);
MapSymbolPAD_Error(PAD2,PAD,init);
@ -402,7 +402,7 @@ int LoadSPU2plugin(const string& filename) {
void *drv;
SPU2plugin = SysLoadLibrary(filename.c_str());
if (SPU2plugin == NULL) { Msgbox::Alert("Could Not Load SPU2 Plugin '%S': %s", params &filename, SysLibError()); return -1; }
if (SPU2plugin == NULL) { Msgbox::Alert("Could Not Load SPU2 Plugin '%hs': %s", params &filename, SysLibError()); return -1; }
drv = SPU2plugin;
TestPS2Esyms(SPU2);
MapSymbol_Error(SPU2init);
@ -445,7 +445,7 @@ int LoadCDVDplugin(const string& filename) {
void *drv;
CDVDplugin = SysLoadLibrary(filename.c_str());
if (CDVDplugin == NULL) { Msgbox::Alert("Could Not Load CDVD Plugin '%S': %s", params &filename, SysLibError()); return -1; }
if (CDVDplugin == NULL) { Msgbox::Alert("Could Not Load CDVD Plugin '%hs': %s", params &filename, SysLibError()); return -1; }
drv = CDVDplugin;
TestPS2Esyms(CDVD);
MapSymbol_Error(CDVDinit);
@ -482,7 +482,7 @@ int LoadDEV9plugin(const string& filename) {
void *drv;
DEV9plugin = SysLoadLibrary(filename.c_str());
if (DEV9plugin == NULL) { Msgbox::Alert("Could Not Load DEV9 Plugin '%S': %s", params &filename, SysLibError()); return -1; }
if (DEV9plugin == NULL) { Msgbox::Alert("Could Not Load DEV9 Plugin '%hs': %s", params &filename, SysLibError()); return -1; }
drv = DEV9plugin;
TestPS2Esyms(DEV9);
MapSymbol_Error(DEV9init);
@ -519,7 +519,7 @@ int LoadUSBplugin(const string& filename) {
void *drv;
USBplugin = SysLoadLibrary(filename.c_str());
if (USBplugin == NULL) { Msgbox::Alert("Could Not Load USB Plugin '%S': %s", params &filename, SysLibError()); return -1; }
if (USBplugin == NULL) { Msgbox::Alert("Could Not Load USB Plugin '%hs': %s", params &filename, SysLibError()); return -1; }
drv = USBplugin;
TestPS2Esyms(USB);
MapSymbol_Error(USBinit);
@ -556,7 +556,7 @@ int LoadFWplugin(const string& filename) {
void *drv;
FWplugin = SysLoadLibrary(filename.c_str());
if (FWplugin == NULL) { Msgbox::Alert("Could Not Load FW Plugin '%S': %s", params &filename, SysLibError()); return -1; }
if (FWplugin == NULL) { Msgbox::Alert("Could Not Load FW Plugin '%hs': %s", params &filename, SysLibError()); return -1; }
drv = FWplugin;
TestPS2Esyms(FW);
MapSymbol_Error(FWinit);

28
pcsx2/PsxHw.h
View File

@ -100,31 +100,31 @@ extern void psxSetNextBranchDelta( s32 delta );
void psxHwReset();
u8 psxHwRead8 (u32 add);
int psxHwConstRead8(u32 x86reg, u32 add, u32 sign);
u16 psxHwRead16(u32 add);
int psxHwConstRead16(u32 x86reg, u32 add, u32 sign);
u32 psxHwRead32(u32 add);
int psxHwConstRead32(u32 x86reg, u32 add);
void psxHwWrite8 (u32 add, u8 value);
void psxHwConstWrite8(u32 add, int mmreg);
void psxHwWrite16(u32 add, u16 value);
void psxHwConstWrite16(u32 add, int mmreg);
void psxHwWrite32(u32 add, u32 value);
void psxHwConstWrite32(u32 add, int mmreg);
u8 psxHw4Read8 (u32 add);
int psxHw4ConstRead8 (u32 x86reg, u32 add, u32 sign);
void psxHw4Write8(u32 add, u8 value);
void psxHw4ConstWrite8(u32 add, int mmreg);
int psxHwFreeze(gzFile f, int Mode);
void psxDmaInterrupt(int n);
void psxDmaInterrupt2(int n);
int psxHwFreeze(gzFile f, int Mode);
namespace Dynarec
{
int psxHwConstRead8(u32 x86reg, u32 add, u32 sign);
int psxHwConstRead16(u32 x86reg, u32 add, u32 sign);
int psxHwConstRead32(u32 x86reg, u32 add);
void psxHwConstWrite8(u32 add, int mmreg);
void psxHwConstWrite16(u32 add, int mmreg);
void psxHwConstWrite32(u32 add, int mmreg);
int psxHw4ConstRead8 (u32 x86reg, u32 add, u32 sign);
void psxHw4ConstWrite8(u32 add, int mmreg);
}
#endif /* __PSXHW_H__ */

1
pcsx2/PsxMem.cpp
View File

@ -24,7 +24,6 @@
#include "Hw.h"
#include "iR3000A.h"
extern u32 g_psxMaxRecMem;
int g_psxWriteOk=1;
static u32 writectrl;

30
pcsx2/PsxMem.h
View File

@ -96,24 +96,26 @@ void psxMemWrite8 (u32 mem, u8 value);
void psxMemWrite16(u32 mem, u16 value);
void psxMemWrite32(u32 mem, u32 value);
// x86reg and mmreg are always x86 regs
void psxRecMemRead8();
int psxRecMemConstRead8(u32 x86reg, u32 mem, u32 sign);
namespace Dynarec
{
// x86reg and mmreg are always x86 regs
void psxRecMemRead8();
int psxRecMemConstRead8(u32 x86reg, u32 mem, u32 sign);
void psxRecMemRead16();
int psxRecMemConstRead16(u32 x86reg, u32 mem, u32 sign);
void psxRecMemRead16();
int psxRecMemConstRead16(u32 x86reg, u32 mem, u32 sign);
void psxRecMemRead32();
int psxRecMemConstRead32(u32 x86reg, u32 mem);
void psxRecMemRead32();
int psxRecMemConstRead32(u32 x86reg, u32 mem);
void psxRecMemWrite8();
int psxRecMemConstWrite8(u32 mem, int mmreg);
void psxRecMemWrite8();
int psxRecMemConstWrite8(u32 mem, int mmreg);
void psxRecMemWrite16();
int psxRecMemConstWrite16(u32 mem, int mmreg);
void psxRecMemWrite32();
int psxRecMemConstWrite32(u32 mem, int mmreg);
void psxRecMemWrite16();
int psxRecMemConstWrite16(u32 mem, int mmreg);
void psxRecMemWrite32();
int psxRecMemConstWrite32(u32 mem, int mmreg);
}
#endif /* __PSXMEMORY_H__ */

6
pcsx2/R3000A.cpp
View File

@ -201,7 +201,7 @@ __forceinline void PSX_INT( IopEventId n, s32 ecycle )
// fixme - this doesn't take into account EE/IOP sync (the IOP may be running
// ahead or behind the EE as per the EEsCycles value)
s32 iopDelta = (g_psxNextBranchCycle-psxRegs.cycle)*8;
cpuSetNextBranchDelta( iopDelta );
R5900::cpuSetNextBranchDelta( iopDelta );
}
}
@ -276,12 +276,12 @@ void iopTestIntc()
if( psxHu32(0x1078) == 0 ) return;
if( (psxHu32(0x1070) & psxHu32(0x1074)) == 0 ) return;
if( !eeEventTestIsActive )
if( !R5900::EventTestIsActive )
{
// An iop exception has occured while the EE is running code.
// Inform the EE to branch so the IOP can handle it promptly:
cpuSetNextBranchDelta( 16 );
R5900::cpuSetNextBranchDelta( 16 );
iopBranchAction = true;
//Console::Error( "** IOP Needs an EE EventText, kthx ** %d", params psxCycleEE );

97
pcsx2/R5900.cpp
View File

@ -28,6 +28,16 @@
#include "Paths.h"
#ifdef _DEBUG
extern u32 s_vucount;
#endif
namespace R5900
{
s32 EEsCycle; // used to sync the IOP to the EE
u32 EEoCycle;
static int inter;
PCSX2_ALIGNED16(cpuRegisters cpuRegs);
@ -38,18 +48,12 @@ PCSX2_ALIGNED16(GPR_reg64 g_cpuConstRegs[32]) = {0};
u32 g_cpuHasConstReg = 0, g_cpuFlushedConstReg = 0;
R5900cpu *Cpu;
s32 EEsCycle; // used to sync the IOP to the EE
u32 EEoCycle;
u32 bExecBIOS = 0; // set if the BIOS has already been executed
static bool cpuIsInitialized = false;
static uint eeWaitCycles = 1024;
bool eeEventTestIsActive = false;
#ifdef _DEBUG
extern u32 s_vucount;
#endif
bool EventTestIsActive = false;
bool cpuInit()
{
@ -100,7 +104,7 @@ bool cpuInit()
if( !CreateProcess(strexe.c_str(), "", NULL, NULL, FALSE, DETACHED_PROCESS|CREATE_NEW_PROCESS_GROUP, NULL, strdir.GetPtr(), &si, &pi))
{
MessageBox(NULL, fmt_string( "Failed to launch %S\n", params &strexe ).c_str(), "Failure", MB_OK);
MessageBox(NULL, fmt_string( "Failed to launch %hs\n", params &strexe ).c_str(), "Failure", MB_OK);
}
else
{
@ -400,12 +404,21 @@ __forceinline void cpuSetBranch()
g_nextBranchCycle = cpuRegs.cycle;
}
void cpuClearInt( uint i )
{
jASSUME( i < 32 );
cpuRegs.interrupt &= ~(1 << i);
}
static __forceinline void TESTINT( u8 n, void (*callback)() )
{
if( !(cpuRegs.interrupt & (1 << n)) ) return;
if( cpuTestCycle( cpuRegs.sCycle[n], cpuRegs.eCycle[n] ) )
{
cpuClearInt( n );
callback();
}
else
cpuSetNextBranch( cpuRegs.sCycle[n], cpuRegs.eCycle[n] );
}
@ -439,9 +452,6 @@ static __forceinline void _cpuTestInterrupts()
}
}
u32 s_iLastCOP0Cycle = 0;
u32 s_iLastPERFCycle[2] = {0,0};
static __forceinline void _cpuTestTIMR()
{
cpuRegs.CP0.n.Count += cpuRegs.cycle-s_iLastCOP0Cycle;
@ -495,7 +505,7 @@ u32 g_nextBranchCycle = 0;
// and the recompiler. (moved here to help alleviate redundant code)
static __forceinline void _cpuBranchTest_Shared()
{
eeEventTestIsActive = true;
EventTestIsActive = true;
g_nextBranchCycle = cpuRegs.cycle + eeWaitCycles;
EEsCycle += cpuRegs.cycle - EEoCycle;
@ -609,7 +619,7 @@ static __forceinline void _cpuBranchTest_Shared()
// Apply vsync and other counter nextCycles
cpuSetNextBranch( nextsCounter, nextCounter );
eeEventTestIsActive = false;
EventTestIsActive = false;
// ---- INTC / DMAC Exceptions -----------------
// Raise the INTC and DMAC interrupts here, which usually throw exceptions.
@ -624,11 +634,6 @@ static __forceinline void _cpuBranchTest_Shared()
}
}
#ifdef PCSX2_DEVBUILD
extern u8 g_globalXMMSaved;
extern u8 g_globalMMXSaved;
#endif
void cpuBranchTest()
{
// cpuBranchTest should be called from the recompiler only.
@ -654,26 +659,6 @@ void cpuBranchTest()
g_EEFreezeRegs = true;
}
__forceinline void CPU_INT( u32 n, s32 ecycle)
{
cpuRegs.interrupt|= 1 << n;
cpuRegs.sCycle[n] = cpuRegs.cycle;
cpuRegs.eCycle[n] = ecycle;
// Interrupt is happening soon: make sure both EE and IOP are aware.
if( ecycle <= 28 && psxCycleEE > 0 )
{
// If running in the IOP, force it to break immediately into the EE.
// the EE's branch test is due to run.
psxBreak += psxCycleEE; // record the number of cycles the IOP didn't run.
psxCycleEE = 0;
}
cpuSetNextBranchDelta( cpuRegs.eCycle[n] );
}
void cpuTestINTCInts()
{
if( cpuRegs.interrupt & (1 << 30) ) return;
@ -687,7 +672,7 @@ void cpuTestINTCInts()
// only set the next branch delta if the exception won't be handled for
// the current branch...
if( !eeEventTestIsActive )
if( !EventTestIsActive )
cpuSetNextBranchDelta( 4 );
else if(psxCycleEE > 0)
{
@ -710,7 +695,7 @@ __forceinline void cpuTestDMACInts()
// only set the next branch delta if the exception won't be handled for
// the current branch...
if( !eeEventTestIsActive )
if( !EventTestIsActive )
cpuSetNextBranchDelta( 4 );
else if(psxCycleEE > 0)
{
@ -780,15 +765,27 @@ void IntcpuBranchTest()
// Perform counters, ints, and IOP updates:
_cpuBranchTest_Shared();
if (VU0.VI[REG_VPU_STAT].UL & 0x1) {
Cpu->ExecuteVU0Block();
// This might be needed to keep the EE and VU0 in sync.
// A better fix will require hefty changes to the VU recs. -_-
if(VU0.VI[REG_VPU_STAT].UL & 0x1)
cpuSetNextBranchDelta( 768 );
}
g_EEFreezeRegs = true;
}
__forceinline void CPU_INT( u32 n, s32 ecycle)
{
cpuRegs.interrupt|= 1 << n;
cpuRegs.sCycle[n] = cpuRegs.cycle;
cpuRegs.eCycle[n] = ecycle;
// Interrupt is happening soon: make sure both EE and IOP are aware.
if( ecycle <= 28 && psxCycleEE > 0 )
{
// If running in the IOP, force it to break immediately into the EE.
// the EE's branch test is due to run.
psxBreak += psxCycleEE; // record the number of cycles the IOP didn't run.
psxCycleEE = 0;
}
cpuSetNextBranchDelta( cpuRegs.eCycle[n] );
}
} // end namespace R5900

122
pcsx2/R5900.h
View File

@ -19,16 +19,21 @@
#ifndef __R5900_H__
#define __R5900_H__
#include <stdio.h>
extern bool g_EEFreezeRegs;
namespace R5900
{
// EE Bios function name tables.
extern const char* const bios[256];
struct R5900cpu {
void (*Init)(); // throws exceptions on failure.
void (*Reset)();
void (*Step)();
void (*Execute)(); /* executes up to a break */
void (*ExecuteBlock)(); /* executes up to a jump */
void (*ExecuteVU0Block)(); /* executes up to a jump */
void (*ExecuteVU1Block)(); /* executes up to a jump */
void (*ExecuteBlock)();
void (*ExecuteVU0Block)();
void (*ExecuteVU1Block)();
void (*EnableVU0micro)(int enable);
void (*EnableVU1micro)(int enable);
void (*Clear)(u32 Addr, u32 Size);
@ -37,6 +42,9 @@ struct R5900cpu {
void (*Shutdown)();
};
extern s32 EEsCycle;
extern u32 EEoCycle;
extern R5900cpu *Cpu;
extern R5900cpu intCpu;
extern R5900cpu recCpu;
@ -77,22 +85,22 @@ union CP0regs {
BadVAddr, Count, EntryHi, Compare;
union {
struct {
int IE:1;
int EXL:1;
int ERL:1;
int KSU:2;
int unused0:3;
int IM:8;
int EIE:1;
int _EDI:1;
int CH:1;
int unused1:3;
int BEV:1;
int DEV:1;
int unused2:2;
int FR:1;
int unused3:1;
int CU:4;
u32 IE:1;
u32 EXL:1;
u32 ERL:1;
u32 KSU:2;
u32 unused0:3;
u32 IM:8;
u32 EIE:1;
u32 _EDI:1;
u32 CH:1;
u32 unused1:3;
u32 BEV:1;
u32 DEV:1;
u32 unused2:2;
u32 FR:1;
u32 unused3:1;
u32 CU:4;
} b;
u32 val;
} Status;
@ -125,13 +133,8 @@ struct cpuRegisters {
u32 tempcycles;
};
extern s32 EEsCycle;
extern u32 EEoCycle;
extern bool eeEventTestIsActive;
extern PCSX2_ALIGNED16_DECL(cpuRegisters cpuRegs);
// used for optimization
typedef union {
union GPR_reg64 {
u64 UD[1]; //64 bits
s64 SD[1];
u32 UL[2];
@ -140,7 +143,7 @@ typedef union {
s16 SS[4];
u8 UC[8];
s8 SC[8];
} GPR_reg64;
};
#define GPR_IS_CONST1(reg) ((reg)<32 && (g_cpuHasConstReg&(1<<(reg))))
#define GPR_IS_CONST2(reg1, reg2) ((g_cpuHasConstReg&(1<<(reg1)))&&(g_cpuHasConstReg&(1<<(reg2))))
@ -155,9 +158,6 @@ typedef union {
if( (reg) < 32 ) g_cpuHasConstReg &= ~(1<<(reg)); \
}
extern PCSX2_ALIGNED16_DECL(GPR_reg64 g_cpuConstRegs[32]);
extern u32 g_cpuHasConstReg, g_cpuFlushedConstReg;
union FPRreg {
float f;
u32 UL;
@ -169,8 +169,6 @@ struct fpuRegisters {
FPRreg ACC; // 32 bit accumulator
};
extern PCSX2_ALIGNED16_DECL(fpuRegisters fpuRegs);
struct tlbs
{
u32 PageMask,EntryHi;
@ -186,8 +184,6 @@ struct tlbs
#endif
};
extern PCSX2_ALIGNED16_DECL(tlbs tlb[48]);
#ifndef _PC_
#define _i64(x) (s64)x
@ -229,29 +225,47 @@ extern PCSX2_ALIGNED16_DECL(tlbs tlb[48]);
bool cpuInit();
void cpuReset(); // can throw Exception::FileNotFound.
void cpuShutdown();
void cpuExecuteBios();
void cpuException(u32 code, u32 bd);
void cpuTlbMissR(u32 addr, u32 bd);
void cpuTlbMissW(u32 addr, u32 bd);
void IntcpuBranchTest();
void cpuBranchTest();
void cpuTestHwInts();
extern void cpuTestINTCInts();
extern void cpuTestDMACInts();
extern void cpuTestTIMRInts();
void cpuExecuteBios();
u32 VirtualToPhysicalR(u32 addr);
u32 VirtualToPhysicalW(u32 addr);
//u32 VirtualToPhysicalR(u32 addr);
//u32 VirtualToPhysicalW(u32 addr);
void intDoBranch(u32 target);
void intSetBranch();
void intExecuteVU0Block();
void intExecuteVU1Block();
namespace Interpreter
{
void intDoBranch(u32 target);
void intSetBranch();
void intExecuteVU0Block();
void intExecuteVU1Block();
}
void JumpCheckSym(u32 addr, u32 pc);
void JumpCheckSymRet(u32 addr);
extern bool g_EEFreezeRegs;
extern int cpuSetNextBranch( u32 startCycle, s32 delta );
extern int cpuSetNextBranchDelta( s32 delta );
extern int cpuTestCycle( u32 startCycle, s32 delta );
extern void cpuSetBranch();
extern PCSX2_ALIGNED16_DECL(fpuRegisters fpuRegs);
extern PCSX2_ALIGNED16_DECL(tlbs tlb[48]);
extern PCSX2_ALIGNED16_DECL(cpuRegisters cpuRegs);
extern PCSX2_ALIGNED16_DECL(GPR_reg64 g_cpuConstRegs[32]);
extern u32 g_nextBranchCycle;
extern u32 g_cpuHasConstReg, g_cpuFlushedConstReg;
extern bool EventTestIsActive;
extern u32 s_iLastCOP0Cycle;
extern u32 s_iLastPERFCycle[2];
//exception code
#define EXC_CODE(x) ((x)<<2)
@ -278,28 +292,6 @@ extern bool g_EEFreezeRegs;
#define EXC_TLB_STORE 1
#define EXC_TLB_LOAD 0
//#define EE_PROFILING //EE Profiling enable
#ifdef EE_PROFILING //EE Profiling code
extern u64 profile_starttick;
extern u64 profile_totalticks;
#define START_EE_PROFILE() \
profile_starttick = GetCPUTick();
#define END_EE_PROFILE() \
profile_totalticks += GetCPUTick()-profile_starttick;
#define CLEAR_EE_PROFILE() \
profile_totalticks = 0;
#else
#define START_EE_PROFILE()
#define END_EE_PROFILE()
#define CLEAR_EE_PROFILE()
#endif
} // End Namespace R5900
#endif /* __R5900_H__ */

2
pcsx2/RDebug/deci2_dbgp.cpp
View File

@ -26,6 +26,8 @@
#include "Threading.h"
using namespace Threading;
using namespace R5900;
struct DECI2_DBGP_HEADER{
DECI2_HEADER h; //+00
u16 id; //+08

4
pcsx2/SPR.cpp
View File

@ -22,6 +22,8 @@
#include "SPR.h"
#include "iR5900.h"
using R5900::Cpu;
#define spr0 ((DMACh*)&PS2MEM_HW[0xD000])
#define spr1 ((DMACh*)&PS2MEM_HW[0xD400])
@ -223,7 +225,6 @@ void SPRFROMinterrupt()
{
spr0->chcr&= ~0x100;
hwDmacIrq(8);
cpuRegs.interrupt &= ~(1 << 8);
}
extern void mfifoGIFtransfer(int);
@ -394,6 +395,5 @@ void SPRTOinterrupt()
{
spr1->chcr &= ~0x100;
hwDmacIrq(9);
cpuRegs.interrupt &= ~(1 << 9);
}

6
pcsx2/SaveState.cpp
View File

@ -33,8 +33,8 @@
#include "Paths.h"
extern u32 s_iLastCOP0Cycle;
extern u32 s_iLastPERFCycle[2];
using namespace R5900;
extern int g_psxWriteOk;
// STATES
@ -83,7 +83,7 @@ string SaveState::GetFilename( int slot )
SaveState::SaveState( const char* msg, const string& destination ) : m_version( g_SaveVersion )
{
Console::WriteLn( "%s %S", params msg, &destination );
Console::WriteLn( "%s %hs", params msg, &destination );
}
s32 CALLBACK gsSafeFreeze( int mode, freezeData *data )

5
pcsx2/Sif.cpp
View File

@ -271,7 +271,7 @@ __forceinline void SIF0Dma()
// }
// }
Cpu->Clear(sif0dma->madr, readSize*4);
R5900::Cpu->Clear(sif0dma->madr, readSize*4);
cycles += readSize * BIAS; // fixme : BIAS is factored in below
//cycles += readSize;
@ -524,14 +524,11 @@ __forceinline void sif1Interrupt() {
__forceinline void EEsif0Interrupt() {
sif0dma->chcr &= ~0x100;
hwDmacIrq(DMAC_SIF0);
cpuRegs.interrupt &= ~(1 << 5);
}
__forceinline void EEsif1Interrupt() {
hwDmacIrq(DMAC_SIF1);
sif1dma->chcr &= ~0x100;
cpuRegs.interrupt &= ~(1 << 6);
}
__forceinline void dmaSIF0() {

2
pcsx2/SourceLog.cpp
View File

@ -30,6 +30,8 @@
#include "Common.h"
#include "PsxCommon.h"
using namespace R5900;
FILE *emuLog;
#ifdef PCSX2_DEVBUILD

2
pcsx2/Stats.cpp
View File

@ -58,6 +58,8 @@ void statsClose() {
fclose(f);
}
using R5900::cpuRegs;
void statsVSync() {
static u64 accum = 0, accumvu1 = 0;
static u32 frame = 0;

8
pcsx2/StringUtils.h
View File

@ -47,11 +47,17 @@ std::string to_string(const T& value)
// allow us to use the va_list feature on references.
struct VARG_PARAM
{
// just some value to make the struct length 32bits instead of 8 bits, so that the
// compiler generates somewhat more efficient code.
uint someval;
};
extern VARG_PARAM va_arg_dummy;
extern const VARG_PARAM va_arg_dummy;
extern void ssprintf(std::string& dest, const std::string& fmt, VARG_PARAM dummy, ...);
extern void ssappendf( std::string& dest, const std::string& format, VARG_PARAM dummy, ...);
extern void vssprintf(std::string& dest, const std::string& format, va_list args);
extern void vssappendf(std::string& dest, const std::string& format, va_list args);
extern std::string fmt_string( const std::string& fmt, VARG_PARAM dummy, ... );
#endif

3
pcsx2/System.cpp
View File

@ -82,6 +82,7 @@ static void trim( string& line )
line.erase( 0, beginning_of_string );
}
using R5900::cpuRegs;
// This function should be called once during program execution.
void SysDetect()
@ -147,4 +148,4 @@ void SysDetect()
}
Console::ClearColor();
}
}

60
pcsx2/VU0.cpp
View File

@ -49,6 +49,8 @@
#include "VUflags.h"
using namespace R5900;
PCSX2_ALIGNED16(VURegs VU0);
void COP2_BC2() { Int_COP2BC2PrintTable[_Rt_]();}
@ -63,7 +65,9 @@ void COP2_Unknown()
CPU_LOG("Unknown COP2 opcode called\n");
}
namespace EE{ namespace Interpreter{ namespace OpcodeImpl
namespace R5900 {
namespace Interpreter{
namespace OpcodeImpl
{
void LQC2() {
u32 addr = cpuRegs.GPR.r[_Rs_].UL[0] + (s16)cpuRegs.code;
@ -339,50 +343,6 @@ void VFCSET() { VU0.code = cpuRegs.code; _vuFCSET(&VU0); }
void VFCGET() { VU0.code = cpuRegs.code; _vuFCGET(&VU0); }
void VXITOP() { VU0.code = cpuRegs.code; _vuXITOP(&VU0); }
#define CP2COND (((VU0.VI[REG_VPU_STAT].US[0] >> 8) & 1))
void BC2F()
{
if (CP2COND == 0)
{
SysPrintf("VU0 Macro Branch \n");
intDoBranch(_BranchTarget_);
}
}
void BC2T()
{
if (CP2COND == 1)
{
SysPrintf("VU0 Macro Branch \n");
intDoBranch(_BranchTarget_);
}
}
void BC2FL()
{
if (CP2COND == 0)
{
SysPrintf("VU0 Macro Branch \n");
intDoBranch(_BranchTarget_);
}
else
{
cpuRegs.pc+= 4;
}
}
void BC2TL()
{
if (CP2COND == 1)
{
SysPrintf("VU0 Macro Branch \n");
intDoBranch(_BranchTarget_);
}
else
{
cpuRegs.pc+= 4;
}
}
void vu0Finish()
{
if( (VU0.VI[REG_VPU_STAT].UL & 0x1) ) {
@ -403,13 +363,3 @@ void vu0Finish()
}
}
}
void VCALLMS() {
vu0Finish();
vu0ExecMicro(((cpuRegs.code >> 6) & 0x7FFF) * 8);
}
void VCALLMSR() {
vu0Finish();
vu0ExecMicro(VU0.VI[REG_CMSAR0].US[0] * 8);
}

46
pcsx2/VU0.h
View File

@ -1,46 +0,0 @@
/* Pcsx2 - Pc Ps2 Emulator
* Copyright (C) 2002-2008 Pcsx2 Team
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
*/
#ifndef __VU0_H__
#define __VU0_H__
#include "VU.h"
#define Lcode cpuRegs.code
int vu0Init();
void vu0Reset();
void vu0ResetRegs();
void vu0Shutdown();
void recResetVU0( void );
void vu0Finish();
extern char *recMemVU0; /* VU0 blocks */
extern char *recVU0; /* VU1 mem */
extern char *recVU0mac;
extern char *recVU0status;
extern char *recVU0clip;
extern char *recVU0Q;
extern char *recVU0cycles;
extern char* recVU0XMMRegs;
extern char *recPtrVU0;
extern u32 vu0recpcold;
#endif /* __VU0_H__ */

13
pcsx2/VU0micro.cpp
View File

@ -61,6 +61,8 @@ void iDumpVU0Registers()
#endif
}
using namespace R5900;
int vu0Init()
{
#ifdef PCSX2_VIRTUAL_MEM
@ -117,7 +119,7 @@ int vu0Init()
VU0.vuExec = vu0Exec;
VU0.vifRegs = vif0Regs;
if( CHECK_VU0REC ) SuperVUInit(0);
if( CHECK_VU0REC ) Dynarec::SuperVUInit(0);
vu0Reset();
@ -126,7 +128,7 @@ int vu0Init()
void vu0Shutdown()
{
if( CHECK_VU0REC ) SuperVUDestroy(0);
if( CHECK_VU0REC ) Dynarec::SuperVUDestroy(0);
#ifdef PCSX2_VIRTUAL_MEM
if( !SysMapUserPhysicalPages(VU0.Mem, 16, NULL, 0) )
@ -163,12 +165,7 @@ void vu0Reset()
memset(VU0.Mem, 0, 4*1024);
memset(VU0.Micro, 0, 4*1024);
recResetVU0();
}
void recResetVU0( void )
{
if( CHECK_VU0REC ) SuperVUReset(0);
if( CHECK_VU0REC ) Dynarec::recResetVU0();
}
void SaveState::vu0Freeze() {

10
pcsx2/VU1micro.cpp
View File

@ -90,7 +90,7 @@ int vu1Init()
VU1.vuExec = vu1Exec;
VU1.vifRegs = vif1Regs;
if( CHECK_VU1REC ) recVU1Init();
if( CHECK_VU1REC ) Dynarec::recVU1Init();
vu1Reset();
@ -98,7 +98,7 @@ int vu1Init()
}
void vu1Shutdown() {
if( CHECK_VU1REC ) recVU1Shutdown();
if( CHECK_VU1REC ) Dynarec::recVU1Shutdown();
}
void vu1ResetRegs()
@ -120,7 +120,7 @@ void vu1Reset() {
memset(VU1.Mem, 0, 16*1024);
memset(VU1.Micro, 0, 16*1024);
recResetVU1();
Dynarec::recResetVU1();
}
void SaveState::vu1Freeze() {
@ -140,7 +140,7 @@ void vu1ExecMicro(u32 addr)
SysPrintf("Previous Microprogram still running on VU1\n");
do {
Cpu->ExecuteVU1Block();
R5900::Cpu->ExecuteVU1Block();
} while(VU0.VI[REG_VPU_STAT].UL & 0x100);
}
VUM_LOG("vu1ExecMicro %x\n", addr);
@ -154,7 +154,7 @@ void vu1ExecMicro(u32 addr)
//do {
FreezeXMMRegs(1);
Cpu->ExecuteVU1Block();
R5900::Cpu->ExecuteVU1Block();
FreezeXMMRegs(0);
//} while(VU0.VI[REG_VPU_STAT].UL & 0x100);
// rec can call vu1ExecMicro

1
pcsx2/VUmicro.h
View File

@ -72,7 +72,6 @@ void recResetVU0( void );
int vu1Init();
void vu1Reset();
void vu1ResetRegs();
void recResetVU1( void );
void vu1Shutdown();
void vu1ExecMicro(u32 addr);
void vu1Exec(VURegs* VU);

4
pcsx2/Vif.cpp
View File

@ -572,7 +572,6 @@ void mfifoVIF1transfer(int qwc) {
void vifMFIFOInterrupt()
{
if(vif1.irq && vif1.tag.size == 0) {
vif1Regs->stat|= VIF1_STAT_INT;
hwIntcIrq(5);
@ -581,7 +580,6 @@ void vifMFIFOInterrupt()
{
vif1Regs->stat&= ~0x1F000000; // FQC=0
vif1ch->chcr &= ~0x100;
cpuRegs.interrupt &= ~(1 << 10);
return;
}
}
@ -590,7 +588,6 @@ void vifMFIFOInterrupt()
if(vifqwc <= 0){
//SysPrintf("Empty\n");
hwDmacIrq(14);
cpuRegs.interrupt &= ~(1 << 10);
return;
}
mfifoVIF1transfer(0);
@ -606,5 +603,4 @@ void vifMFIFOInterrupt()
vif1Regs->stat&= ~0x1F000000; // FQC=0
// }
cpuRegs.interrupt &= ~(1 << 10);
}

5
pcsx2/VifDma.cpp
View File

@ -31,6 +31,8 @@
#endif
using namespace std; // for min / max
using R5900::Cpu; // for detecting VU1 dummy / frameskip.
using R5900::cpuRegs;
//#define VIFUNPACKDEBUG //enable unpack debugging output
@ -205,9 +207,7 @@ __forceinline void vif0FLUSH() {
int _cycles;
_cycles = VU0.cycle;
//FreezeXMMRegs(1);
vu0Finish();
//FreezeXMMRegs(0);
g_vifCycles+= (VU0.cycle - _cycles)*BIAS;
}
@ -2108,7 +2108,6 @@ __forceinline void vif1Interrupt() {
vif1Regs->stat&= ~0x1F000000; // FQC=0
// One game doesnt like vif stalling at end, cant remember what. Spiderman isnt keen on it tho
vif1ch->chcr &= ~0x100;
cpuRegs.interrupt &= ~(1 << 1);
return;
}
//return 0;

97
pcsx2/vssprintf.cpp
View File

@ -503,12 +503,12 @@ static void flt( std::string& dest, double num, int size, int precision, char fm
#endif
///////////////////////////////////////////////////////////////////////////
// This is a "mostly" direct replacement for vsprintf, that is more secure and easier
// to use than vsnprintf or vsprintf_s. See the docs for ssprintf for usage notes.
void vssprintf(std::string& dest, const std::string& format, va_list args)
void vssappendf(std::string& dest, const std::string& format, va_list args)
{
int len;
int i, base;
int base;
int flags; // Flags to number()
@ -516,7 +516,9 @@ void vssprintf(std::string& dest, const std::string& format, va_list args)
int precision; // Min. # of digits for integers; max number of chars for from string
int qualifier; // 'h', 'l', or 'L' for integer fields
dest.clear();
// Optimization: Memory is cheap. Allocating it on the fly is not. Allocate more room
// than we'll likely need right upfront!
dest.reserve( format.length() * 2 );
for( const char* fmt = format.c_str(); *fmt; fmt++ )
{
@ -571,7 +573,7 @@ repeat:
// Get the conversion qualifier
qualifier = -1;
if (*fmt == 'h' || *fmt == 'l' || *fmt == 'L')
if (*fmt == 'h' || *fmt == 'l' || *fmt == 'L' )
{
qualifier = *fmt;
fmt++;
@ -590,24 +592,47 @@ repeat:
case 's':
{
const char* s = va_arg(args, char *);
if (!s) s = "<NULL>";
len = strnlen(s, precision);
if (!(flags & LEFT)) while (len < field_width--) dest += ' ';
for (i = 0; i < len; ++i) dest += *s++;
while (len < field_width--) dest += ' ';
}
continue;
// let's add support for std::string as a formatted parameter! (air)
if( qualifier == 'h' )
{
static const string nullstring( "<NULL>" );
// let's add support for std::string as a formatted parameter! (air)
case 'S':
{
std::string* ss = va_arg(args, std::string*);
const char* s = ( ss!=NULL ) ? ss->c_str() : "<NULL>";
len = strnlen(s, precision);
if (!(flags & LEFT)) while (len < field_width--) dest += ' ';
for (i = 0; i < len; ++i) dest += *s++;
while (len < field_width--) dest += ' ';
const std::string* ss = va_arg(args, std::string*);
if( ss == NULL ) ss = &nullstring;
int len = ss->length();
if( precision < 0 )
{
// no precision override so just copy the whole string.
if (!(flags & LEFT)) while (len < field_width--) dest += ' ';
dest += *ss;
}
else
{
if( len > precision ) len = precision;
if (!(flags & LEFT)) while (len < field_width--) dest += ' ';
dest.append( ss->begin(), ss->begin()+len );
}
while (len < field_width--) dest += ' ';
}
else
{
const char* s = va_arg(args, char *);
if (!s) s = "<NULL>";
int len = strlen(s);
if( precision < 0 )
{
if (!(flags & LEFT)) while (len < field_width--) dest += ' ';
dest += s;
}
else
{
if( len > precision ) len = precision;
if (!(flags & LEFT)) while (len < field_width--) dest += ' ';
dest.append( s, s+len );
}
while (len < field_width--) dest += ' ';
}
}
continue;
@ -689,6 +714,7 @@ repeat:
if (qualifier == 'L')
{
// 64-bit integer support! (air)
number(dest, va_arg(args, s64), base, field_width, precision, flags);
}
else
@ -704,6 +730,22 @@ repeat:
}
}
void vssprintf( std::string& dest, const std::string& format, va_list args )
{
dest.clear();
vssappendf( dest, format, args );
}
void ssappendf( std::string& dest, const std::string& format, VARG_PARAM dummy, ...)
{
dummy_assert();
va_list args;
va_start(args, dummy);
vssappendf( dest, format, args );
va_end(args);
}
// This is a "mostly" direct replacement for sprintf, based on std::string.
// The most notable difference in use is the requirement of a "params" keyword delimiting
// the format string from the parameters used to fill the string's tokens. It looks
@ -712,10 +754,12 @@ repeat:
// ssprintf( dest, "Yo Joe, %d. In the Hizzou %s.", params intval, strval );
//
// In addition to all standard printf formatting tokens, ssprintf also supports a new token
// for std::string parameters as %S (passed by reference/pointer). Note that these are
// passed by pointer so you *must* use the & sign most of the time. Example:
// for std::string parameters as %hs (passed by reference/pointer). I opted for %hs (using 'h'
// as a qualifier) over %S because under MSVC %S acts as a char/widechar conversion. Note
// that these are passed by pointer so you *must* use the & operator most of the time.
// Example:
//
// ssprintf( dest, "Yo Joe, %S.", params &strval );
// ssprintf( dest, "Yo Joe, %hs.", params &strval );
//
// This can be a cavet of sorts since forgetting to use the & will always compile but
// will cause undefined behavior and odd crashes (much like how the same thing happens
@ -753,4 +797,5 @@ std::string fmt_string( const std::string& fmt, VARG_PARAM dummy, ... )
va_end( args );
return retval;
}
}

6
pcsx2/vtlb.cpp
View File

@ -21,6 +21,8 @@
#include "vtlb.h"
#include "x86/ix86/ix86.h"
using namespace R5900;
#ifdef PCSX2_DEVBUILD
#define verify(x) {if (!(x)) { (*(u8*)0)=3; }}
#else
@ -480,7 +482,7 @@ void vtlb_Term()
}
namespace EE { namespace Dynarec
namespace Dynarec
{
//ecx = addr
@ -695,6 +697,6 @@ void vtlb_DynGenWrite(u32 sz,int freereg)
x86SetJ8(cont);
}
} }
}
#endif // PCSX2_VIRTUAL_MEM

4
pcsx2/vtlb.h
View File

@ -59,12 +59,12 @@ void __fastcall vtlb_memWrite32(u32 mem, u32 value);
void __fastcall vtlb_memWrite64(u32 mem, const u64* value);
void __fastcall vtlb_memWrite128(u32 mem, const u64* value);
namespace EE { namespace Dynarec {
namespace Dynarec {
void vtlb_DynGenWrite(u32 sz,int freereg);
void vtlb_DynGenRead(u32 sz,int freereg);
} }
}
#endif

2
pcsx2/windows/ConfigDlg.cpp
View File

@ -69,7 +69,7 @@ struct ComboInitializer
string tmpStr;
Path::Combine( tmpStr, Config.PluginsDir, FindData.cFileName );
Lib = LoadLibrary(tmpStr.c_str());
if (Lib == NULL) { Console::Error( "%S: %s", params &tmpStr, SysLibError()); return false; }
if (Lib == NULL) { Console::Error( "%hs: %s", params &tmpStr, SysLibError()); return false; }
PS2E_GetLibType = (_PS2EgetLibType) GetProcAddress((HMODULE)Lib,"PS2EgetLibType");
PS2E_GetLibName = (_PS2EgetLibName) GetProcAddress((HMODULE)Lib,"PS2EgetLibName");

2
pcsx2/windows/CpuDlg.cpp
View File

@ -159,7 +159,7 @@ BOOL CALLBACK CpuDlgProc(HWND hW, UINT uMsg, WPARAM wParam, LPARAM lParam)
Config.Options = newopts;
}
else
UpdateVSyncRate();
R5900::UpdateVSyncRate();
SaveConfig();

1
pcsx2/windows/DebugMemory.cpp
View File

@ -22,6 +22,7 @@
#include "Common.h"
#include "resource.h"
using namespace R5900;
unsigned long memory_addr;
BOOL mem_inupdate = FALSE;

13
pcsx2/windows/Debugger.cpp
View File

@ -27,12 +27,13 @@
#include "PsxMem.h"
#include "R3000A.h"
using namespace R5900;
#ifdef _MSC_VER
#pragma warning(disable:4996) //ignore the stricmp deprecated warning
#endif
extern void (*IOP_DEBUG_BSC[64])(char *buf);
extern void UpdateR5900op();
void RefreshIOPDebugger(void);
extern int ISR3000A;//for disasm
HWND hWnd_debugdisasm, hWnd_debugscroll,hWnd_IOP_debugdisasm, hWnd_IOP_debugscroll;
@ -173,7 +174,7 @@ BOOL APIENTRY DumpProc(HWND hDlg, UINT message, WPARAM wParam, LPARAM lParam)
sprintf(buf, "%08X %08X: %s", temp, cpuRegs.code, tmp);
output.append( buf );
EE::OpcodeTables::Standard[_Opcode_].decode( output );
R5900::OpcodeTables::tbl_Standard[_Opcode_].disasm( output );
fprintf(fp, "%s\n", buf);
@ -580,7 +581,8 @@ BOOL APIENTRY DebuggerProc(HWND hDlg, UINT message, WPARAM wParam, LPARAM lParam
return TRUE;
case IDC_CPUOP:
UpdateR5900op();
// This updated a global opcode counter.
//UpdateR5900op();
return TRUE;
case IDC_DEBUG_BP_EXEC:
@ -626,9 +628,6 @@ BOOL APIENTRY DebuggerProc(HWND hDlg, UINT message, WPARAM wParam, LPARAM lParam
return FALSE;
}
/* this lives in interpreter.c */
extern const char* bios[];
void RefreshDebugger(void)
{
unsigned long t;
@ -651,7 +650,7 @@ void RefreshDebugger(void)
if (0x0c == *mem && 0x24030000 == (*(mem-1) & 0xFFFFFF00)){
/* it's a syscall preceeded by a li v1,$data instruction. */
u8 bios_call = *(mem-1) & 0xFF;
sprintf(syscall_str, "%08X:\tsyscall\t%s", t, bios[bios_call]);
sprintf(syscall_str, "%08X:\tsyscall\t%s", t, R5900::bios[bios_call]);
} else {
std::string str;
disR5900Fasm(str, *mem, t);

4
pcsx2/windows/Debugreg.cpp
View File

@ -28,10 +28,14 @@
#include "R3000a.h"
#include "VUmicro.h"
using namespace R5900;
HINSTANCE m_hInst;
HWND m_hWnd;
char text1[256];
// Wow! This module is a lot of copy-paste!
// Between this and DisAsm modules, *someone* needs a new Ctrl-V combo on their keyboard. (air)
/*R3000a registers handle */
static HWND IOPGPR0Handle=NULL;

2
pcsx2/windows/RDebugger.cpp
View File

@ -26,6 +26,8 @@
#include "PsxCommon.h"
#include "../rdebug/deci2.h"
using namespace R5900;
u32 port=8510;
SOCKET serversocket, remote;
char message[1024]; //message to add to listbox

107
pcsx2/windows/VCprojects/pcsx2_2008.vcproj
View File

@ -1448,6 +1448,10 @@
/>
</FileConfiguration>
</File>
<File
RelativePath="..\..\x86\ix86\ix86_tools.cpp"
>
</File>
</Filter>
<Filter
Name="zlib"
@ -2300,6 +2304,10 @@
RelativePath="..\..\COP0.cpp"
>
</File>
<File
RelativePath="..\..\COP2.cpp"
>
</File>
<File
RelativePath="..\..\Counters.cpp"
>
@ -2317,7 +2325,6 @@
<Tool
Name="VCCLCompilerTool"
RuntimeLibrary="0"
AssemblerOutput="4"
/>
</FileConfiguration>
<FileConfiguration
@ -2624,36 +2631,8 @@
RelativePath="..\..\x86\ix86-32\iR5900Shift.cpp"
>
</File>
</Filter>
</Filter>
<Filter
Name="Hw"
>
<File
RelativePath="..\..\FiFo.cpp"
>
</File>
<File
RelativePath="..\..\Hw.cpp"
>
</File>
<File
RelativePath="..\..\Hw.h"
>
</File>
<File
RelativePath="..\..\SPR.cpp"
>
</File>
<File
RelativePath="..\..\SPR.h"
>
</File>
<Filter
Name="Dynarec"
>
<File
RelativePath="..\..\x86\iHw.cpp"
RelativePath="..\..\x86\ix86-32\iR5900Templates.cpp"
>
</File>
</Filter>
@ -2710,14 +2689,6 @@
RelativePath="..\..\PsxDma.h"
>
</File>
<File
RelativePath="..\..\PsxHw.cpp"
>
</File>
<File
RelativePath="..\..\PsxHw.h"
>
</File>
<File
RelativePath="..\..\PsxInterpreter.cpp"
>
@ -2757,10 +2728,6 @@
<Filter
Name="Dynarec"
>
<File
RelativePath="..\..\x86\iPsxHw.cpp"
>
</File>
<File
RelativePath="..\..\x86\iPsxMem.cpp"
>
@ -3078,10 +3045,6 @@
RelativePath="..\..\VU0.cpp"
>
</File>
<File
RelativePath="..\..\VU0.h"
>
</File>
<File
RelativePath="..\..\VU0micro.cpp"
>
@ -3178,14 +3141,6 @@
<Filter
Name="Debug"
>
<File
RelativePath="..\..\DebugTools\cpuopsDebug.cpp"
>
</File>
<File
RelativePath="..\..\DebugTools\cpuopsDebug.h"
>
</File>
<File
RelativePath="..\..\DebugTools\Debug.h"
>
@ -3227,6 +3182,50 @@
>
</File>
</Filter>
<Filter
Name="Hardware"
>
<File
RelativePath="..\..\FiFo.cpp"
>
</File>
<File
RelativePath="..\..\Hw.cpp"
>
</File>
<File
RelativePath="..\..\Hw.h"
>
</File>
<File
RelativePath="..\..\PsxHw.cpp"
>
</File>
<File
RelativePath="..\..\PsxHw.h"
>
</File>
<File
RelativePath="..\..\SPR.cpp"
>
</File>
<File
RelativePath="..\..\SPR.h"
>
</File>
<Filter
Name="Dynarec"
>
<File
RelativePath="..\..\x86\iHw.cpp"
>
</File>
<File
RelativePath="..\..\x86\iPsxHw.cpp"
>
</File>
</Filter>
</Filter>
</Filter>
<Filter
Name="ISO"

4
pcsx2/windows/WinMain.cpp
View File

@ -730,8 +730,8 @@ LRESULT WINAPI MainWndProc(HWND hWnd, UINT msg, WPARAM wParam, LPARAM lParam)
remoteDebugBios=DialogBox(gApp.hInstance, MAKEINTRESOURCE(IDD_RDEBUGPARAMS), NULL, (DLGPROC)RemoteDebuggerParamsProc);
if (remoteDebugBios)
{
cpuReset();
cpuExecuteBios();
R5900::cpuReset();
R5900::cpuExecuteBios();
DialogBox(gApp.hInstance, MAKEINTRESOURCE(IDD_RDEBUG), NULL, (DLGPROC)RemoteDebuggerProc);
CreateMainWindow(SW_SHOWNORMAL);

2
pcsx2/windows/WinSysExec.cpp
View File

@ -30,7 +30,7 @@
#include "Common.h"
#include "PsxCommon.h"
using std::string;
using namespace R5900;
int UseGui = 1;
int nDisableSC = 0; // screensaver

2
pcsx2/windows/WinVM.cpp
View File

@ -39,7 +39,7 @@ LRESULT WINAPI UserNameProc(HWND hDlg, UINT uMsg, WPARAM wParam, LPARAM lParam)
{
wchar_t str[255];
GetWindowTextW(GetDlgItem(hDlg, IDC_USER_NAME), str, 255);
swprintf(s_szUserName, 255, L"%S", &str);
swprintf(s_szUserName, 255, L"%hs", &str);
EndDialog(hDlg, TRUE );
return TRUE;
}

8
pcsx2/windows/ini.cpp
View File

@ -82,7 +82,7 @@ public:
{
SetCurrentSection( "Misc" );
Entry( "Patching", Conf.Patch, true );
Entry( "Patching", Conf.Patch, false );
Entry( "GameFixes", Conf.GameFixes);
#ifdef PCSX2_DEVBUILD
Entry( "DevLogFlags", varLog );
@ -156,7 +156,7 @@ public:
);
if( retval >= m_workspace.GetLength() - 2 )
Console::Notice( "Loadini Warning > Possible truncated value on key '%S'", params &var );
Console::Notice( "Loadini Warning > Possible truncated value on key '%hs'", params &var );
value = m_workspace.GetPtr();
}
@ -167,7 +167,7 @@ public:
);
if( retval >= sizeof(value) - 2 )
Console::Notice( "Loadini Warning > Possible truncated value on key '%S'", params &var );
Console::Notice( "Loadini Warning > Possible truncated value on key '%hs'", params &var );
}
void Entry( const string& var, int& value, const int defvalue=0 )
@ -201,7 +201,7 @@ public:
if( enumArray[i] == NULL )
{
Console::Notice( "Loadini Warning > Unrecognized value '%S' on key '%S'\n\tUsing the default setting of '%s'.",
Console::Notice( "Loadini Warning > Unrecognized value '%hs' on key '%hs'\n\tUsing the default setting of '%s'.",
params &retval, &var, enumArray[defvalue] );
value = defvalue;
}

2
pcsx2/x86/fast_routines.cpp
View File

@ -86,6 +86,8 @@ void checkregs()
if( g_EEFreezeRegs ) assert( g_globalMMXSaved );
}
#endif
__declspec(align(16)) u8 _xmm_backup[16*2];
//this one checks for alligments too ...
__declspec(naked) void __fastcall memcpy_raz_u(void *dest, const void *src, size_t bytes)

17
pcsx2/x86/iCOP2.cpp
View File

@ -30,12 +30,19 @@
#include "VUmicro.h"
#include "iVUmicro.h"
#ifdef _WIN32
#pragma warning(disable:4244)
#pragma warning(disable:4761)
#endif
extern void _vu0WaitMicro();
// Temporary until I can get the VUs namespaced properly.
using namespace Dynarec::R5900;
namespace Dynarec
{
#define _Ft_ _Rt_
#define _Fs_ _Rd_
#define _Fd_ _Sa_
@ -47,12 +54,11 @@
void recCop2BranchCall( void (*func)() )
{
SetFPUstate();
EE::Dynarec::recBranchCall( func );
R5900::recBranchCall( func );
_freeX86regs();
}
#define REC_COP2_FUNC( f ) \
void f(); \
void rec##f(s32 info) \
{ \
Console::Notice("Warning > cop2 "#f" called"); \
@ -73,7 +79,6 @@ void recV##f( s32 info ) { \
recVUMI_##f( &VU0, info ); \
}
extern u32 dumplog;
#define REC_COP2_VU0_Q(f) \
void recV##f( s32 info ) { \
recVUMI_##f( &VU0, info ); \
@ -93,8 +98,6 @@ void recCOP2(s32 info);
void recCOP2_SPECIAL(s32 info);
void recCOP2_BC2(s32 info);
void recCOP2_SPECIAL2(s32 info);
extern void _vu0WaitMicro();
static void recCFC2(s32 info)
{
@ -680,3 +683,5 @@ void recCOP2_SPECIAL2(s32 info)
int opc=(cpuRegs.code & 0x3) | ((cpuRegs.code >> 4) & 0x7c);
recCOP2SPECIAL2t[opc](info);
}
}

17
pcsx2/x86/iCP0.cpp
View File

@ -30,6 +30,12 @@
#include "iR5900.h"
#include "iCP0.h"
namespace Dynarec {
namespace R5900 {
namespace OpcodeImpl
{
/*********************************************************
* COP0 opcodes *
* *
@ -71,8 +77,6 @@ REC_SYS(TLBWR);
REC_SYS(TLBP);
////////////////////////////////////////////////////
extern u32 s_iLastCOP0Cycle;
extern u32 s_iLastPERFCycle[2];
void recMFC0( void )
{
@ -326,14 +330,14 @@ void recMTC0()
void recERET()
{
EE::Dynarec::recBranchCall( ERET );
recBranchCall( R5900::Interpreter::OpcodeImpl::ERET );
}
void recEI()
{
// must branch after enabling interrupts, so that anything
// pending gets triggered properly.
EE::Dynarec::recBranchCall( EI );
recBranchCall( R5900::Interpreter::OpcodeImpl::EI );
}
void recDI()
@ -347,10 +351,9 @@ void recDI()
MOV32RtoM( (uptr)&g_nextBranchCycle, ECX );
iFlushCall(0);
CALLFunc( (uptr)DI );
CALLFunc( (uptr)R5900::Interpreter::OpcodeImpl::DI );
}
/*void rec(COP0) {
}
@ -378,4 +381,6 @@ void rec(TLBWR) {
void rec(TLBP) {
}*/
}}}
#endif

33
pcsx2/x86/iCP0.h
View File

@ -24,18 +24,25 @@
* *
*********************************************************/
void recMFC0( void );
void recMTC0( void );
void recBC0F( void );
void recBC0T( void );
void recBC0FL( void );
void recBC0TL( void );
void recTLBR( void );
void recTLBWI( void );
void recTLBWR( void );
void recTLBP( void );
void recERET( void );
void recDI( void );
void recEI( void );
namespace Dynarec {
namespace R5900 {
namespace OpcodeImpl
{
void recCOP0_Unknown();
void recMFC0( void );
void recMTC0( void );
void recBC0F( void );
void recBC0T( void );
void recBC0FL( void );
void recBC0TL( void );
void recTLBR( void );
void recTLBWI( void );
void recTLBWR( void );
void recTLBP( void );
void recERET( void );
void recDI( void );
void recEI( void );
}}}
#endif

158
pcsx2/x86/iCore.cpp
View File

@ -28,6 +28,12 @@
#include "iCore.h"
#include "R3000A.h"
// Required because the iCore has tons of code shared between both the EE and IOP.. ugh.
using namespace R5900;
namespace Dynarec
{
u16 g_x86AllocCounter = 0;
u16 g_xmmAllocCounter = 0;
@ -38,7 +44,6 @@ u32 g_cpuRegHasSignExt = 0, g_cpuPrevRegHasSignExt = 0; // set if upper 32 bits
// used to make sure regs don't get changed while in recompiler
// use FreezeMMXRegs, FreezeXMMRegs
u8 g_globalXMMSaved = 0;
u32 g_recWriteback = 0;
#ifdef _DEBUG
@ -46,7 +51,6 @@ char g_globalXMMLocked = 0;
#endif
_xmmregs xmmregs[XMMREGS], s_saveXMMregs[XMMREGS];
PCSX2_ALIGNED16(u64 g_globalXMMData[2*XMMREGS]);
// X86 caching
_x86regs x86regs[X86REGS], s_saveX86regs[X86REGS];
@ -1004,84 +1008,6 @@ void _freeXMMregs()
}
}
__forceinline void FreezeXMMRegs_(int save)
{
//SysPrintf("FreezeXMMRegs_(%d); [%d]\n", save, g_globalXMMSaved);
assert( g_EEFreezeRegs );
if( save ) {
g_globalXMMSaved++;
if( g_globalXMMSaved > 1 ){
//SysPrintf("XMM Already saved\n");
return;
}
#ifdef _MSC_VER
__asm {
movaps xmmword ptr [g_globalXMMData + 0x00], xmm0
movaps xmmword ptr [g_globalXMMData + 0x10], xmm1
movaps xmmword ptr [g_globalXMMData + 0x20], xmm2
movaps xmmword ptr [g_globalXMMData + 0x30], xmm3
movaps xmmword ptr [g_globalXMMData + 0x40], xmm4
movaps xmmword ptr [g_globalXMMData + 0x50], xmm5
movaps xmmword ptr [g_globalXMMData + 0x60], xmm6
movaps xmmword ptr [g_globalXMMData + 0x70], xmm7
}
#else
__asm__(".intel_syntax\n"
"movaps [%0+0x00], %%xmm0\n"
"movaps [%0+0x10], %%xmm1\n"
"movaps [%0+0x20], %%xmm2\n"
"movaps [%0+0x30], %%xmm3\n"
"movaps [%0+0x40], %%xmm4\n"
"movaps [%0+0x50], %%xmm5\n"
"movaps [%0+0x60], %%xmm6\n"
"movaps [%0+0x70], %%xmm7\n"
".att_syntax\n" : : "r"(g_globalXMMData) );
#endif // _MSC_VER
}
else {
if( g_globalXMMSaved==0 )
{
//SysPrintf("XMM Regs not saved!\n");
return;
}
// TODO: really need to backup all regs?
g_globalXMMSaved--;
if( g_globalXMMSaved > 0 ) return;
#ifdef _MSC_VER
__asm {
movaps xmm0, xmmword ptr [g_globalXMMData + 0x00]
movaps xmm1, xmmword ptr [g_globalXMMData + 0x10]
movaps xmm2, xmmword ptr [g_globalXMMData + 0x20]
movaps xmm3, xmmword ptr [g_globalXMMData + 0x30]
movaps xmm4, xmmword ptr [g_globalXMMData + 0x40]
movaps xmm5, xmmword ptr [g_globalXMMData + 0x50]
movaps xmm6, xmmword ptr [g_globalXMMData + 0x60]
movaps xmm7, xmmword ptr [g_globalXMMData + 0x70]
}
#else
__asm__(".intel_syntax\n"
"movaps %%xmm0, [%0+0x00]\n"
"movaps %%xmm1, [%0+0x10]\n"
"movaps %%xmm2, [%0+0x20]\n"
"movaps %%xmm3, [%0+0x30]\n"
"movaps %%xmm4, [%0+0x40]\n"
"movaps %%xmm5, [%0+0x50]\n"
"movaps %%xmm6, [%0+0x60]\n"
"movaps %%xmm7, [%0+0x70]\n"
".att_syntax\n" : : "r"(g_globalXMMData) );
#endif // _MSC_VER
}
}
// PSX
void _psxMoveGPRtoR(x86IntRegType to, int fromgpr)
{
@ -1389,3 +1315,75 @@ BASEBLOCKEX** GetAllBaseBlocks(int* pnum, int cpu)
{
return s_vecBaseBlocksEx[cpu].GetAll(pnum);
}
////////////////////////////////////////////////////
//#include "R3000A.h"
//#include "PsxCounters.h"
//#include "PsxMem.h"
//extern tIPU_BP g_BP;
#if 0
extern u32 psxdump;
extern void iDumpPsxRegisters(u32 startpc, u32 temp);
extern Counter counters[6];
extern int rdram_devices; // put 8 for TOOL and 2 for PS2 and PSX
extern int rdram_sdevid;
#endif
void iDumpRegisters(u32 startpc, u32 temp)
{
// [TODO] fixme : thie code is broken and has no labels. Needs a rewrite to be useful.
#if 0
int i;
const char* pstr;// = temp ? "t" : "";
const u32 dmacs[] = {0x8000, 0x9000, 0xa000, 0xb000, 0xb400, 0xc000, 0xc400, 0xc800, 0xd000, 0xd400 };
const char* psymb;
if (temp)
pstr = "t";
else
pstr = "";
psymb = disR5900GetSym(startpc);
if( psymb != NULL )
__Log("%sreg(%s): %x %x c:%x\n", pstr, psymb, startpc, cpuRegs.interrupt, cpuRegs.cycle);
else
__Log("%sreg: %x %x c:%x\n", pstr, startpc, cpuRegs.interrupt, cpuRegs.cycle);
for(i = 1; i < 32; ++i) __Log("%s: %x_%x_%x_%x\n", disRNameGPR[i], cpuRegs.GPR.r[i].UL[3], cpuRegs.GPR.r[i].UL[2], cpuRegs.GPR.r[i].UL[1], cpuRegs.GPR.r[i].UL[0]);
//for(i = 0; i < 32; i+=4) __Log("cp%d: %x_%x_%x_%x\n", i, cpuRegs.CP0.r[i], cpuRegs.CP0.r[i+1], cpuRegs.CP0.r[i+2], cpuRegs.CP0.r[i+3]);
//for(i = 0; i < 32; ++i) __Log("%sf%d: %f %x\n", pstr, i, fpuRegs.fpr[i].f, fpuRegs.fprc[i]);
//for(i = 1; i < 32; ++i) __Log("%svf%d: %f %f %f %f, vi: %x\n", pstr, i, VU0.VF[i].F[3], VU0.VF[i].F[2], VU0.VF[i].F[1], VU0.VF[i].F[0], VU0.VI[i].UL);
for(i = 0; i < 32; ++i) __Log("%sf%d: %x %x\n", pstr, i, fpuRegs.fpr[i].UL, fpuRegs.fprc[i]);
for(i = 1; i < 32; ++i) __Log("%svf%d: %x %x %x %x, vi: %x\n", pstr, i, VU0.VF[i].UL[3], VU0.VF[i].UL[2], VU0.VF[i].UL[1], VU0.VF[i].UL[0], VU0.VI[i].UL);
__Log("%svfACC: %x %x %x %x\n", pstr, VU0.ACC.UL[3], VU0.ACC.UL[2], VU0.ACC.UL[1], VU0.ACC.UL[0]);
__Log("%sLO: %x_%x_%x_%x, HI: %x_%x_%x_%x\n", pstr, cpuRegs.LO.UL[3], cpuRegs.LO.UL[2], cpuRegs.LO.UL[1], cpuRegs.LO.UL[0],
cpuRegs.HI.UL[3], cpuRegs.HI.UL[2], cpuRegs.HI.UL[1], cpuRegs.HI.UL[0]);
__Log("%sCycle: %x %x, Count: %x\n", pstr, cpuRegs.cycle, g_nextBranchCycle, cpuRegs.CP0.n.Count);
iDumpPsxRegisters(psxRegs.pc, temp);
__Log("f410,30,40: %x %x %x, %d %d\n", psHu32(0xf410), psHu32(0xf430), psHu32(0xf440), rdram_sdevid, rdram_devices);
__Log("cyc11: %x %x; vu0: %x, vu1: %x\n", cpuRegs.sCycle[1], cpuRegs.eCycle[1], VU0.cycle, VU1.cycle);
__Log("%scounters: %x %x; psx: %x %x\n", pstr, nextsCounter, nextCounter, psxNextsCounter, psxNextCounter);
for(i = 0; i < 4; ++i) {
__Log("eetimer%d: count: %x mode: %x target: %x %x; %x %x; %x %x %x %x\n", i,
counters[i].count, counters[i].mode, counters[i].target, counters[i].hold, counters[i].rate,
counters[i].interrupt, counters[i].Cycle, counters[i].sCycle, counters[i].CycleT, counters[i].sCycleT);
}
__Log("VIF0_STAT = %x, VIF1_STAT = %x\n", psHu32(0x3800), psHu32(0x3C00));
__Log("ipu %x %x %x %x; bp: %x %x %x %x\n", psHu32(0x2000), psHu32(0x2010), psHu32(0x2020), psHu32(0x2030), g_BP.BP, g_BP.bufferhasnew, g_BP.FP, g_BP.IFC);
__Log("gif: %x %x %x\n", psHu32(0x3000), psHu32(0x3010), psHu32(0x3020));
for(i = 0; i < ARRAYSIZE(dmacs); ++i) {
DMACh* p = (DMACh*)(PS2MEM_HW+dmacs[i]);
__Log("dma%d c%x m%x q%x t%x s%x\n", i, p->chcr, p->madr, p->qwc, p->tadr, p->sadr);
}
__Log("dmac %x %x %x %x\n", psHu32(DMAC_CTRL), psHu32(DMAC_STAT), psHu32(DMAC_RBSR), psHu32(DMAC_RBOR));
__Log("intc %x %x\n", psHu32(INTC_STAT), psHu32(INTC_MASK));
__Log("sif: %x %x %x %x %x\n", psHu32(0xf200), psHu32(0xf220), psHu32(0xf230), psHu32(0xf240), psHu32(0xf260));
#endif
}
}

40
pcsx2/x86/iCore.h
View File

@ -16,16 +16,18 @@
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
*/
// NOTE: x86-64 recompiler didn't support mmx
#ifndef _PCSX2_CORE_RECOMPILER_
#define _PCSX2_CORE_RECOMPILER_
#include "ix86/ix86.h"
#include "iVUmicro.h"
// xp64 had a stack shadow memory
#define REC_INC_STACK 0
// Namespace Note : Dyanmic recompiler tools used by EE, IOP, and PS2 hardware.
// Underneath this namespace thenare Dynarec::R5900, Dynarec::R3000a, etc. for each
// of the items specific to those CPUs (those are defined in other headers).
namespace Dynarec
{
// used to keep block information
#define BLOCKTYPE_STARTPC 4 // startpc offset
#define BLOCKTYPE_DELAYSLOT 1 // if bit set, delay slot
@ -100,6 +102,9 @@ void _flushX86regs();
void _freeX86regs();
void _freeX86tempregs();
u8 _hasFreeX86reg();
void _flushCachedRegs();
void _flushConstRegs();
void _flushConstReg(int reg);
// see MEM_X defines for argX format
extern void _callPushArg(u32 arg, uptr argmem); /// X86ARG is ignored for 32bit recs
@ -107,15 +112,6 @@ extern void _callFunctionArg1(uptr fn, u32 arg1, uptr arg1mem);
extern void _callFunctionArg2(uptr fn, u32 arg1, u32 arg2, uptr arg1mem, uptr arg2mem);
extern void _callFunctionArg3(uptr fn, u32 arg1, u32 arg2, u32 arg3, uptr arg1mem, uptr arg2mem, uptr arg3mem);
// when using mmx/xmm regs, use; 0 is load
// freezes no matter the state
extern void FreezeXMMRegs_(int save);
void _flushCachedRegs();
void _flushConstRegs();
void _flushConstReg(int reg);
// return type: 0 - const, 1 - mmx, 2 - xmm
#define PROCESS_EE_MMX 0x01
#define PROCESS_EE_XMM 0x02
@ -370,6 +366,9 @@ extern u32 g_cpuRegHasSignExt, g_cpuPrevRegHasSignExt;
extern u8 g_globalXMMSaved;
extern _xmmregs xmmregs[XMMREGS], s_saveXMMregs[XMMREGS];
extern u16 g_x86AllocCounter;
extern u16 g_xmmAllocCounter;
#ifdef _DEBUG
extern char g_globalXMMLocked;
#endif
@ -403,14 +402,13 @@ void SetMMXstate();
void _recMove128MtoM(u32 to, u32 from);
/////////////////////
// MMX x86-32 only //
/////////////////////
/////////////////////////////
// MMX x86-32 only //
/////////////////////////////
#define FPU_STATE 0
#define MMX_STATE 1
extern void FreezeMMXRegs_(int save);
void SetFPUstate();
// max is 0x7f, when 0x80 is set, need to flush reg
@ -468,7 +466,6 @@ void LogicalOpMtoR(x86MMXRegType to, u32 from, int op);
// a negative shift is for sign extension
int _signExtendGPRtoMMX(x86MMXRegType to, u32 gprreg, int shift);
extern u8 g_globalMMXSaved;
extern _mmxregs mmxregs[MMXREGS], s_saveMMXregs[MMXREGS];
extern u16 x86FpuState, iCWstate;
@ -477,4 +474,13 @@ void LogicalOp32MtoR(x86IntRegType to, uptr from, int op);
void LogicalOp32ItoR(x86IntRegType to, u32 from, int op);
void LogicalOp32ItoM(uptr to, u32 from, int op);
#ifdef ARITHMETICIMM_RECOMPILE
extern void LogicalOpRtoR(x86MMXRegType to, x86MMXRegType from, int op);
extern void LogicalOpMtoR(x86MMXRegType to, u32 from, int op);
#endif
void iDumpRegisters(u32 startpc, u32 temp);
}
#endif

103
pcsx2/x86/iFPU.cpp
View File

@ -24,13 +24,50 @@
#include "iR5900.h"
#include "iFPU.h"
// Needed for gcc 4.3, due to header revisions.
// (really? that makes no sense... commented out, if they break something
// on gcc, re-add them.. if not, delete (air))
//#include "stdio.h"
//#include "stdlib.h"
//------------------------------------------------------------------
extern PCSX2_ALIGNED16_DECL(u32 g_minvals[4]);
extern PCSX2_ALIGNED16_DECL(u32 g_maxvals[4]);
//------------------------------------------------------------------
// Misc...
//------------------------------------------------------------------
//static u32 _mxcsr = 0x7F80;
//static u32 _mxcsrs;
static u32 fpucw = 0x007f;
static u32 fpucws = 0;
//------------------------------------------------------------------
namespace Dynarec {
namespace R5900
{
void SaveCW(int type) {
if (iCWstate & type) return;
if (type == 2) {
// SSE_STMXCSR((uptr)&_mxcsrs);
// SSE_LDMXCSR((uptr)&_mxcsr);
} else {
FNSTCW( (uptr)&fpucws );
FLDCW( (uptr)&fpucw );
}
iCWstate|= type;
}
void LoadCW() {
if (iCWstate == 0) return;
if (iCWstate & 2) {
//SSE_LDMXCSR((uptr)&_mxcsrs);
}
if (iCWstate & 1) {
FLDCW( (uptr)&fpucws );
}
iCWstate = 0;
}
//------------------------------------------------------------------
namespace OpcodeImpl
{
//------------------------------------------------------------------
// Helper Macros
@ -52,9 +89,6 @@
#define FPU_ADD_SUB_HACK 1 // Add/Sub opcodes produce more ps2-like results if set to 1
extern PCSX2_ALIGNED16_DECL(u32 g_minvals[4]);
extern PCSX2_ALIGNED16_DECL(u32 g_maxvals[4]);
static u32 PCSX2_ALIGNED16(s_neg[4]) = { 0x80000000, 0xffffffff, 0xffffffff, 0xffffffff };
static u32 PCSX2_ALIGNED16(s_pos[4]) = { 0x7fffffff, 0xffffffff, 0xffffffff, 0xffffffff };
@ -78,55 +112,6 @@ static u32 PCSX2_ALIGNED16(s_pos[4]) = { 0x7fffffff, 0xffffffff, 0xffffffff, 0xf
}
//------------------------------------------------------------------
//------------------------------------------------------------------
// Misc...
//------------------------------------------------------------------
//static u32 _mxcsr = 0x7F80;
//static u32 _mxcsrs;
static u32 fpucw = 0x007f;
static u32 fpucws = 0;
void recCOP1_BC1()
{
recCP1BC1[_Rt_]();
}
void SaveCW(int type) {
if (iCWstate & type) return;
if (type == 2) {
// SSE_STMXCSR((uptr)&_mxcsrs);
// SSE_LDMXCSR((uptr)&_mxcsr);
} else {
FNSTCW( (uptr)&fpucws );
FLDCW( (uptr)&fpucw );
}
iCWstate|= type;
}
void LoadCW( void ) {
if (iCWstate == 0) return;
if (iCWstate & 2) {
//SSE_LDMXCSR((uptr)&_mxcsrs);
}
if (iCWstate & 1) {
FLDCW( (uptr)&fpucws );
}
iCWstate = 0;
}
void recCOP1_S( void ) {
recCP1S[ _Funct_ ]( );
}
void recCOP1_W( void ) {
recCP1W[ _Funct_ ]( );
}
//------------------------------------------------------------------
//------------------------------------------------------------------
// *FPU Opcodes!*
//------------------------------------------------------------------
@ -1776,3 +1761,5 @@ void recRSQRT_S_xmm(int info)
FPURECOMPILE_CONSTCODE(RSQRT_S, XMMINFO_WRITED|XMMINFO_READS|XMMINFO_READT);
#endif // FPU_RECOMPILE
}}}

83
pcsx2/x86/iFPU.h
View File

@ -19,41 +19,54 @@
#ifndef __IFPU_H__
#define __IFPU_H__
void recMFC1( void );
void recCFC1( void );
void recMTC1( void );
void recCTC1( void );
void recCOP1_BC1( void );
void recCOP1_S( void );
void recCOP1_W( void );
void recC_EQ( void );
void recC_F( void );
void recC_LT( void );
void recC_LE( void );
void recADD_S( void );
void recSUB_S( void );
void recMUL_S( void );
void recDIV_S( void );
void recSQRT_S( void );
void recABS_S( void );
void recMOV_S( void );
void recNEG_S( void );
void recRSQRT_S( void );
void recADDA_S( void );
void recSUBA_S( void );
void recMULA_S( void );
void recMADD_S( void );
void recMSUB_S( void );
void recMADDA_S( void );
void recMSUBA_S( void );
void recCVT_S( void );
void recCVT_W( void );
void recMAX_S( void );
void recMIN_S( void );
void recBC1F( void );
void recBC1T( void );
void recBC1FL( void );
void recBC1TL( void );
namespace Dynarec {
namespace R5900
{
void SaveCW();
void LoadCW();
namespace OpcodeImpl
{
void recCOP1_Unknown();
void recMFC1( void );
void recCFC1( void );
void recMTC1( void );
void recCTC1( void );
void recCOP1_BC1( void );
void recCOP1_S( void );
void recCOP1_W( void );
void recC_EQ( void );
void recC_F( void );
void recC_LT( void );
void recC_LE( void );
void recADD_S( void );
void recSUB_S( void );
void recMUL_S( void );
void recDIV_S( void );
void recSQRT_S( void );
void recABS_S( void );
void recMOV_S( void );
void recNEG_S( void );
void recRSQRT_S( void );
void recADDA_S( void );
void recSUBA_S( void );
void recMULA_S( void );
void recMADD_S( void );
void recMSUB_S( void );
void recMADDA_S( void );
void recMSUBA_S( void );
void recCVT_S( void );
void recCVT_W( void );
void recMAX_S( void );
void recMIN_S( void );
void recBC1F( void );
void recBC1T( void );
void recBC1FL( void );
void recBC1TL( void );
}
} }
#endif

6
pcsx2/x86/iGS.cpp
View File

@ -34,6 +34,10 @@ extern u8 g_RealGSMem[0x2000];
#define PS2GS_BASE(mem) (g_RealGSMem+(mem&0x13ff))
#endif
namespace Dynarec {
using namespace R5900;
// __thiscall -- Calling Convention Notes.
// ** MSVC passes the pointer to the object as ECX. Other parameters are passed normally
@ -301,3 +305,5 @@ void gsConstRead128(u32 mem, int xmmreg)
GIF_LOG("GS read 128 %8.8lx (%8.8x), at %8.8lx\n", (uptr)PS2GS_BASE(mem), mem);
_eeReadConstMem128( xmmreg, (uptr)PS2GS_BASE(mem));
}
} // end namespace Dynarec

3
pcsx2/x86/iHw.cpp
View File

@ -37,6 +37,9 @@ extern int rdram_sdevid;
extern char sio_buffer[1024];
extern int sio_count;
using namespace Dynarec;
using namespace Dynarec::R5900;
int hwConstRead8(u32 x86reg, u32 mem, u32 sign)
{
if( mem >= 0x10000000 && mem < 0x10008000 )

52
pcsx2/x86/iMMI.cpp
View File

@ -29,7 +29,9 @@
#include "iR5900.h"
#include "iMMI.h"
namespace EE { namespace Dynarec { namespace OpcodeImpl
namespace Dynarec {
namespace R5900 {
namespace OpcodeImpl
{
#ifndef MMI_RECOMPILE
@ -247,7 +249,7 @@ CPU_SSE2_XMMCACHE_START(XMMINFO_WRITED|XMMINFO_READLO|XMMINFO_READHI)
_deleteEEreg(XMMGPR_LO, 1);
_deleteEEreg(XMMGPR_HI, 1);
iFlushCall(FLUSH_CACHED_REGS); // since calling CALLFunc
CALLFunc( (uptr)Interpreter::OpcodeImpl::PMFHL );
CALLFunc( (uptr)R5900::Interpreter::OpcodeImpl::PMFHL );
break;
case 0x03: // LH
@ -543,42 +545,6 @@ void recPLZCW( void )
}
*/
#ifdef MMI0_RECOMPILE
void recMMI0( void )
{
EE::OpcodeTables::MMI0[ _Sa_ ].recompile( );
}
#endif
#ifdef MMI1_RECOMPILE
void recMMI1( void )
{
EE::OpcodeTables::MMI1[ _Sa_ ].recompile( );
}
#endif
#ifdef MMI2_RECOMPILE
void recMMI2( void )
{
EE::OpcodeTables::MMI2[ _Sa_ ].recompile( );
}
#endif
#ifdef MMI3_RECOMPILE
void recMMI3( void )
{
EE::OpcodeTables::MMI3[ _Sa_ ].recompile( );
}
#endif
#endif
/*********************************************************
@ -1026,7 +992,7 @@ void recPADDSW( void )
MOV32ItoM( (uptr)&cpuRegs.code, cpuRegs.code );
MOV32ItoM( (uptr)&cpuRegs.pc, pc );
CALLFunc( (uptr)Interpreter::OpcodeImpl::PADDSW );
CALLFunc( (uptr)R5900::Interpreter::OpcodeImpl::PADDSW );
}
////////////////////////////////////////////////////
@ -1117,7 +1083,7 @@ void recPSUBSW( void )
MOV32ItoM( (uptr)&cpuRegs.code, cpuRegs.code );
MOV32ItoM( (uptr)&cpuRegs.pc, pc );
CALLFunc( (uptr)Interpreter::OpcodeImpl::PSUBSW );
CALLFunc( (uptr)R5900::Interpreter::OpcodeImpl::PSUBSW );
}
////////////////////////////////////////////////////
@ -1545,7 +1511,7 @@ CPU_SSE_XMMCACHE_END
MOV32ItoM( (uptr)&cpuRegs.code, cpuRegs.code );
MOV32ItoM( (uptr)&cpuRegs.pc, pc );
CALLFunc( (uptr)Interpreter::OpcodeImpl::PABSW );
CALLFunc( (uptr)R5900::Interpreter::OpcodeImpl::PABSW );
}
////////////////////////////////////////////////////
@ -1569,7 +1535,7 @@ CPU_SSE_XMMCACHE_END
MOV32ItoM( (uptr)&cpuRegs.code, cpuRegs.code );
MOV32ItoM( (uptr)&cpuRegs.pc, pc );
CALLFunc( (uptr)Interpreter::OpcodeImpl::PABSW );
CALLFunc( (uptr)R5900::Interpreter::OpcodeImpl::PABSW );
}
////////////////////////////////////////////////////
@ -2907,7 +2873,7 @@ void recPSRAVW( void )
MOV32ItoM( (uptr)&cpuRegs.pc, (u32)pc );
iFlushCall(FLUSH_EVERYTHING);
if( _Rd_ > 0 ) _deleteEEreg(_Rd_, 0);
CALLFunc( (uptr)Interpreter::OpcodeImpl::PSRAVW );
CALLFunc( (uptr)R5900::Interpreter::OpcodeImpl::PSRAVW );
}

7
pcsx2/x86/iMMI.h
View File

@ -24,8 +24,12 @@
#ifndef __IMMI_H__
#define __IMMI_H__
namespace EE { namespace Dynarec { namespace OpcodeImpl
namespace Dynarec {
namespace R5900 {
namespace OpcodeImpl
{
void recMMI_Unknown();
void recMADD();
void recMADDU();
void recPLZCW();
@ -135,4 +139,3 @@ namespace EE { namespace Dynarec { namespace OpcodeImpl
#endif

9
pcsx2/x86/iPsxHw.cpp
View File

@ -21,9 +21,17 @@
#include "PsxCommon.h"
#include "iR5900.h"
// iPsxHw uses the R5900 flushcall because this module can be called from both
// the EE and the IOP -- R5900's iFlushCall is compatible with iPsxFlushcall, but
// iPsxFlushCall does not flush all the regtypes that iFlushCall does.
using ::Dynarec::R5900::iFlushCall;
extern int g_pbufi;
extern s8 g_pbuf[1024];
namespace Dynarec
{
#define CONSTREAD8_CALL(name) { \
iFlushCall(0); \
CALLFunc((uptr)name); \
@ -1178,3 +1186,4 @@ void psxHw4ConstWrite8(u32 add, int mmreg) {
}
}
} // end namespace Dynarec

7
pcsx2/x86/iPsxMem.cpp
View File

@ -23,8 +23,12 @@
#include "iCore.h"
#include "iR3000A.h"
extern u32 g_psxMaxRecMem;
extern int g_psxWriteOk;
namespace Dynarec
{
extern u32 g_psxMaxRecMem;
static u32 writectrl;
#ifdef PCSX2_VIRTUAL_MEM
@ -869,3 +873,4 @@ int psxRecMemConstWrite32(u32 mem, int mmreg)
}
#endif
}

17
pcsx2/x86/iR3000A.cpp
View File

@ -42,10 +42,16 @@
#include "SamplProf.h"
u32 g_psxMaxRecMem = 0;
extern const char *disRNameGPR[];
using namespace R3000a;
extern char* disR3000Fasm(u32 code, u32 pc);
extern u32 g_psxNextBranchCycle;
extern void psxBREAK();
namespace Dynarec
{
u32 g_psxMaxRecMem = 0;
u32 s_psxrecblocks[] = {0};
//Using assembly code from an external file.
@ -689,7 +695,6 @@ static __forceinline void R3000AExecute()
}
}
extern u32 g_psxNextBranchCycle;
u32 g_psxlastpc = 0;
#if defined(_MSC_VER)
@ -1006,8 +1011,6 @@ static void iPsxBranchTest(u32 newpc, u32 cpuBranch)
j8Ptr[2] = JG8( 0 ); // jump if psxCycleEE > 0
if( REC_INC_STACK )
ADD64ItoR(ESP, REC_INC_STACK);
RET2(); // returns control to the EE
// Continue onward with branching here:
@ -1066,7 +1069,6 @@ void rpsxSYSCALL()
//if (!psxbranch) psxbranch = 2;
}
void psxBREAK();
void rpsxBREAK()
{
MOV32ItoM( (uptr)&psxRegs.code, psxRegs.code );
@ -1554,6 +1556,9 @@ StartRecomp:
assert( s_pCurBlock->pFnptr != 0 );
}
}
using namespace Dynarec;
R3000Acpu psxRec = {
recInit,
recReset,

5
pcsx2/x86/iR3000A.h
View File

@ -29,7 +29,8 @@ static const int psxInstCycles_Peephole_Store = 0;
static const int psxInstCycles_Store = 0;
static const int psxInstCycles_Load = 0;
namespace Dynarec
{
// to be consistent with EE
#define PSX_HI XMMGPR_HI
#define PSX_LO XMMGPR_LO
@ -114,4 +115,6 @@ void psxRecompileCodeConst2(R3000AFNPTR constcode, R3000AFNPTR_INFO noconstcode)
// [lo,hi] = rt op rs
void psxRecompileCodeConst3(R3000AFNPTR constcode, R3000AFNPTR_INFO constscode, R3000AFNPTR_INFO consttcode, R3000AFNPTR_INFO noconstcode, int LOHI);
} // end namespace Dynarec
#endif

15
pcsx2/x86/iR3000Atables.cpp
View File

@ -32,11 +32,14 @@ extern void psxSWL();
extern void psxSWR();
extern int g_psxWriteOk;
namespace Dynarec
{
extern u32 g_psxMaxRecMem;
// R3000A instruction implementation
#define REC_FUNC(f) \
void psx##f(); \
static void rpsx##f() { \
MOV32ItoM((uptr)&psxRegs.code, (u32)psxRegs.code); \
_psxFlushCall(FLUSH_EVERYTHING); \
@ -2004,9 +2007,7 @@ void rpsxpropREGIMM(EEINST* prev, EEINST* pinst)
rpsxpropSetRead(_Rs_);
break;
default:
assert(0);
break;
jNO_DEFAULT
}
}
@ -2028,7 +2029,9 @@ void rpsxpropCP0(EEINST* prev, EEINST* pinst)
break;
case 16: // rfe
break;
default:
assert(0);
jNO_DEFAULT
}
}
}

64
pcsx2/x86/iR5900.h
View File

@ -19,6 +19,7 @@
#ifndef __IR5900_H__
#define __IR5900_H__
#include "R5900.h"
#include "VU.h"
#include "iCore.h"
@ -41,18 +42,14 @@
#define CP2_RECOMPILE
#define EE_CONST_PROP // rec2 - enables constant propagation (faster)
//#define EE_FPU_REGCACHING 1 // Not used anymore, its always on!
namespace Dynarec {
namespace R5900 {
using namespace ::R5900; // This makes sure the Dynarec inherits all R5900 globals.
#define PC_GETBLOCK(x) PC_GETBLOCK_(x, recLUT)
void recClearMem(BASEBLOCK* p);
#define REC_CLEARM(mem) { \
if ((mem) < maxrecmem && recLUT[(mem) >> 16]) { \
BASEBLOCK* p = PC_GETBLOCK(mem); \
if( *(u32*)p ) recClearMem(p); \
} \
} \
extern u32 pc;
extern int branch;
extern uptr* recLUT;
@ -61,39 +58,41 @@ extern u32 maxrecmem;
extern u32 pc; // recompiler pc
extern int branch; // set for branch
extern u32 target; // branch target
extern u16 x86FpuState;
extern u16 iCWstate;
extern u32 s_nBlockCycles; // cycles of current block recompiling
extern u32 s_saveConstGPRreg;
extern GPR_reg64 s_ConstGPRreg;
#define REC_FUNC_INLINE( f, delreg ) \
MOV32ItoM( (uptr)&cpuRegs.code, (u32)cpuRegs.code ); \
MOV32ItoM( (uptr)&cpuRegs.pc, (u32)pc ); \
iFlushCall(FLUSH_EVERYTHING); \
if( (delreg) > 0 ) _deleteEEreg(delreg, 0); \
CALLFunc( (uptr)EE::Interpreter::OpcodeImpl::f );
CALLFunc( (uptr)R5900::Interpreter::OpcodeImpl::f );
#define REC_FUNC( f, delreg ) \
void f( void ); \
void rec##f( void ) \
{ \
MOV32ItoM( (uptr)&cpuRegs.code, (u32)cpuRegs.code ); \
MOV32ItoM( (uptr)&cpuRegs.pc, (u32)pc ); \
iFlushCall(FLUSH_EVERYTHING); \
if( (delreg) > 0 ) _deleteEEreg(delreg, 0); \
CALLFunc( (uptr)Interpreter::OpcodeImpl::f ); \
CALLFunc( (uptr)R5900::Interpreter::OpcodeImpl::f ); \
}
#define REC_SYS( f ) \
void f( void ); \
void rec##f( void ) \
{ \
MOV32ItoM( (uptr)&cpuRegs.code, (u32)cpuRegs.code ); \
MOV32ItoM( (uptr)&cpuRegs.pc, (u32)pc ); \
iFlushCall(FLUSH_EVERYTHING); \
CALLFunc( (uptr)f ); \
CALLFunc( (uptr)R5900::Interpreter::OpcodeImpl::f ); \
branch = 2; \
}
// Used to clear recompiled code blocks during memory/dma write operations.
void recClearMem(BASEBLOCK* p);
void REC_CLEARM( u32 mem );
// used when processing branches
void SaveBranchState();
void LoadBranchState();
@ -103,29 +102,19 @@ void SetBranchReg( u32 reg );
void SetBranchImm( u32 imm );
void iFlushCall(int flushtype);
void SaveCW();
void LoadCW();
extern void (*recCP0[32])();
extern void (*recCP0BC0[32])();
extern void (*recCP0C0[64])();
extern void (*recCP1[32])();
extern void (*recCP1BC1[32])();
extern void (*recCP1S[64])();
extern void (*recCP1W[64])();
namespace EE { namespace Dynarec {
extern void (*recBSC_co[64])();
void recBranchCall( void (*func)() );
} }
extern void (*recBSC_co[64])();
void recBranchCall( void (*func)() );
u32* _eeGetConstReg(int reg); // gets a memory pointer to the constant reg
void _eeFlushAllUnused();
void _eeOnWriteReg(int reg, int signext);
// these are defined in iFPU.cpp
void LoadCW();
void SaveCW(int type);
// totally deletes from const, xmm, and mmx entries
// if flush is 1, also flushes to memory
// if 0, only flushes if not an xmm reg (used when overwriting lower 64bits of reg)
@ -234,7 +223,7 @@ void eeRecompileCodeConstSPECIAL(R5900FNPTR constcode, R5900FNPTR_INFO multicode
#define FPURECOMPILE_CONSTCODE(fn, xmminfo) \
void rec##fn(void) \
{ \
eeFPURecompileCode(rec##fn##_xmm, fn, xmminfo); \
eeFPURecompileCode(rec##fn##_xmm, R5900::Interpreter::OpcodeImpl::fn, xmminfo); \
}
// rd = rs op rt (all regs need to be in xmm)
@ -288,13 +277,6 @@ protected:
};
// perf counters
#ifdef PCSX2_DEVBUILD
extern void StartPerfCounter();
extern void StopPerfCounter();
#else
#define StartPerfCounter()
#define StopPerfCounter()
#endif
} }
#endif // __IR5900_H__

4
pcsx2/x86/iR5900Arit.h
View File

@ -24,7 +24,9 @@
* Format: OP rd, rs, rt *
*********************************************************/
namespace EE { namespace Dynarec { namespace OpcodeImpl
namespace Dynarec {
namespace R5900 {
namespace OpcodeImpl
{
void recADD( void );
void recADDU( void );

4
pcsx2/x86/iR5900AritImm.h
View File

@ -23,7 +23,9 @@
* Arithmetic with immediate operand *
* Format: OP rt, rs, immediate *
*********************************************************/
namespace EE { namespace Dynarec { namespace OpcodeImpl
namespace Dynarec {
namespace R5900 {
namespace OpcodeImpl
{
void recADDI( void );
void recADDIU( void );

4
pcsx2/x86/iR5900Branch.h
View File

@ -24,7 +24,9 @@
* Format: OP rd, rt, sa *
*********************************************************/
namespace EE { namespace Dynarec { namespace OpcodeImpl
namespace Dynarec {
namespace R5900 {
namespace OpcodeImpl
{
void recBEQ( void );
void recBEQL( void );

4
pcsx2/x86/iR5900Jump.h
View File

@ -24,7 +24,9 @@
* Format: OP target *
*********************************************************/
namespace EE { namespace Dynarec { namespace OpcodeImpl
namespace Dynarec {
namespace R5900 {
namespace OpcodeImpl
{
void recJ( void );
void recJAL( void );

6
pcsx2/x86/iR5900LoadStore.h
View File

@ -23,7 +23,9 @@
* Format: OP rt, offset(base) *
*********************************************************/
namespace EE { namespace Dynarec { namespace OpcodeImpl
namespace Dynarec {
namespace R5900 {
namespace OpcodeImpl
{
void recLB( void );
void recLBU( void );
@ -52,7 +54,7 @@ namespace EE { namespace Dynarec { namespace OpcodeImpl
void recSQC2( void );
// coissues
#ifdef PCSX2_VIRTUAL_MEM
#ifdef PCSX2_VIRTUAL_MEM
void recLB_co( void );
void recLBU_co( void );
void recLH_co( void );

4
pcsx2/x86/iR5900Move.h
View File

@ -19,7 +19,9 @@
#ifndef __IR5900MOVE_H__
#define __IR5900MOVE_H__
namespace EE { namespace Dynarec { namespace OpcodeImpl
namespace Dynarec {
namespace R5900 {
namespace OpcodeImpl
{
void recLUI( void );
void recMFLO( void );

4
pcsx2/x86/iR5900MultDiv.h
View File

@ -24,7 +24,9 @@
* Format: OP rs, rt *
*********************************************************/
namespace EE { namespace Dynarec { namespace OpcodeImpl
namespace Dynarec {
namespace R5900 {
namespace OpcodeImpl
{
void recMULT( void );
void recMULTU( void );

4
pcsx2/x86/iR5900Shift.h
View File

@ -24,7 +24,9 @@
* Format: OP rd, rt, sa *
*********************************************************/
namespace EE { namespace Dynarec { namespace OpcodeImpl
namespace Dynarec {
namespace R5900 {
namespace OpcodeImpl
{
void recSLL( void );
void recSRL( void );

12
pcsx2/x86/iVU0micro.cpp
View File

@ -37,7 +37,9 @@
#pragma warning(disable:4761)
#endif
static VURegs * const VU = (VURegs*)&VU0;
namespace Dynarec
{
#ifdef _DEBUG
extern u32 vudump;
#endif
@ -61,7 +63,7 @@ void recExecuteVU0Block( void )
SuperVUExecuteProgram(VU0.VI[ REG_TPC ].UL & 0xfff, 0);
FreezeXMMRegs(0);
}
else intExecuteVU0Block();
else ::R5900::Interpreter::intExecuteVU0Block();
//}
}
@ -72,3 +74,9 @@ void recClearVU0( u32 Addr, u32 Size )
}
}
void recResetVU0( void )
{
SuperVUReset(0);
}
}

18
pcsx2/x86/iVU1micro.cpp
View File

@ -29,7 +29,7 @@
#include "iCP0.h"
#include "VU.h"
#include "VUmicro.h"
#include "iVUmicro.h"
#include "iVUzerorec.h"
#include "iVUops.h"
#include "VUops.h"
@ -40,6 +40,14 @@
#pragma warning(disable:4761)
#endif
// fixme - having the VUs share the branch/pc values of the R5900 is bad on so many levels... >_< (air)
using ::Dynarec::R5900::pc;
using ::Dynarec::R5900::branch;
namespace Dynarec
{
#define VU ((VURegs*)&VU1)
//Lower/Upper instructions can use that..
@ -73,11 +81,6 @@
#define VU1_ACCz_ADDR (uptr)&VU1.ACC.UL[2]
#define VU1_ACCw_ADDR (uptr)&VU1.ACC.UL[3]
extern void SuperVUInit(int vuindex);
extern void SuperVUDestroy(int vuindex);
extern void SuperVUReset(int vuindex);
extern void SuperVUExecuteProgram(u32 startpc, int vuindex);
extern void SuperVUClear(u32 startpc, u32 size, int vuindex);
void recVU1Init()
{
@ -169,7 +172,7 @@ void recExecuteVU1Block(void)
}
#endif
while (VU0.VI[ REG_VPU_STAT ].UL&0x100) {
intExecuteVU1Block();
::R5900::Interpreter::intExecuteVU1Block();
}
}
}
@ -178,3 +181,4 @@ void recClearVU1( u32 Addr, u32 Size ) {
assert( (Addr&7) == 0 );
if( CHECK_VU1REC ) SuperVUClear(Addr, Size*4, 1);
}
}

5
pcsx2/x86/iVUmicro.cpp
View File

@ -38,6 +38,10 @@
#endif
//------------------------------------------------------------------
namespace Dynarec
{
using ::Dynarec::R5900::pc;
using ::Dynarec::R5900::branch;
//------------------------------------------------------------------
// Helper Macros
@ -1269,3 +1273,4 @@ void SetVUNanMode(int mode)
if ( mode ) SysPrintf("enabling vunan mode");
}
}

5
pcsx2/x86/iVUmicro.h
View File

@ -19,6 +19,9 @@
#ifndef __IVUMICRO_H__
#define __IVUMICRO_H__
namespace Dynarec
{
#define VU0_MEMSIZE 0x1000
#define VU1_MEMSIZE 0x4000
@ -279,4 +282,6 @@ void recVUMI_XTOP(VURegs *vuRegs, int info);
void recVUMI_XITOP(VURegs *vuRegs, int info);
void recVUMI_XTOP( VURegs *VU , int info);
} // end namespace Dynarec
#endif /* __IVUMICRO_H__ */

4
pcsx2/x86/iVUmicroLower.cpp
View File

@ -33,6 +33,8 @@
#include "iVUzerorec.h"
//------------------------------------------------------------------
namespace Dynarec
{
//------------------------------------------------------------------
// Helper Macros
@ -2036,3 +2038,5 @@ void VU1XGKICK_MTGSTransfer(u32 *pMem, u32 addr)
}
}
//------------------------------------------------------------------
} // end namespace Dynarec

6
pcsx2/x86/iVUmicroUpper.cpp
View File

@ -33,6 +33,8 @@
#include "iVUzerorec.h"
//------------------------------------------------------------------
namespace Dynarec
{
//------------------------------------------------------------------
// Helper Macros
@ -2534,4 +2536,6 @@ void recVUMI_CLIP(VURegs *VU, int info)
_freeX86reg(x86temp1);
_freeX86reg(x86temp2);
}
}
} // end namespace Dynarec

42
pcsx2/x86/iVUzerorec.cpp
View File

@ -21,6 +21,10 @@
#include "PrecompiledHeader.h"
#include <float.h>
#include <vector>
#include <list>
#include <map>
#include <algorithm>
#ifndef _WIN32
#include <sys/types.h>
@ -37,30 +41,24 @@
#include "iVUzerorec.h"
#include "SamplProf.h"
// temporary externs
extern u32 vudump;
extern void iDumpVU0Registers();
extern void iDumpVU1Registers();
extern char* disVU1MicroUF(u32 code, u32 pc);
extern char* disVU1MicroLF(u32 code, u32 pc);
#ifdef __LINUX__
#undef max
#undef min
#endif
#include <vector>
#include <list>
#include <map>
#include <algorithm>
using namespace std;
#ifdef _WIN32
#pragma warning(disable:4244)
#pragma warning(disable:4761)
#endif
using namespace std;
using namespace R5900;
using namespace Dynarec::R5900;
namespace Dynarec
{
// temporary externs
extern u32 vudump;
extern void iDumpVU0Registers();
extern void iDumpVU1Registers();
// SuperVURec optimization options, uncomment only for debugging purposes
#define SUPERVU_CACHING // vu programs are saved and queried via memcompare (should be no reason to disable this)
#define SUPERVU_WRITEBACKS // don't flush the writebacks after every block
@ -94,7 +92,7 @@ static u32 s_vuInfo; // info passed into rec insts
static const u32 s_MemSize[2] = {VU0_MEMSIZE, VU1_MEMSIZE};
static u8* s_recVUMem = NULL, *s_recVUPtr = NULL;
// tables
// tables which are defined at the bottom of this massive file.
extern void (*recVU_UPPER_OPCODE[64])( VURegs* VU, s32 info );
extern void (*recVU_LOWER_OPCODE[128])( VURegs* VU, s32 info );
@ -2263,8 +2261,6 @@ static int s_needFlush; // first bit - Q, second bit - P, third bit - Q has been
static int s_JumpX86;
static int s_ScheduleXGKICK = 0, s_XGKICKReg = -1;
extern u32 g_sseVUMXCSR, g_sseMXCSR;
void recVUMI_XGKICK_( VURegs *VU );
void SuperVUCleanupProgram(u32 startpc, int vuindex)
@ -4138,3 +4134,5 @@ void recVUunknown( VURegs* VU, s32 info )
{
SysPrintf("Unknown SVU micromode opcode called\n");
}
}

11
pcsx2/x86/iVUzerorec.h
View File

@ -23,9 +23,11 @@
#include "iVUmicro.h"
void SuperVUInit(int vuindex); // if vuindex is -1, inits the global VU resources
void SuperVUDestroy(int vuindex); // if vuindex is -1, destroys everything
void SuperVUReset(int vuindex); // if vuindex is -1, resets everything
namespace Dynarec
{
extern void SuperVUInit(int vuindex); // if vuindex is -1, inits the global VU resources
extern void SuperVUDestroy(int vuindex); // if vuindex is -1, destroys everything
extern void SuperVUReset(int vuindex); // if vuindex is -1, resets everything
//Using assembly code from an external file.
#ifdef __LINUX__
@ -47,7 +49,6 @@ u32 SuperVUGetVIAddr(int reg, int read);
// if p == 0, flush q else flush p; if wait is != 0, waits for p/q
void SuperVUFlush(int p, int wait);
// These are for recCode called from iVUmicroLower:
}
#endif

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