diff --git a/pcsx2/COP0.cpp b/pcsx2/COP0.cpp index 19dff77f0e..257e173673 100644 --- a/pcsx2/COP0.cpp +++ b/pcsx2/COP0.cpp @@ -22,20 +22,10 @@ #include "R5900.h" #include "InterTables.h" - -void COP0_BC0() { - COP0_LOG("%s\n", disR5900Current.getString()); - Int_COP0BC0PrintTable[(cpuRegs.code >> 16) & 0x03](); -} - -void COP0_Func() { - COP0_LOG("%s\n", disR5900Current.getString()); - Int_COP0C0PrintTable[_Funct_](); -} - -void COP0_Unknown() { - CPU_LOG("COP0 Unknown opcode called\n"); -} +namespace R5900 +{ +u32 s_iLastCOP0Cycle = 0; +u32 s_iLastPERFCycle[2] = { 0, 0 }; void UpdateCP0Status() { u32 value = cpuRegs.CP0.n.Status.val; @@ -54,12 +44,118 @@ void WriteCP0Status(u32 value) { UpdateCP0Status(); } -extern u32 s_iLastCOP0Cycle; -extern u32 s_iLastPERFCycle[2]; +void MapTLB(int i) +{ + u32 mask, addr; + u32 saddr, eaddr; +#ifndef PCSX2_VIRTUAL_MEM + DevCon::WriteLn("MAP TLB %d: %08x-> [%08x %08x] S=%d G=%d ASID=%d Mask= %03X", params + i,tlb[i].VPN2,tlb[i].PFN0,tlb[i].PFN1,tlb[i].S,tlb[i].G,tlb[i].ASID,tlb[i].Mask); + + if (tlb[i].S) + { + SysPrintf("OMG SPRAM MAPPING %08X %08X\n",tlb[i].VPN2,tlb[i].Mask); + vtlb_VMapBuffer(tlb[i].VPN2,psS,0x4000); + } +#endif + if (tlb[i].VPN2 == 0x70000000) return; //uh uhh right ... + + if (tlb[i].EntryLo0 & 0x2) { + mask = ((~tlb[i].Mask) << 1) & 0xfffff; + saddr = tlb[i].VPN2 >> 12; + eaddr = saddr + tlb[i].Mask + 1; + + for (addr=saddr; addr> 12) & mask)) { //match + memSetPageAddr(addr << 12, tlb[i].PFN0 + ((addr - saddr) << 12)); + Cpu->Clear(addr << 12, 1); + } + } + } + + if (tlb[i].EntryLo1 & 0x2) { + mask = ((~tlb[i].Mask) << 1) & 0xfffff; + saddr = (tlb[i].VPN2 >> 12) + tlb[i].Mask + 1; + eaddr = saddr + tlb[i].Mask + 1; + + for (addr=saddr; addr> 12) & mask)) { //match + memSetPageAddr(addr << 12, tlb[i].PFN1 + ((addr - saddr) << 12)); + Cpu->Clear(addr << 12, 1); + } + } + } +} + +void UnmapTLB(int i) +{ + //SysPrintf("Clear TLB %d: %08x-> [%08x %08x] S=%d G=%d ASID=%d Mask= %03X\n",i,tlb[i].VPN2,tlb[i].PFN0,tlb[i].PFN1,tlb[i].S,tlb[i].G,tlb[i].ASID,tlb[i].Mask); + u32 mask, addr; + u32 saddr, eaddr; + +#ifndef PCSX2_VIRTUAL_MEM + if (tlb[i].S) + { + vtlb_VMapUnmap(tlb[i].VPN2,0x4000); + return; + } +#endif + + if (tlb[i].EntryLo0 & 0x2) + { + mask = ((~tlb[i].Mask) << 1) & 0xfffff; + saddr = tlb[i].VPN2 >> 12; + eaddr = saddr + tlb[i].Mask + 1; + // SysPrintf("Clear TLB: %08x ~ %08x\n",saddr,eaddr-1); + for (addr=saddr; addr> 12) & mask)) { //match + memClearPageAddr(addr << 12); + Cpu->Clear(addr << 12, 1); + } + } + } + + if (tlb[i].EntryLo1 & 0x2) { + mask = ((~tlb[i].Mask) << 1) & 0xfffff; + saddr = (tlb[i].VPN2 >> 12) + tlb[i].Mask + 1; + eaddr = saddr + tlb[i].Mask + 1; + // SysPrintf("Clear TLB: %08x ~ %08x\n",saddr,eaddr-1); + for (addr=saddr; addr> 12) & mask)) { //match + memClearPageAddr(addr << 12); + Cpu->Clear(addr << 12, 1); + } + } + } +} + +void WriteTLB(int i) +{ + tlb[i].PageMask = cpuRegs.CP0.n.PageMask; + tlb[i].EntryHi = cpuRegs.CP0.n.EntryHi; + tlb[i].EntryLo0 = cpuRegs.CP0.n.EntryLo0; + tlb[i].EntryLo1 = cpuRegs.CP0.n.EntryLo1; + + tlb[i].Mask = (cpuRegs.CP0.n.PageMask >> 13) & 0xfff; + tlb[i].nMask = (~tlb[i].Mask) & 0xfff; + tlb[i].VPN2 = ((cpuRegs.CP0.n.EntryHi >> 13) & (~tlb[i].Mask)) << 13; + tlb[i].ASID = cpuRegs.CP0.n.EntryHi & 0xfff; + tlb[i].G = cpuRegs.CP0.n.EntryLo0 & cpuRegs.CP0.n.EntryLo1 & 0x1; + tlb[i].PFN0 = (((cpuRegs.CP0.n.EntryLo0 >> 6) & 0xFFFFF) & (~tlb[i].Mask)) << 12; + tlb[i].PFN1 = (((cpuRegs.CP0.n.EntryLo1 >> 6) & 0xFFFFF) & (~tlb[i].Mask)) << 12; +#ifndef PCSX2_VIRTUAL_MEM + tlb[i].S = cpuRegs.CP0.n.EntryLo0&0x80000000; +#endif + MapTLB(i); +} + +namespace Interpreter { +namespace OpcodeImpl +{ void MFC0() { if (!_Rt_) return; - if (_Rd_ != 9) { COP0_LOG("%s\n", disR5900Current.getString()); } + if (_Rd_ != 9) { COP0_LOG("%s\n", disR5900Current.getCString() ); } //if(bExecBIOS == FALSE && _Rd_ == 25) SysPrintf("MFC0 _Rd_ %x = %x\n", _Rd_, cpuRegs.CP0.r[_Rd_]); switch (_Rd_) { @@ -99,7 +195,7 @@ void MFC0() { } void MTC0() { - COP0_LOG("%s\n", disR5900Current.getString()); + COP0_LOG("%s\n", disR5900Current.getCString()); //if(bExecBIOS == FALSE && _Rd_ == 25) SysPrintf("MTC0 _Rd_ %x = %x\n", _Rd_, cpuRegs.CP0.r[_Rd_]); switch (_Rd_) { case 25: @@ -178,111 +274,6 @@ void TLBR() { cpuRegs.CP0.n.EntryLo1 =(tlb[i].EntryLo1&~1)|((tlb[i].EntryHi>>12)&1); } -void UnmapTLB(int i) -{ - //SysPrintf("Clear TLB %d: %08x-> [%08x %08x] S=%d G=%d ASID=%d Mask= %03X\n",i,tlb[i].VPN2,tlb[i].PFN0,tlb[i].PFN1,tlb[i].S,tlb[i].G,tlb[i].ASID,tlb[i].Mask); - u32 mask, addr; - u32 saddr, eaddr; - -#ifndef PCSX2_VIRTUAL_MEM - if (tlb[i].S) - { - vtlb_VMapUnmap(tlb[i].VPN2,0x4000); - return; - } -#endif - - if (tlb[i].EntryLo0 & 0x2) - { - mask = ((~tlb[i].Mask) << 1) & 0xfffff; - saddr = tlb[i].VPN2 >> 12; - eaddr = saddr + tlb[i].Mask + 1; - // SysPrintf("Clear TLB: %08x ~ %08x\n",saddr,eaddr-1); - for (addr=saddr; addr> 12) & mask)) { //match - memClearPageAddr(addr << 12); - Cpu->Clear(addr << 12, 1); - } - } - } - - if (tlb[i].EntryLo1 & 0x2) { - mask = ((~tlb[i].Mask) << 1) & 0xfffff; - saddr = (tlb[i].VPN2 >> 12) + tlb[i].Mask + 1; - eaddr = saddr + tlb[i].Mask + 1; - // SysPrintf("Clear TLB: %08x ~ %08x\n",saddr,eaddr-1); - for (addr=saddr; addr> 12) & mask)) { //match - memClearPageAddr(addr << 12); - Cpu->Clear(addr << 12, 1); - } - } - } -} - -void MapTLB(int i) -{ - u32 mask, addr; - u32 saddr, eaddr; - -#ifndef PCSX2_VIRTUAL_MEM - DevCon::WriteLn("MAP TLB %d: %08x-> [%08x %08x] S=%d G=%d ASID=%d Mask= %03X", params - i,tlb[i].VPN2,tlb[i].PFN0,tlb[i].PFN1,tlb[i].S,tlb[i].G,tlb[i].ASID,tlb[i].Mask); - - if (tlb[i].S) - { - SysPrintf("OMG SPRAM MAPPING %08X %08X\n",tlb[i].VPN2,tlb[i].Mask); - vtlb_VMapBuffer(tlb[i].VPN2,psS,0x4000); - } -#endif - if (tlb[i].VPN2 == 0x70000000) return; //uh uhh right ... - - if (tlb[i].EntryLo0 & 0x2) { - mask = ((~tlb[i].Mask) << 1) & 0xfffff; - saddr = tlb[i].VPN2 >> 12; - eaddr = saddr + tlb[i].Mask + 1; - - for (addr=saddr; addr> 12) & mask)) { //match - memSetPageAddr(addr << 12, tlb[i].PFN0 + ((addr - saddr) << 12)); - Cpu->Clear(addr << 12, 1); - } - } - } - - if (tlb[i].EntryLo1 & 0x2) { - mask = ((~tlb[i].Mask) << 1) & 0xfffff; - saddr = (tlb[i].VPN2 >> 12) + tlb[i].Mask + 1; - eaddr = saddr + tlb[i].Mask + 1; - - for (addr=saddr; addr> 12) & mask)) { //match - memSetPageAddr(addr << 12, tlb[i].PFN1 + ((addr - saddr) << 12)); - Cpu->Clear(addr << 12, 1); - } - } - } -} -void WriteTLB(int i) -{ - tlb[i].PageMask = cpuRegs.CP0.n.PageMask; - tlb[i].EntryHi = cpuRegs.CP0.n.EntryHi; - tlb[i].EntryLo0 = cpuRegs.CP0.n.EntryLo0; - tlb[i].EntryLo1 = cpuRegs.CP0.n.EntryLo1; - - tlb[i].Mask = (cpuRegs.CP0.n.PageMask >> 13) & 0xfff; - tlb[i].nMask = (~tlb[i].Mask) & 0xfff; - tlb[i].VPN2 = ((cpuRegs.CP0.n.EntryHi >> 13) & (~tlb[i].Mask)) << 13; - tlb[i].ASID = cpuRegs.CP0.n.EntryHi & 0xfff; - tlb[i].G = cpuRegs.CP0.n.EntryLo0 & cpuRegs.CP0.n.EntryLo1 & 0x1; - tlb[i].PFN0 = (((cpuRegs.CP0.n.EntryLo0 >> 6) & 0xFFFFF) & (~tlb[i].Mask)) << 12; - tlb[i].PFN1 = (((cpuRegs.CP0.n.EntryLo1 >> 6) & 0xFFFFF) & (~tlb[i].Mask)) << 12; -#ifndef PCSX2_VIRTUAL_MEM - tlb[i].S = cpuRegs.CP0.n.EntryLo0&0x80000000; -#endif - MapTLB(i); -} - void TLBWI() { int j = cpuRegs.CP0.n.Index & 0x3f; @@ -367,3 +358,4 @@ void EI() { } } +} } } // end namespace R5900::Interpreter::OpcodeImpl \ No newline at end of file diff --git a/pcsx2/COP0.h b/pcsx2/COP0.h index 6fb2a200d0..dbcd54e9d0 100644 --- a/pcsx2/COP0.h +++ b/pcsx2/COP0.h @@ -19,10 +19,13 @@ #ifndef __COP0_H__ #define __COP0_H__ -void WriteCP0Status(u32 value); -void UpdateCP0Status(); -void WriteTLB(int i); -void UnmapTLB(int i); -void MapTLB(int i); +namespace R5900 +{ + void WriteCP0Status(u32 value); + void UpdateCP0Status(); + void WriteTLB(int i); + void UnmapTLB(int i); + void MapTLB(int i); +} #endif /* __COP0_H__ */ diff --git a/pcsx2/COP2.cpp b/pcsx2/COP2.cpp new file mode 100644 index 0000000000..7ac8675e12 --- /dev/null +++ b/pcsx2/COP2.cpp @@ -0,0 +1,89 @@ +/* Pcsx2 - Pc Ps2 Emulator + * Copyright (C) 2002-2008 Pcsx2 Team + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA + */ + +#include "PrecompiledHeader.h" + +#include "Common.h" +#include "DebugTools/Debug.h" +#include "R5900.h" +#include "InterTables.h" +#include "VUops.h" +#include "VUmicro.h" + +//namespace R5900 { +//namespace Interpreter { +//namespace OpcodeImpl{ + +using namespace R5900; +using namespace R5900::Interpreter; + +#define CP2COND (((VU0.VI[REG_VPU_STAT].US[0] >> 8) & 1)) + +void VCALLMS() { + vu0Finish(); + vu0ExecMicro(((cpuRegs.code >> 6) & 0x7FFF) * 8); +} + +void VCALLMSR() { + vu0Finish(); + vu0ExecMicro(VU0.VI[REG_CMSAR0].US[0] * 8); +} + +void BC2F() +{ + if (CP2COND == 0) + { + SysPrintf("VU0 Macro Branch \n"); + intDoBranch(_BranchTarget_); + } +} +void BC2T() +{ + if (CP2COND == 1) + { + SysPrintf("VU0 Macro Branch \n"); + intDoBranch(_BranchTarget_); + } +} + +void BC2FL() +{ + if (CP2COND == 0) + { + SysPrintf("VU0 Macro Branch \n"); + intDoBranch(_BranchTarget_); + } + else + { + cpuRegs.pc+= 4; + } +} +void BC2TL() +{ + if (CP2COND == 1) + { + SysPrintf("VU0 Macro Branch \n"); + intDoBranch(_BranchTarget_); + } + else + { + cpuRegs.pc+= 4; + } +} + +//}}} diff --git a/pcsx2/Cache.cpp b/pcsx2/Cache.cpp index 218693d2db..d1c86c7daa 100644 --- a/pcsx2/Cache.cpp +++ b/pcsx2/Cache.cpp @@ -23,7 +23,8 @@ _cacheS pCache[64]; -namespace EE { namespace Interpreter { namespace OpcodeImpl +namespace R5900{ +namespace Interpreter { #ifdef PCSX2_CACHE_EMU_MEM @@ -147,6 +148,9 @@ u8 *readCache(u32 mem) { return pCache[i].data[number][(mem>>4) & 0x3].b8._8; } +namespace OpcodeImpl +{ + extern int Dcache; void CACHE() { u32 addr; @@ -381,11 +385,16 @@ void CACHE() { } } } +} // end namespace OpcodeImpl #else +namespace OpcodeImpl +{ + void CACHE() { } +} #endif -}}} // end namespace EE::Interpeter::OpcodeImpl \ No newline at end of file +}} \ No newline at end of file diff --git a/pcsx2/Console.cpp b/pcsx2/Console.cpp index 9a4ae3a642..8bb0b010e0 100644 --- a/pcsx2/Console.cpp +++ b/pcsx2/Console.cpp @@ -23,7 +23,7 @@ using namespace std; -VARG_PARAM va_arg_dummy; +const VARG_PARAM va_arg_dummy = { 0 }; // Methods of the Console namespace not defined here are to be found in the platform // dependent implementations in WinConsole.cpp and LnxConsole.cpp. diff --git a/pcsx2/Counters.cpp b/pcsx2/Counters.cpp index 37218b16c2..d7d47f58f4 100644 --- a/pcsx2/Counters.cpp +++ b/pcsx2/Counters.cpp @@ -27,11 +27,19 @@ using namespace Threading; +extern u8 psxhblankgate; +u32 g_vu1SkipCount; // number of frames to disable/skip VU1 + +static void (*s_prevExecuteVU1Block)() = NULL; // old VU1 block (either Int or Rec) +extern void DummyExecuteVU1Block(void); + +namespace R5900 +{ + u64 profile_starttick = 0; u64 profile_totalticks = 0; int gates = 0; -extern u8 psxhblankgate; // Counter 4 takes care of scanlines - hSync/hBlanks // Counter 5 takes care of vSync/vBlanks @@ -42,11 +50,6 @@ s32 nextCounter; // delta from nextsCounter, in cycles, until the next rcntUpdat // VUSkip Locals and Globals -u32 g_vu1SkipCount; // number of frames to disable/skip VU1 -static void (*s_prevExecuteVU1Block)() = NULL; // old VU1 block (either Int or Rec) - -extern void DummyExecuteVU1Block(void); - void rcntReset(int index) { counters[index].count = 0; counters[index].sCycleT = cpuRegs.cycle; @@ -259,12 +262,6 @@ extern u32 vu0time; void vSyncDebugStuff() { -#ifdef EE_PROFILING - if( (iFrame%20) == 0 ) { - SysPrintf("Profiled Cycles at %d frames %d\n", iFrame, profile_totalticks); - CLEAR_EE_PROFILE(); - } -#endif #ifdef PCSX2_DEVBUILD if( g_TestRun.enabled && g_TestRun.frame > 0 ) { @@ -832,6 +829,10 @@ u32 rcntCycle(int index) return counters[index].count; } +} // End namespace R5900! + +using namespace R5900; + void SaveState::rcntFreeze() { Freeze(counters); @@ -865,4 +866,3 @@ void SaveState::rcntFreeze() iopBranchAction = 1; // probably not needed but won't hurt anything either. } } - diff --git a/pcsx2/Counters.h b/pcsx2/Counters.h index bf0d79b400..f096759130 100644 --- a/pcsx2/Counters.h +++ b/pcsx2/Counters.h @@ -19,6 +19,8 @@ #ifndef __COUNTERS_H__ #define __COUNTERS_H__ +namespace R5900 +{ struct EECNT_MODE { // 0 - BUSCLK @@ -127,8 +129,6 @@ struct Counter { extern Counter counters[6]; extern s32 nextCounter; // delta until the next counter event (must be signed) extern u32 nextsCounter; -extern u32 g_lastVSyncCycle; -extern u32 g_deltaVSyncCycle; extern void rcntUpdate_hScanline(); extern void rcntUpdate_vSync(); @@ -145,5 +145,8 @@ u32 rcntRcount(int index); u32 rcntCycle(int index); u32 UpdateVSyncRate(); +void frameLimitReset(); + +} // End namespace R5900! #endif /* __COUNTERS_H__ */ diff --git a/pcsx2/DebugTools/Debug.h b/pcsx2/DebugTools/Debug.h index 32694451f0..0413ac50bc 100644 --- a/pcsx2/DebugTools/Debug.h +++ b/pcsx2/DebugTools/Debug.h @@ -24,43 +24,52 @@ extern FILE *emuLog; -void disR5900F( std::string& output, u32 code, u32 pc); -void disR5900Fasm( std::string& output, u32 code, u32 pc); -char* disR3000Fasm(u32 code, u32 pc); +extern char* disR3000Fasm(u32 code, u32 pc); +extern char* disR3000AF(u32 code, u32 pc); -void disR5900AddSym(u32 addr, const char *name); -const char* disR5900GetSym(u32 addr); -const char* disR5900GetUpperSym(u32 addr); -void disR5900FreeSyms(); -void dFindSym( std::string& output, u32 addr ); +extern char* disVU0MicroUF(u32 code, u32 pc); +extern char* disVU0MicroLF(u32 code, u32 pc); +extern char* disVU1MicroUF(u32 code, u32 pc); +extern char* disVU1MicroLF(u32 code, u32 pc); -void strAppend( std::string& output, const char *fmt, ... ); +extern const char * const CP2VFnames[]; +extern const char * const disRNameCP2f[]; +extern const char * const disRNameCP2i[]; -char* disVU0MicroUF(u32 code, u32 pc); -char* disVU0MicroLF(u32 code, u32 pc); -char* disVU1MicroUF(u32 code, u32 pc); -char* disVU1MicroLF(u32 code, u32 pc); - -char* disR3000AF(u32 code, u32 pc); - -extern const char *CP2VFnames[]; -extern const char *disRNameCP2f[]; -extern const char *disRNameCP2i[]; - -// A helper class for getting a quick and efficient string representation of the -// R5900's current instruction. This class is *not* thread safe! -class DisR5900CurrentState +namespace R5900 { -protected: - std::string result; + // [TODO] : These function names can be de-obfuscated with the help of a little namespace love. -public: - const char* getString(); -}; + void disR5900F( std::string& output, u32 code, u32 pc); + void disR5900Fasm( std::string& output, u32 code, u32 pc); + void disR5900AddSym(u32 addr, const char *name); + const char* disR5900GetSym(u32 addr); + const char* disR5900GetUpperSym(u32 addr); + void disR5900FreeSyms(); + void dFindSym( std::string& output, u32 addr ); -extern DisR5900CurrentState disR5900Current; + extern const char * const disRNameGPR[]; + + // A helper class for getting a quick and efficient string representation of the + // R5900's current instruction. This class is *not* thread safe! + class DisR5900CurrentState + { + protected: + std::string result; + + public: + const std::string& getString(); + const char* getCString(); + }; + + extern DisR5900CurrentState disR5900Current; +} + +namespace R3000a +{ + extern const char * const disRNameGPR[]; +} -//that way is slower but you now not need to compile every time ;P #ifdef PCSX2_DEVBUILD extern u32 varLog; diff --git a/pcsx2/DebugTools/DisR3000A.cpp b/pcsx2/DebugTools/DisR3000A.cpp index 8a5b56b944..5bcc793281 100644 --- a/pcsx2/DebugTools/DisR3000A.cpp +++ b/pcsx2/DebugTools/DisR3000A.cpp @@ -23,18 +23,22 @@ static char ostr[1024]; // Names of registers -static const char *disRNameGPR[] = { - "r0", "at", "v0", "v1", "a0", "a1","a2", "a3", - "t0", "t1", "t2", "t3", "t4", "t5","t6", "t7", - "s0", "s1", "s2", "s3", "s4", "s5","s6", "s7", - "t8", "t9", "k0", "k1", "gp", "sp","fp", "ra"}; +namespace IOP +{ + const char * const disRNameGPR[] = { + "r0", "at", "v0", "v1", "a0", "a1","a2", "a3", + "t0", "t1", "t2", "t3", "t4", "t5","t6", "t7", + "s0", "s1", "s2", "s3", "s4", "s5","s6", "s7", + "t8", "t9", "k0", "k1", "gp", "sp","fp", "ra"}; -static const char *disRNameCP0[] = { - "Index" , "Random" , "EntryLo0", "EntryLo1", "Context" , "PageMask" , "Wired" , "*Check me*", - "BadVAddr" , "Count" , "EntryHi" , "Compare" , "Status" , "Cause" , "ExceptPC" , "PRevID" , - "Config" , "LLAddr" , "WatchLo" , "WatchHi" , "XContext", "*RES*" , "*RES*" , "*RES*" , - "*RES*" , "*RES* " , "PErr" , "CacheErr", "TagLo" , "TagHi" , "ErrorEPC" , "*RES*" }; + const char * const disRNameCP0[] = { + "Index" , "Random" , "EntryLo0", "EntryLo1", "Context" , "PageMask" , "Wired" , "*Check me*", + "BadVAddr" , "Count" , "EntryHi" , "Compare" , "Status" , "Cause" , "ExceptPC" , "PRevID" , + "Config" , "LLAddr" , "WatchLo" , "WatchHi" , "XContext", "*RES*" , "*RES*" , "*RES*" , + "*RES*" , "*RES* " , "PErr" , "CacheErr", "TagLo" , "TagHi" , "ErrorEPC" , "*RES*" }; +} +using namespace IOP; // Type definition of our functions diff --git a/pcsx2/DebugTools/DisR5900.cpp b/pcsx2/DebugTools/DisR5900.cpp index 6cff0510b6..1519dd71b4 100644 --- a/pcsx2/DebugTools/DisR5900.cpp +++ b/pcsx2/DebugTools/DisR5900.cpp @@ -24,46 +24,47 @@ using namespace std; #include "R5900.h" #include "VU.h" -//static char ostr[1024]; - -// Names of registers -const char *disRNameGPR[] = { - "r0", "at", "v0", "v1", "a0", "a1","a2", "a3", - "t0", "t1", "t2", "t3", "t4", "t5","t6", "t7", - "s0", "s1", "s2", "s3", "s4", "s5","s6", "s7", - "t8", "t9", "k0", "k1", "gp", "sp","fp", "ra", "hi", "lo"}; // lo,hi used in rec - -const char *disRNameCP0[] = { - "Index" , "Random" , "EntryLo0" , "EntryLo1", "Context" , "PageMask" , "Wired" , "*RES*", - "BadVAddr" , "Count" , "EntryHi" , "Compare" , "Status" , "Cause" , "ExceptPC" , "PRevID", - "Config" , "LLAddr" , "WatchLo" , "WatchHi" , "*RES*" , "*RES*" , "*RES*" , "Debug", - "DEPC" , "PerfCnt" , "ErrCtl" , "CacheErr", "TagLo" , "TagHi" , "ErrorEPC" , "DESAVE"}; - -const char *disRNameCP1[] = { - "FPR0" , "FPR1" , "FPR2" , "FPR3" , "FPR4" , "FPR5" , "FPR6" , "FPR7", - "FPR8" , "FPR9" , "FPR10", "FPR11", "FPR12", "FPR13", "FPR14", "FPR15", - "FPR16", "FPR17", "FPR18", "FPR19", "FPR20", "FPR21", "FPR22", "FPR23", - "FPR24", "FPR25", "FPR26", "FPR27", "FPR28", "FPR29", "FPR30", "FPR31"}; - -const char *disRNameCP1c[] = { - "FRevID", "*RES*", "*RES*", "*RES*", "*RES*", "*RES*", "*RES*", "*RES*", - "*RES*", "*RES*", "*RES*", "*RES*", "*RES*", "*RES*", "*RES*", "*RES*", - "*RES*", "*RES*", "*RES*", "*RES*", "*RES*", "*RES*", "*RES*", "*RES*", - "*RES*", "*RES*", "*RES*", "*RES*", "*RES*", "*RES*", "*RES*", "FStatus"}; - -const char *disRNameCP2f[] = { +static const char * const disRNameCP2f[] = { "VF00", "VF01", "VF02", "VF03", "VF04", "VF05", "VF06", "VF07", "VF08", "VF09", "VF10", "VF11", "VF12", "VF13", "VF14", "VF15", "VF16", "VF17", "VF18", "VF19", "VF20", "VF21", "VF22", "VF23", "VF24", "VF25", "VF26", "VF27", "VF28", "VF29", "VF30", "VF31"}; -const char *disRNameCP2i[] = { +static const char * const disRNameCP2i[] = { "VI00", "VI01", "VI02", "VI03", "VI04", "VI05", "VI06", "VI07", "VI08", "VI09", "VI10", "VI11", "VI12", "VI13", "VI14", "VI15", "Status", "MAC", "Clip", "*RES*", "R", "I", "Q", "*RES*", "*RES*", "*RES*", "TPC", "CMSAR0", "FBRST", "VPU-STAT", "*RES*", "CMSAR1"}; -const char *CP2VFnames[] = { "x", "y", "z", "w" }; +static const char * const CP2VFnames[] = { "x", "y", "z", "w" }; + +namespace R5900 +{ + +// Names of registers +const char * const disRNameGPR[] = { + "r0", "at", "v0", "v1", "a0", "a1","a2", "a3", + "t0", "t1", "t2", "t3", "t4", "t5","t6", "t7", + "s0", "s1", "s2", "s3", "s4", "s5","s6", "s7", + "t8", "t9", "k0", "k1", "gp", "sp","fp", "ra", "hi", "lo"}; // lo,hi used in rec + +const char * const disRNameCP0[] = { + "Index" , "Random" , "EntryLo0" , "EntryLo1", "Context" , "PageMask" , "Wired" , "*RES*", + "BadVAddr" , "Count" , "EntryHi" , "Compare" , "Status" , "Cause" , "ExceptPC" , "PRevID", + "Config" , "LLAddr" , "WatchLo" , "WatchHi" , "*RES*" , "*RES*" , "*RES*" , "Debug", + "DEPC" , "PerfCnt" , "ErrCtl" , "CacheErr", "TagLo" , "TagHi" , "ErrorEPC" , "DESAVE"}; + +static const char * const disRNameCP1[] = { + "FPR0" , "FPR1" , "FPR2" , "FPR3" , "FPR4" , "FPR5" , "FPR6" , "FPR7", + "FPR8" , "FPR9" , "FPR10", "FPR11", "FPR12", "FPR13", "FPR14", "FPR15", + "FPR16", "FPR17", "FPR18", "FPR19", "FPR20", "FPR21", "FPR22", "FPR23", + "FPR24", "FPR25", "FPR26", "FPR27", "FPR28", "FPR29", "FPR30", "FPR31"}; + +static const char * const disRNameCP1c[] = { + "FRevID", "*RES*", "*RES*", "*RES*", "*RES*", "*RES*", "*RES*", "*RES*", + "*RES*", "*RES*", "*RES*", "*RES*", "*RES*", "*RES*", "*RES*", "*RES*", + "*RES*", "*RES*", "*RES*", "*RES*", "*RES*", "*RES*", "*RES*", "*RES*", + "*RES*", "*RES*", "*RES*", "*RES*", "*RES*", "*RES*", "*RES*", "FStatus"}; // Type definition of our functions #define DisFInterface (string& output, u32 code, u32 pc) @@ -130,38 +131,42 @@ typedef void (*TdisR5900F)DisFInterface; #define _Fsf_ ((code >> 21) & 0x03) #define _Ftf_ ((code >> 23) & 0x03) -#define dName(i) strAppend(output, "%-7s,", i); -#define dGPR128(i) strAppend(output, "%8.8x_%8.8x_%8.8x_%8.8x (%s),", cpuRegs.GPR.r[i].UL[3], cpuRegs.GPR.r[i].UL[2], cpuRegs.GPR.r[i].UL[1], cpuRegs.GPR.r[i].UL[0], disRNameGPR[i]) -#define dGPR64(i) strAppend(output, "%8.8x_%8.8x (%s),", cpuRegs.GPR.r[i].UL[1], cpuRegs.GPR.r[i].UL[0], disRNameGPR[i]) -#define dGPR64U(i) strAppend(output, "%8.8x_%8.8x (%s),", cpuRegs.GPR.r[i].UL[3], cpuRegs.GPR.r[i].UL[2], disRNameGPR[i]) -#define dGPR32(i) strAppend(output, "%8.8x (%s),", cpuRegs.GPR.r[i].UL[0], disRNameGPR[i]) +// sap! it stands for string append. It's not a friendly name but for now it makes +// the copy-paste marathon of code below more readable! +#define _sap( str ) ssappendf( output, str, params -#define dCP032(i) strAppend(output, "%8.8x (%s),", cpuRegs.CP0.r[i], disRNameCP0[i]) +#define dName(i) _sap("%-7s,") i); +#define dGPR128(i) _sap("%8.8x_%8.8x_%8.8x_%8.8x (%s),") cpuRegs.GPR.r[i].UL[3], cpuRegs.GPR.r[i].UL[2], cpuRegs.GPR.r[i].UL[1], cpuRegs.GPR.r[i].UL[0], disRNameGPR[i]) +#define dGPR64(i) _sap("%8.8x_%8.8x (%s),") cpuRegs.GPR.r[i].UL[1], cpuRegs.GPR.r[i].UL[0], disRNameGPR[i]) +#define dGPR64U(i) _sap("%8.8x_%8.8x (%s),") cpuRegs.GPR.r[i].UL[3], cpuRegs.GPR.r[i].UL[2], disRNameGPR[i]) +#define dGPR32(i) _sap("%8.8x (%s),") cpuRegs.GPR.r[i].UL[0], disRNameGPR[i]) -#define dCP132(i) strAppend(output, "%f (%s),", fpuRegs.fpr[i].f, disRNameCP1[i]) -#define dCP1c32(i) strAppend(output, "%8.8x (%s),", fpuRegs.fprc[i], disRNameCP1c[i]) -#define dCP1acc() strAppend(output, "%f (ACC),", fpuRegs.ACC.f) +#define dCP032(i) _sap("%8.8x (%s),") cpuRegs.CP0.r[i], disRNameCP0[i]) -#define dCP2128f(i) strAppend(output, "w=%f z=%f y=%f x=%f (%s),", VU0.VF[i].f.w, VU0.VF[i].f.z, VU0.VF[i].f.y, VU0.VF[i].f.x, disRNameCP2f[i]) -#define dCP232x(i) strAppend(output, "x=%f (%s),", VU0.VF[i].f.x, disRNameCP2f[i]) -#define dCP232y(i) strAppend(output, "y=%f (%s),", VU0.VF[i].f.y, disRNameCP2f[i]) -#define dCP232z(i) strAppend(output, "z=%f (%s),", VU0.VF[i].f.z, disRNameCP2f[i]) -#define dCP232w(i) strAppend(output, "w=%f (%s),", VU0.VF[i].f.w, disRNameCP2f[i]) -#define dCP2ACCf() strAppend(output, "w=%f z=%f y=%f x=%f (ACC),", VU0.ACC.f.w, VU0.ACC.f.z, VU0.ACC.f.y, VU0.ACC.f.x) -#define dCP232i(i) strAppend(output, "%8.8x (%s),", VU0.VI[i].UL, disRNameCP2i[i]) -#define dCP232iF(i) strAppend(output, "%f (%s),", VU0.VI[i].F, disRNameCP2i[i]) -#define dCP232f(i, j) strAppend(output, "Q %s=%f (%s),", CP2VFnames[j], VU0.VF[i].F[j], disRNameCP2f[i]) +#define dCP132(i) _sap("%f (%s),") fpuRegs.fpr[i].f, disRNameCP1[i]) +#define dCP1c32(i) _sap("%8.8x (%s),") fpuRegs.fprc[i], disRNameCP1c[i]) +#define dCP1acc() _sap("%f (ACC),") fpuRegs.ACC.f) -#define dHI64() strAppend(output, "%8.8x_%8.8x (%s),", cpuRegs.HI.UL[1], cpuRegs.HI.UL[0], "hi") -#define dLO64() strAppend(output, "%8.8x_%8.8x (%s),", cpuRegs.LO.UL[1], cpuRegs.LO.UL[0], "lo") -#define dImm() strAppend(output, "%4.4x (%d),", _Im_, _Im_) -#define dTarget() strAppend(output, "%8.8x,", _Target_) -#define dSa() strAppend(output, "%2.2x (%d),", _Sa_, _Sa_) -#define dSa32() strAppend(output, "%2.2x (%d),", _Sa_+32, _Sa_+32) -#define dOfB() strAppend(output, "%4.4x (%8.8x (%s)),", _Im_, cpuRegs.GPR.r[_Rs_].UL[0], disRNameGPR[_Rs_]) -#define dOffset() strAppend(output, "%8.8x,", _Branch_) -#define dCode() strAppend(output, "%8.8x,", (code >> 6) & 0xffffff) -#define dSaR() strAppend(output, "%8.8x,", cpuRegs.sa) +#define dCP2128f(i) _sap("w=%f z=%f y=%f x=%f (%s),") VU0.VF[i].f.w, VU0.VF[i].f.z, VU0.VF[i].f.y, VU0.VF[i].f.x, disRNameCP2f[i]) +#define dCP232x(i) _sap("x=%f (%s),") VU0.VF[i].f.x, disRNameCP2f[i]) +#define dCP232y(i) _sap("y=%f (%s),") VU0.VF[i].f.y, disRNameCP2f[i]) +#define dCP232z(i) _sap("z=%f (%s),") VU0.VF[i].f.z, disRNameCP2f[i]) +#define dCP232w(i) _sap("w=%f (%s),") VU0.VF[i].f.w, disRNameCP2f[i]) +#define dCP2ACCf() _sap("w=%f z=%f y=%f x=%f (ACC),") VU0.ACC.f.w, VU0.ACC.f.z, VU0.ACC.f.y, VU0.ACC.f.x) +#define dCP232i(i) _sap("%8.8x (%s),") VU0.VI[i].UL, disRNameCP2i[i]) +#define dCP232iF(i) _sap("%f (%s),") VU0.VI[i].F, disRNameCP2i[i]) +#define dCP232f(i, j) _sap("Q %s=%f (%s),") CP2VFnames[j], VU0.VF[i].F[j], disRNameCP2f[i]) + +#define dHI64() _sap("%8.8x_%8.8x (%s),") cpuRegs.HI.UL[1], cpuRegs.HI.UL[0], "hi") +#define dLO64() _sap("%8.8x_%8.8x (%s),") cpuRegs.LO.UL[1], cpuRegs.LO.UL[0], "lo") +#define dImm() _sap("%4.4x (%d),") _Im_, _Im_) +#define dTarget() _sap("%8.8x,") _Target_) +#define dSa() _sap("%2.2x (%d),") _Sa_, _Sa_) +#define dSa32() _sap("%2.2x (%d),") _Sa_+32, _Sa_+32) +#define dOfB() _sap("%4.4x (%8.8x (%s)),") _Im_, cpuRegs.GPR.r[_Rs_].UL[0], disRNameGPR[_Rs_]) +#define dOffset() _sap("%8.8x,") _Branch_) +#define dCode() _sap("%8.8x,") (code >> 6) & 0xffffff) +#define dSaR() _sap("%8.8x,") cpuRegs.sa) struct sSymbol { u32 addr; @@ -1010,10 +1015,20 @@ MakeDisF(disR5900F, disR5900[code >> 26] DisFInterfaceN) // returns a string representation of the cpuRegs current instruction. // The return value of this method is *not* thread safe! -const char* DisR5900CurrentState::getString() +const string& DisR5900CurrentState::getString() { + result.clear(); + disR5900F( result, cpuRegs.code, cpuRegs.pc ); + return result; +} + +const char* DisR5900CurrentState::getCString() +{ + result.clear(); disR5900F( result, cpuRegs.code, cpuRegs.pc ); return result.c_str(); } -DisR5900CurrentState disR5900Current; \ No newline at end of file +DisR5900CurrentState disR5900Current; + +} \ No newline at end of file diff --git a/pcsx2/DebugTools/DisR5900asm.cpp b/pcsx2/DebugTools/DisR5900asm.cpp index 81bf0e71fa..ebe4a4bcc4 100644 --- a/pcsx2/DebugTools/DisR5900asm.cpp +++ b/pcsx2/DebugTools/DisR5900asm.cpp @@ -31,6 +31,9 @@ unsigned long opcode_addr; using namespace std; +namespace R5900 +{ + /* //DECODE PROCUDURES @@ -55,13 +58,13 @@ using namespace std; #define DECODE_C2BC ((cpuRegs.code >> 16) & 0x03) */ /*************************CPUS REGISTERS**************************/ -const char *GPR_REG[32] = { +static const char * const GPR_REG[32] = { "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", "t8", "t9", "k0", "k1", "gp", "sp", "fp", "ra" }; -const char *COP0_REG[32] ={ +static const char * const COP0_REG[32] ={ "Index","Random","EntryLo0","EntryLo1","Context","PageMask", "Wired","C0r7","BadVaddr","Count","EntryHi","Compare","Status", "Cause","EPC","PRId","Config","C0r17","C0r18","C0r19","C0r20", @@ -69,14 +72,14 @@ const char *COP0_REG[32] ={ "TagHi","ErrorPC","C0r31" }; //floating point cop1 Floating point reg -const char *COP1_REG_FP[32] ={ +static const char * const COP1_REG_FP[32] ={ "f00","f01","f02","f03","f04","f05","f06","f07", "f08","f09","f10","f11","f12","f13","f14","f15", "f16","f17","f18","f19","f20","f21","f21","f23", "f24","f25","f26","f27","f28","f29","f30","f31" }; //floating point cop1 control registers -const char *COP1_REG_FCR[32] ={ +static const char * const COP1_REG_FCR[32] ={ "fcr00","fcr01","fcr02","fcr03","fcr04","fcr05","fcr06","fcr07", "fcr08","fcr09","fcr10","fcr11","fcr12","fcr13","fcr14","fcr15", "fcr16","fcr17","fcr18","fcr19","fcr20","fcr21","fcr21","fcr23", @@ -84,7 +87,7 @@ const char *COP1_REG_FCR[32] ={ }; //floating point cop2 reg -const char *COP2_REG_FP[32] ={ +static const char * const COP2_REG_FP[32] ={ "vf00","vf01","vf02","vf03","vf04","vf05","vf06","vf07", "vf08","vf09","vf10","vf11","vf12","vf13","vf14","vf15", "vf16","vf17","vf18","vf19","vf20","vf21","vf21","vf23", @@ -92,82 +95,18 @@ const char *COP2_REG_FP[32] ={ }; //cop2 control registers -const char *COP2_REG_CTL[32] ={ +static const char * const COP2_REG_CTL[32] ={ "vi00","vi01","vi02","vi03","vi04","vi05","vi06","vi07", "vi08","vi09","vi10","vi11","vi12","vi13","vi14","vi15", "Status","MACflag","ClipFlag","c2c19","R","I","Q","c2c23", "c2c24","c2c25","TPC","CMSAR0","FBRST","VPU-STAT","c2c30","CMSAR1" }; -void P_COP0_Unknown( string& output ); -void P_COP0_BC0( string& output ); -void P_COP0_Func( string& output ); -void P_COP1_BC1( string& output ); -void P_COP1_S( string& output ); -void P_COP1_W( string& output ); -void P_COP1_Unknown( string& output ); -void P_COP2_BC2( string& output ); -void P_COP2_SPECIAL( string& output ); void P_COP2_Unknown( string& output ); void P_COP2_SPECIAL2( string& output ); +void P_COP2_SPECIAL( string& output ); +void P_COP2_BC2( string& output ); -//**************************************************************************** -//** COP0 ** -//**************************************************************************** -void P_MFC0( string& output ); -void P_MTC0( string& output ); -void P_BC0F( string& output ); -void P_BC0T( string& output ); -void P_BC0FL( string& output ); -void P_BC0TL( string& output ); -void P_TLBR( string& output ); -void P_TLBWI( string& output ); -void P_TLBWR( string& output ); -void P_TLBP( string& output ); -void P_ERET( string& output ); -void P_DI( string& output ); -void P_EI( string& output ); -//**************************************************************************** -//** END OF COP0 ** -//**************************************************************************** -//**************************************************************************** -//** COP1 - Floating Point Unit (FPU) ** -//**************************************************************************** -void P_MFC1( string& output ); -void P_CFC1( string& output ); -void P_MTC1( string& output ); -void P_CTC1( string& output ); -void P_BC1F( string& output ); -void P_BC1T( string& output ); -void P_BC1FL( string& output ); -void P_BC1TL( string& output ); -void P_ADD_S( string& output ); -void P_SUB_S( string& output ); -void P_MUL_S( string& output ); -void P_DIV_S( string& output ); -void P_SQRT_S( string& output ); -void P_ABS_S( string& output ); -void P_MOV_S( string& output ); -void P_NEG_S( string& output ); -void P_RSQRT_S( string& output ); -void P_ADDA_S( string& output ); -void P_SUBA_S( string& output ); -void P_MULA_S( string& output ); -void P_MADD_S( string& output ); -void P_MSUB_S( string& output ); -void P_MADDA_S( string& output ); -void P_MSUBA_S( string& output ); -void P_CVT_W( string& output ); -void P_MAX_S( string& output ); -void P_MIN_S( string& output ); -void P_C_F( string& output ); -void P_C_EQ( string& output ); -void P_C_LT( string& output ); -void P_C_LE( string& output ); - void P_CVT_S( string& output ); -//**************************************************************************** -//** END OF COP1 ** -//**************************************************************************** //**************************************************************************** //** COP2 - (VU0) ** //**************************************************************************** @@ -459,12 +398,6 @@ void P_VRXOR( string& output ); hi |-------|-------|-------|-------|-------|-------|-------|-------| *1=BC See BC0 list *2 = TLB instr, see TLB list */ -void (*COP0PrintTable[32])( string& output ) = { - P_MFC0, P_COP0_Unknown, P_COP0_Unknown, P_COP0_Unknown, P_MTC0, P_COP0_Unknown, P_COP0_Unknown, P_COP0_Unknown, - P_COP0_BC0, P_COP0_Unknown, P_COP0_Unknown, P_COP0_Unknown, P_COP0_Unknown, P_COP0_Unknown, P_COP0_Unknown, P_COP0_Unknown, - P_COP0_Func, P_COP0_Unknown, P_COP0_Unknown, P_COP0_Unknown, P_COP0_Unknown, P_COP0_Unknown, P_COP0_Unknown, P_COP0_Unknown, - P_COP0_Unknown, P_COP0_Unknown, P_COP0_Unknown, P_COP0_Unknown, P_COP0_Unknown, P_COP0_Unknown, P_COP0_Unknown, P_COP0_Unknown, -}; /* BC0: Instructions encoded by the rt field when opcode = COP0 & rs field=BC0 31--------26-25------21 ----------------------------------------0 @@ -477,12 +410,6 @@ void (*COP0PrintTable[32])( string& output ) = { 11 | --- | --- | --- | --- | --- | --- | --- | --- | hi |-------|-------|-------|-------|-------|-------|-------|-------| */ -void (*COP0BC0PrintTable[32])( string& output ) = { - P_BC0F, P_BC0T, P_BC0FL, P_BC0TL, P_COP0_Unknown, P_COP0_Unknown, P_COP0_Unknown, P_COP0_Unknown, - P_COP0_Unknown, P_COP0_Unknown, P_COP0_Unknown, P_COP0_Unknown, P_COP0_Unknown, P_COP0_Unknown, P_COP0_Unknown, P_COP0_Unknown, - P_COP0_Unknown, P_COP0_Unknown, P_COP0_Unknown, P_COP0_Unknown, P_COP0_Unknown, P_COP0_Unknown, P_COP0_Unknown, P_COP0_Unknown, - P_COP0_Unknown, P_COP0_Unknown, P_COP0_Unknown, P_COP0_Unknown, P_COP0_Unknown, P_COP0_Unknown, P_COP0_Unknown, P_COP0_Unknown, -}; /* C0=Instructions encode by function field when Opcode field=COP0 & rs field=C0 31---------26------------------------------------------5--------0 @@ -499,16 +426,6 @@ void (*COP0BC0PrintTable[32])( string& output ) = { 111 | EI | DI | --- | --- | --- | --- | --- | --- | hi |-------|-------|-------|-------|-------|-------|-------|-------| */ -void (*COP0C0PrintTable[64])( string& output ) = { - P_COP0_Unknown, P_TLBR, P_TLBWI, P_COP0_Unknown, P_COP0_Unknown, P_COP0_Unknown, P_TLBWR, P_COP0_Unknown, - P_TLBP, P_COP0_Unknown, P_COP0_Unknown, P_COP0_Unknown, P_COP0_Unknown, P_COP0_Unknown, P_COP0_Unknown, P_COP0_Unknown, - P_COP0_Unknown, P_COP0_Unknown, P_COP0_Unknown, P_COP0_Unknown, P_COP0_Unknown, P_COP0_Unknown, P_COP0_Unknown, P_COP0_Unknown, - P_ERET, P_COP0_Unknown, P_COP0_Unknown, P_COP0_Unknown, P_COP0_Unknown, P_COP0_Unknown, P_COP0_Unknown, P_COP0_Unknown, - P_COP0_Unknown, P_COP0_Unknown, P_COP0_Unknown, P_COP0_Unknown, P_COP0_Unknown, P_COP0_Unknown, P_COP0_Unknown, P_COP0_Unknown, - P_COP0_Unknown, P_COP0_Unknown, P_COP0_Unknown, P_COP0_Unknown, P_COP0_Unknown, P_COP0_Unknown, P_COP0_Unknown, P_COP0_Unknown, - P_COP0_Unknown, P_COP0_Unknown, P_COP0_Unknown, P_COP0_Unknown, P_COP0_Unknown, P_COP0_Unknown, P_COP0_Unknown, P_COP0_Unknown, - P_EI, P_DI, P_COP0_Unknown, P_COP0_Unknown, P_COP0_Unknown, P_COP0_Unknown, P_COP0_Unknown, P_COP0_Unknown -}; /* COP1: Instructions encoded by the fmt field when opcode = COP1. 31--------26-25------21 ----------------------------------------0 @@ -523,12 +440,6 @@ void (*COP0C0PrintTable[64])( string& output ) = { *1 = BC instructions, see BC1 list *2 = S instr, see FPU list *3 = W instr, see FPU list */ -void (*COP1PrintTable[32])( string& output ) = { - P_MFC1, P_COP1_Unknown, P_CFC1, P_COP1_Unknown, P_MTC1, P_COP1_Unknown, P_CTC1, P_COP1_Unknown, - P_COP1_BC1, P_COP1_Unknown, P_COP1_Unknown, P_COP1_Unknown, P_COP1_Unknown, P_COP1_Unknown, P_COP1_Unknown, P_COP1_Unknown, - P_COP1_S, P_COP1_Unknown, P_COP1_Unknown, P_COP1_Unknown, P_COP1_W, P_COP1_Unknown, P_COP1_Unknown, P_COP1_Unknown, - P_COP1_Unknown, P_COP1_Unknown, P_COP1_Unknown, P_COP1_Unknown, P_COP1_Unknown, P_COP1_Unknown, P_COP1_Unknown, P_COP1_Unknown, -}; /* BC1: Instructions encoded by the rt field when opcode = COP1 & rs field=BC1 31--------26-25------21 ----------------------------------------0 @@ -541,12 +452,6 @@ void (*COP1PrintTable[32])( string& output ) = { 11 | --- | --- | --- | --- | --- | --- | --- | --- | hi |-------|-------|-------|-------|-------|-------|-------|-------| */ -void (*COP1BC1PrintTable[32])( string& output ) = { - P_BC1F, P_BC1T, P_BC1FL, P_BC1TL, P_COP1_Unknown, P_COP1_Unknown, P_COP1_Unknown, P_COP1_Unknown, - P_COP1_Unknown, P_COP1_Unknown, P_COP1_Unknown, P_COP1_Unknown, P_COP1_Unknown, P_COP1_Unknown, P_COP1_Unknown, P_COP1_Unknown, - P_COP1_Unknown, P_COP1_Unknown, P_COP1_Unknown, P_COP1_Unknown, P_COP1_Unknown, P_COP1_Unknown, P_COP1_Unknown, P_COP1_Unknown, - P_COP1_Unknown, P_COP1_Unknown, P_COP1_Unknown, P_COP1_Unknown, P_COP1_Unknown, P_COP1_Unknown, P_COP1_Unknown, P_COP1_Unknown, -}; /* FPU: Instructions encoded by the function field when opcode = COP1 and rs = S @@ -564,16 +469,6 @@ void (*COP1BC1PrintTable[32])( string& output ) = { 111 | --- | --- | --- | --- | --- | --- | --- | --- | hi |-------|-------|-------|-------|-------|-------|-------|-------| */ -void (*COP1SPrintTable[64])( string& output ) = { -P_ADD_S, P_SUB_S, P_MUL_S, P_DIV_S, P_SQRT_S, P_ABS_S, P_MOV_S, P_NEG_S, -P_COP1_Unknown,P_COP1_Unknown,P_COP1_Unknown,P_COP1_Unknown,P_COP1_Unknown,P_COP1_Unknown,P_COP1_Unknown,P_COP1_Unknown, -P_COP1_Unknown,P_COP1_Unknown,P_COP1_Unknown,P_COP1_Unknown,P_COP1_Unknown,P_COP1_Unknown,P_RSQRT_S, P_COP1_Unknown, -P_ADDA_S, P_SUBA_S, P_MULA_S, P_COP1_Unknown,P_MADD_S, P_MSUB_S, P_MADDA_S, P_MSUBA_S, -P_COP1_Unknown,P_COP1_Unknown,P_COP1_Unknown,P_COP1_Unknown,P_CVT_W, P_COP1_Unknown,P_COP1_Unknown,P_COP1_Unknown, -P_MAX_S, P_MIN_S, P_COP1_Unknown,P_COP1_Unknown,P_COP1_Unknown,P_COP1_Unknown,P_COP1_Unknown,P_COP1_Unknown, -P_C_F, P_COP1_Unknown,P_C_EQ, P_COP1_Unknown,P_C_LT, P_COP1_Unknown,P_C_LE, P_COP1_Unknown, -P_COP1_Unknown,P_COP1_Unknown,P_COP1_Unknown,P_COP1_Unknown,P_COP1_Unknown,P_COP1_Unknown,P_COP1_Unknown,P_COP1_Unknown, -}; /* FPU: Instructions encoded by the function field when opcode = COP1 and rs = W @@ -591,19 +486,9 @@ P_COP1_Unknown,P_COP1_Unknown,P_COP1_Unknown,P_COP1_Unknown,P_COP1_Unknown,P_COP 111 | --- | --- | --- | --- | --- | --- | --- | --- | hi |-------|-------|-------|-------|-------|-------|-------|-------| */ -void (*COP1WPrintTable[64])( string& output ) = { -P_COP1_Unknown,P_COP1_Unknown,P_COP1_Unknown,P_COP1_Unknown,P_COP1_Unknown,P_COP1_Unknown,P_COP1_Unknown,P_COP1_Unknown, -P_COP1_Unknown,P_COP1_Unknown,P_COP1_Unknown,P_COP1_Unknown,P_COP1_Unknown,P_COP1_Unknown,P_COP1_Unknown,P_COP1_Unknown, -P_COP1_Unknown,P_COP1_Unknown,P_COP1_Unknown,P_COP1_Unknown,P_COP1_Unknown,P_COP1_Unknown,P_COP1_Unknown,P_COP1_Unknown, -P_COP1_Unknown,P_COP1_Unknown,P_COP1_Unknown,P_COP1_Unknown,P_COP1_Unknown,P_COP1_Unknown,P_COP1_Unknown,P_COP1_Unknown, -P_CVT_S, P_COP1_Unknown,P_COP1_Unknown,P_COP1_Unknown,P_COP1_Unknown,P_COP1_Unknown,P_COP1_Unknown,P_COP1_Unknown, -P_COP1_Unknown,P_COP1_Unknown,P_COP1_Unknown,P_COP1_Unknown,P_COP1_Unknown,P_COP1_Unknown,P_COP1_Unknown,P_COP1_Unknown, -P_COP1_Unknown,P_COP1_Unknown,P_COP1_Unknown,P_COP1_Unknown,P_COP1_Unknown,P_COP1_Unknown,P_COP1_Unknown,P_COP1_Unknown, -P_COP1_Unknown,P_COP1_Unknown,P_COP1_Unknown,P_COP1_Unknown,P_COP1_Unknown,P_COP1_Unknown,P_COP1_Unknown,P_COP1_Unknown, -}; //************************************************************* -//COP2 TABLES :) +// COP2 TABLES :) [VU0 as a Co-Processor to the EE] //************************************************************* /* COP2: Instructions encoded by the fmt field when opcode = COP2. @@ -732,38 +617,11 @@ void disR5900Fasm(string& output, u32 code, u32 pc) sprintf(obuf, "%08X:\t", pc ); output.assign( obuf ); - EE::OpcodeTables::Standard[(code) >> 26].decode( output ); + R5900::OpcodeTables::tbl_Standard[(code) >> 26].disasm( output ); cpuRegs.code = scode; } -//***********COP0 TABLE CALLS******************************** - -void P_COP0_BC0( string& output ) -{ - COP0BC0PrintTable[DECODE_C0BC]( output ); -} -void P_COP0_Func( string& output ) -{ - COP0C0PrintTable[DECODE_FUNCTION]( output ); -} - -//****************END OF MMI TABLES CALLS********************** -//COP1 TABLECALLS******************************************* -void P_COP1_BC1( string& output ) -{ - COP1BC1PrintTable[DECODE_C1BC]( output ); -} -void P_COP1_S( string& output ) -{ - COP1SPrintTable[DECODE_FUNCTION]( output ); -} -void P_COP1_W( string& output ) -{ - COP1WPrintTable[DECODE_FUNCTION]( output ); -} -//**********************END OF COP1 TABLE CALLS - //************************************************************* //************************COP2********************************** void P_COP2_BC2( string& output ) @@ -780,70 +638,46 @@ void P_COP2_SPECIAL2( string& output ) } //**************************UNKNOWN**************************** -void P_COP0_Unknown( string& output ) -{ - output.append( "COP0 ??" ); -} -void P_COP1_Unknown( string& output ) -{ - output.append( "COP1 ??" ); -} void P_COP2_Unknown( string& output ) { - output.append( "COP2 ??" ); + output += "COP2 ??"; } - //************************************************************* //*****************SOME DECODE STUFF*************************** + +void label_decode( string& output, u32 addr ) +{ + string buf; + ssprintf(buf, "0x%08X",params addr); + const char* label = disR5900GetSym( addr ); + + if( label != NULL ) + { + output += label; + output += ' '; + } + + output += buf; +} + void jump_decode( string& output ) { - char buf[256]; - u32 addr; - addr = DECODE_JUMP; - sprintf(buf, "0x%08X", addr); - dFindSym( output, addr ); - output.append( buf ); + label_decode( output, DECODE_JUMP ); } void offset_decode( string& output ) { - char buf[256]; - u32 addr; - addr = DECODE_OFFSET; - sprintf(buf, "0x%08X", addr); - dFindSym( output, addr ); - output.append( buf ); + label_decode( output, DECODE_OFFSET ); } //*********************END OF DECODE ROUTINES****************** -void strAppend( string& output, const char *fmt, ... ) -{ - va_list list; - char tmp[512]; - - va_start(list, fmt); - vsprintf(tmp, fmt, list); - output.append( tmp ); - va_end(list); -} - - -namespace EE { namespace Debug { namespace OpcodePrint +namespace OpcodeDisasm { -// ********** VariousCOP TABLE CALLS ********** -void COP0( string& output ) -{ - COP0PrintTable[DECODE_RS]( output ); -} -void COP1( string& output ) -{ - COP1PrintTable[DECODE_RS]( output ); -} void COP2( string& output ) { COP2PrintTable[DECODE_RS]( output ); @@ -852,338 +686,353 @@ void COP2( string& output ) // Unkown Opcode! void Unknown( string& output ) { - output.append( "?????" ); + output += "?????"; } void MMI_Unknown( string& output ) { - output.append( "MMI ??" ); + output += "MMI ??"; } +void COP0_Unknown( string& output ) +{ + output += "COP0 ??"; +} + +void COP1_Unknown( string& output ) +{ + output += "FPU ??"; +} + +// sap! it stands for string append. It's not a friendly name but for now it makes +// the copy-paste marathon of code below more readable! +#define _sap( str ) ssappendf( output, str, params + //********************* Standard Opcodes*********************** -void J( string& output ) { output.append("j\t" ); jump_decode(output);} -void JAL( string& output ) { output.append("jal\t" ); jump_decode(output);} -void BEQ( string& output ) { strAppend(output, "beq\t%s, %s, ", GPR_REG[DECODE_RS], GPR_REG[DECODE_RT]); offset_decode(output); } -void BNE( string& output ) { strAppend(output, "bne\t%s, %s, ", GPR_REG[DECODE_RS], GPR_REG[DECODE_RT]); offset_decode(output); } -void BLEZ( string& output ) { strAppend(output, "blez\t%s, ", GPR_REG[DECODE_RS]); offset_decode(output); } -void BGTZ( string& output ) { strAppend(output, "bgtz\t%s, ", GPR_REG[DECODE_RS]); offset_decode(output); } -void ADDI( string& output ) { strAppend(output, "addi\t%s, %s, 0x%04X", GPR_REG[DECODE_RT], GPR_REG[DECODE_RS], DECODE_IMMED);} -void ADDIU( string& output ) { strAppend(output, "addiu\t%s, %s, 0x%04X", GPR_REG[DECODE_RT], GPR_REG[DECODE_RS], DECODE_IMMED);} -void SLTI( string& output ) { strAppend(output, "slti\t%s, %s, 0x%04X", GPR_REG[DECODE_RT], GPR_REG[DECODE_RS], DECODE_IMMED); } -void SLTIU( string& output ) { strAppend(output, "sltiu\t%s, %s, 0x%04X", GPR_REG[DECODE_RT], GPR_REG[DECODE_RS], DECODE_IMMED); } -void ANDI( string& output ) { strAppend(output, "andi\t%s, %s, 0x%04X", GPR_REG[DECODE_RT], GPR_REG[DECODE_RS], DECODE_IMMED);} -void ORI( string& output ) { strAppend(output, "ori\t%s, %s, 0x%04X", GPR_REG[DECODE_RT], GPR_REG[DECODE_RS], DECODE_IMMED); } -void XORI( string& output ) { strAppend(output, "xori\t%s, %s, 0x%04X", GPR_REG[DECODE_RT], GPR_REG[DECODE_RS], DECODE_IMMED); } -void LUI( string& output ) { strAppend(output, "lui\t%s, 0x%04X", GPR_REG[DECODE_RT], DECODE_IMMED); } -void BEQL( string& output ) { strAppend(output, "beql\t%s, %s, %s", GPR_REG[DECODE_RS], GPR_REG[DECODE_RT]); offset_decode(output); } -void BNEL( string& output ) { strAppend(output, "bnel\t%s, %s, %s", GPR_REG[DECODE_RS], GPR_REG[DECODE_RT]); offset_decode(output); } -void BLEZL( string& output ) { strAppend(output, "blezl\t%s, ", GPR_REG[DECODE_RS]); offset_decode(output); } -void BGTZL( string& output ) { strAppend(output, "bgtzl\t%s, ", GPR_REG[DECODE_RS]); offset_decode(output); } -void DADDI( string& output ) { strAppend(output, "daddi\t%s, %s, 0x%04X", GPR_REG[DECODE_RT], GPR_REG[DECODE_RS], DECODE_IMMED); } -void DADDIU( string& output ) { strAppend(output, "daddiu\t%s, %s, 0x%04X", GPR_REG[DECODE_RT], GPR_REG[DECODE_RS], DECODE_IMMED); } -void LDL( string& output ) { strAppend(output, "ldl\t%s, 0x%04X(%s)", GPR_REG[DECODE_RT], DECODE_IMMED, GPR_REG[DECODE_RS]); } -void LDR( string& output ) { strAppend(output, "ldr\t%s, 0x%04X(%s)", GPR_REG[DECODE_RT], DECODE_IMMED, GPR_REG[DECODE_RS]); } -void LB( string& output ) { strAppend(output, "lb\t%s, 0x%04X(%s)", GPR_REG[DECODE_RT], DECODE_IMMED, GPR_REG[DECODE_RS]); } -void LH( string& output ) { strAppend(output, "lh\t%s, 0x%04X(%s)", GPR_REG[DECODE_RT], DECODE_IMMED, GPR_REG[DECODE_RS]); } -void LWL( string& output ) { strAppend(output, "lwl\t%s, 0x%04X(%s)", GPR_REG[DECODE_RT], DECODE_IMMED, GPR_REG[DECODE_RS]); } -void LW( string& output ) { strAppend(output, "lw\t%s, 0x%04X(%s)", GPR_REG[DECODE_RT], DECODE_IMMED, GPR_REG[DECODE_RS]); } -void LBU( string& output ) { strAppend(output, "lbu\t%s, 0x%04X(%s)", GPR_REG[DECODE_RT], DECODE_IMMED, GPR_REG[DECODE_RS]); } -void LHU( string& output ) { strAppend(output, "lhu\t%s, 0x%04X(%s)", GPR_REG[DECODE_RT], DECODE_IMMED, GPR_REG[DECODE_RS]); } -void LWR( string& output ) { strAppend(output, "lwr\t%s, 0x%04X(%s)", GPR_REG[DECODE_RT], DECODE_IMMED, GPR_REG[DECODE_RS]); } -void LWU( string& output ) { strAppend(output, "lwu\t%s, 0x%04X(%s)", GPR_REG[DECODE_RT], DECODE_IMMED, GPR_REG[DECODE_RS]); } -void SB( string& output ) { strAppend(output, "sb\t%s, 0x%04X(%s)", GPR_REG[DECODE_RT], DECODE_IMMED, GPR_REG[DECODE_RS]); } -void SH( string& output ) { strAppend(output, "sh\t%s, 0x%04X(%s)", GPR_REG[DECODE_RT], DECODE_IMMED, GPR_REG[DECODE_RS]); } -void SWL( string& output ) { strAppend(output, "swl\t%s, 0x%04X(%s)", GPR_REG[DECODE_RT], DECODE_IMMED, GPR_REG[DECODE_RS]); } -void SW( string& output ) { strAppend(output, "sw\t%s, 0x%04X(%s)", GPR_REG[DECODE_RT], DECODE_IMMED, GPR_REG[DECODE_RS]); } -void SDL( string& output ) { strAppend(output, "sdl\t%s, 0x%04X(%s)", GPR_REG[DECODE_RT], DECODE_IMMED, GPR_REG[DECODE_RS]); } -void SDR( string& output ) { strAppend(output, "sdr\t%s, 0x%04X(%s)", GPR_REG[DECODE_RT], DECODE_IMMED, GPR_REG[DECODE_RS]); } -void SWR( string& output ) { strAppend(output, "swr\t%s, 0x%04X(%s)", GPR_REG[DECODE_RT], DECODE_IMMED, GPR_REG[DECODE_RS]); } -void LD( string& output ) { strAppend(output, "ld\t%s, 0x%04X(%s)", GPR_REG[DECODE_RT], DECODE_IMMED, GPR_REG[DECODE_RS]); } -void SD( string& output ) { strAppend(output, "sd\t%s, 0x%04X(%s)", GPR_REG[DECODE_RT], DECODE_IMMED, GPR_REG[DECODE_RS]); } -void LQ( string& output ) { strAppend(output, "lq\t%s, 0x%04X(%s)", GPR_REG[DECODE_RT], DECODE_IMMED, GPR_REG[DECODE_RS]); } -void SQ( string& output ) { strAppend(output, "sq\t%s, 0x%04X(%s)", GPR_REG[DECODE_RT], DECODE_IMMED, GPR_REG[DECODE_RS]); } -void SWC1( string& output ) { strAppend(output, "swc1\t%s, 0x%04X(%s)", COP1_REG_FP[DECODE_FT], DECODE_IMMED, GPR_REG[DECODE_RS]); } -void SQC2( string& output ) { strAppend(output, "sqc2\t%s, 0x%04X(%s)", COP2_REG_FP[DECODE_FT], DECODE_IMMED, GPR_REG[DECODE_RS]); } -void PREF( string& output ) { output.append( "pref ---");/*strAppend(output, "PREF\t%s, 0x%04X(%s)", GPR_REG[DECODE_RT], DECODE_IMMED, GPR_REG[RS]); */} -void LWC1( string& output ) { strAppend(output, "lwc1\t%s, 0x%04X(%s)", COP1_REG_FP[DECODE_FT], DECODE_IMMED, GPR_REG[DECODE_RS]); } -void LQC2( string& output ) { strAppend(output, "lqc2\t%s, 0x%04X(%s)", COP2_REG_FP[DECODE_FT], DECODE_IMMED, GPR_REG[DECODE_RS]); } +void J( string& output ) { output += "j\t"; jump_decode(output);} +void JAL( string& output ) { output += "jal\t"; jump_decode(output);} +void BEQ( string& output ) { _sap("beq\t%s, %s, ") GPR_REG[DECODE_RS], GPR_REG[DECODE_RT]); offset_decode(output); } +void BNE( string& output ) { _sap("bne\t%s, %s, ") GPR_REG[DECODE_RS], GPR_REG[DECODE_RT]); offset_decode(output); } +void BLEZ( string& output ) { _sap("blez\t%s, ") GPR_REG[DECODE_RS]); offset_decode(output); } +void BGTZ( string& output ) { _sap("bgtz\t%s, ") GPR_REG[DECODE_RS]); offset_decode(output); } +void ADDI( string& output ) { _sap("addi\t%s, %s, 0x%04X") GPR_REG[DECODE_RT], GPR_REG[DECODE_RS], DECODE_IMMED);} +void ADDIU( string& output ) { _sap("addiu\t%s, %s, 0x%04X") GPR_REG[DECODE_RT], GPR_REG[DECODE_RS], DECODE_IMMED);} +void SLTI( string& output ) { _sap("slti\t%s, %s, 0x%04X") GPR_REG[DECODE_RT], GPR_REG[DECODE_RS], DECODE_IMMED); } +void SLTIU( string& output ) { _sap("sltiu\t%s, %s, 0x%04X") GPR_REG[DECODE_RT], GPR_REG[DECODE_RS], DECODE_IMMED); } +void ANDI( string& output ) { _sap("andi\t%s, %s, 0x%04X") GPR_REG[DECODE_RT], GPR_REG[DECODE_RS], DECODE_IMMED);} +void ORI( string& output ) { _sap("ori\t%s, %s, 0x%04X") GPR_REG[DECODE_RT], GPR_REG[DECODE_RS], DECODE_IMMED); } +void XORI( string& output ) { _sap("xori\t%s, %s, 0x%04X") GPR_REG[DECODE_RT], GPR_REG[DECODE_RS], DECODE_IMMED); } +void LUI( string& output ) { _sap("lui\t%s, 0x%04X") GPR_REG[DECODE_RT], DECODE_IMMED); } +void BEQL( string& output ) { _sap("beql\t%s, %s, %s") GPR_REG[DECODE_RS], GPR_REG[DECODE_RT]); offset_decode(output); } +void BNEL( string& output ) { _sap("bnel\t%s, %s, %s") GPR_REG[DECODE_RS], GPR_REG[DECODE_RT]); offset_decode(output); } +void BLEZL( string& output ) { _sap("blezl\t%s, ") GPR_REG[DECODE_RS]); offset_decode(output); } +void BGTZL( string& output ) { _sap("bgtzl\t%s, ") GPR_REG[DECODE_RS]); offset_decode(output); } +void DADDI( string& output ) { _sap("daddi\t%s, %s, 0x%04X") GPR_REG[DECODE_RT], GPR_REG[DECODE_RS], DECODE_IMMED); } +void DADDIU( string& output ) { _sap("daddiu\t%s, %s, 0x%04X") GPR_REG[DECODE_RT], GPR_REG[DECODE_RS], DECODE_IMMED); } +void LDL( string& output ) { _sap("ldl\t%s, 0x%04X(%s)") GPR_REG[DECODE_RT], DECODE_IMMED, GPR_REG[DECODE_RS]); } +void LDR( string& output ) { _sap("ldr\t%s, 0x%04X(%s)") GPR_REG[DECODE_RT], DECODE_IMMED, GPR_REG[DECODE_RS]); } +void LB( string& output ) { _sap("lb\t%s, 0x%04X(%s)") GPR_REG[DECODE_RT], DECODE_IMMED, GPR_REG[DECODE_RS]); } +void LH( string& output ) { _sap("lh\t%s, 0x%04X(%s)") GPR_REG[DECODE_RT], DECODE_IMMED, GPR_REG[DECODE_RS]); } +void LWL( string& output ) { _sap("lwl\t%s, 0x%04X(%s)") GPR_REG[DECODE_RT], DECODE_IMMED, GPR_REG[DECODE_RS]); } +void LW( string& output ) { _sap("lw\t%s, 0x%04X(%s)") GPR_REG[DECODE_RT], DECODE_IMMED, GPR_REG[DECODE_RS]); } +void LBU( string& output ) { _sap("lbu\t%s, 0x%04X(%s)") GPR_REG[DECODE_RT], DECODE_IMMED, GPR_REG[DECODE_RS]); } +void LHU( string& output ) { _sap("lhu\t%s, 0x%04X(%s)") GPR_REG[DECODE_RT], DECODE_IMMED, GPR_REG[DECODE_RS]); } +void LWR( string& output ) { _sap("lwr\t%s, 0x%04X(%s)") GPR_REG[DECODE_RT], DECODE_IMMED, GPR_REG[DECODE_RS]); } +void LWU( string& output ) { _sap("lwu\t%s, 0x%04X(%s)") GPR_REG[DECODE_RT], DECODE_IMMED, GPR_REG[DECODE_RS]); } +void SB( string& output ) { _sap("sb\t%s, 0x%04X(%s)") GPR_REG[DECODE_RT], DECODE_IMMED, GPR_REG[DECODE_RS]); } +void SH( string& output ) { _sap("sh\t%s, 0x%04X(%s)") GPR_REG[DECODE_RT], DECODE_IMMED, GPR_REG[DECODE_RS]); } +void SWL( string& output ) { _sap("swl\t%s, 0x%04X(%s)") GPR_REG[DECODE_RT], DECODE_IMMED, GPR_REG[DECODE_RS]); } +void SW( string& output ) { _sap("sw\t%s, 0x%04X(%s)") GPR_REG[DECODE_RT], DECODE_IMMED, GPR_REG[DECODE_RS]); } +void SDL( string& output ) { _sap("sdl\t%s, 0x%04X(%s)") GPR_REG[DECODE_RT], DECODE_IMMED, GPR_REG[DECODE_RS]); } +void SDR( string& output ) { _sap("sdr\t%s, 0x%04X(%s)") GPR_REG[DECODE_RT], DECODE_IMMED, GPR_REG[DECODE_RS]); } +void SWR( string& output ) { _sap("swr\t%s, 0x%04X(%s)") GPR_REG[DECODE_RT], DECODE_IMMED, GPR_REG[DECODE_RS]); } +void LD( string& output ) { _sap("ld\t%s, 0x%04X(%s)") GPR_REG[DECODE_RT], DECODE_IMMED, GPR_REG[DECODE_RS]); } +void SD( string& output ) { _sap("sd\t%s, 0x%04X(%s)") GPR_REG[DECODE_RT], DECODE_IMMED, GPR_REG[DECODE_RS]); } +void LQ( string& output ) { _sap("lq\t%s, 0x%04X(%s)") GPR_REG[DECODE_RT], DECODE_IMMED, GPR_REG[DECODE_RS]); } +void SQ( string& output ) { _sap("sq\t%s, 0x%04X(%s)") GPR_REG[DECODE_RT], DECODE_IMMED, GPR_REG[DECODE_RS]); } +void SWC1( string& output ) { _sap("swc1\t%s, 0x%04X(%s)") COP1_REG_FP[DECODE_FT], DECODE_IMMED, GPR_REG[DECODE_RS]); } +void SQC2( string& output ) { _sap("sqc2\t%s, 0x%04X(%s)") COP2_REG_FP[DECODE_FT], DECODE_IMMED, GPR_REG[DECODE_RS]); } +void PREF( string& output ) { output += "pref ---"; /*_sap("PREF\t%s, 0x%04X(%s)") GPR_REG[DECODE_RT], DECODE_IMMED, GPR_REG[RS]); */} +void LWC1( string& output ) { _sap("lwc1\t%s, 0x%04X(%s)") COP1_REG_FP[DECODE_FT], DECODE_IMMED, GPR_REG[DECODE_RS]); } +void LQC2( string& output ) { _sap("lqc2\t%s, 0x%04X(%s)") COP2_REG_FP[DECODE_FT], DECODE_IMMED, GPR_REG[DECODE_RS]); } //********************END OF STANDARD OPCODES************************* void SLL( string& output ) { if (cpuRegs.code == 0x00000000) - output.append( "nop"); + output += "nop"; else - strAppend(output, "sll\t%s, %s, 0x%02X", GPR_REG[DECODE_RD], GPR_REG[DECODE_RT], DECODE_SA); + _sap("sll\t%s, %s, 0x%02X") GPR_REG[DECODE_RD], GPR_REG[DECODE_RT], DECODE_SA); } -void SRL( string& output ) { strAppend(output, "srl\t%s, %s, 0x%02X", GPR_REG[DECODE_RD], GPR_REG[DECODE_RT], DECODE_SA); } -void SRA( string& output ) { strAppend(output, "sra\t%s, %s, 0x%02X", GPR_REG[DECODE_RD], GPR_REG[DECODE_RT], DECODE_SA); } -void SLLV( string& output ) { strAppend(output, "sllv\t%s, %s, %s", GPR_REG[DECODE_RD], GPR_REG[DECODE_RT], GPR_REG[DECODE_RS]); } -void SRLV( string& output ) { strAppend(output, "srlv\t%s, %s, %s", GPR_REG[DECODE_RD], GPR_REG[DECODE_RT], GPR_REG[DECODE_RS]);} -void SRAV( string& output ) { strAppend(output, "srav\t%s, %s, %s", GPR_REG[DECODE_RD], GPR_REG[DECODE_RT], GPR_REG[DECODE_RS]); } -void JR( string& output ) { strAppend(output, "jr\t%s", GPR_REG[DECODE_RS]); } +void SRL( string& output ) { _sap("srl\t%s, %s, 0x%02X") GPR_REG[DECODE_RD], GPR_REG[DECODE_RT], DECODE_SA); } +void SRA( string& output ) { _sap("sra\t%s, %s, 0x%02X") GPR_REG[DECODE_RD], GPR_REG[DECODE_RT], DECODE_SA); } +void SLLV( string& output ) { _sap("sllv\t%s, %s, %s") GPR_REG[DECODE_RD], GPR_REG[DECODE_RT], GPR_REG[DECODE_RS]); } +void SRLV( string& output ) { _sap("srlv\t%s, %s, %s") GPR_REG[DECODE_RD], GPR_REG[DECODE_RT], GPR_REG[DECODE_RS]);} +void SRAV( string& output ) { _sap("srav\t%s, %s, %s") GPR_REG[DECODE_RD], GPR_REG[DECODE_RT], GPR_REG[DECODE_RS]); } +void JR( string& output ) { _sap("jr\t%s") GPR_REG[DECODE_RS]); } void JALR( string& output ) { int rd = DECODE_RD; if (rd == 31) - strAppend(output, "jalr\t%s", GPR_REG[DECODE_RS]); + _sap("jalr\t%s") GPR_REG[DECODE_RS]); else - strAppend(output, "jalr\t%s, %s", GPR_REG[rd], GPR_REG[DECODE_RS]); + _sap("jalr\t%s, %s") GPR_REG[rd], GPR_REG[DECODE_RS]); } -void SYNC( string& output ) { strAppend(output, "SYNC");} -void MFHI( string& output ) { strAppend(output, "mfhi\t%s", GPR_REG[DECODE_RD]); } -void MTHI( string& output ) { strAppend(output, "mthi\t%s", GPR_REG[DECODE_RS]); } -void MFLO( string& output ) { strAppend(output, "mflo\t%s", GPR_REG[DECODE_RD]); } -void MTLO( string& output ) { strAppend(output, "mtlo\t%s", GPR_REG[DECODE_RS]); } -void DSLLV( string& output ) { strAppend(output, "dsllv\t%s, %s, %s", GPR_REG[DECODE_RD], GPR_REG[DECODE_RT], GPR_REG[DECODE_RS]); } -void DSRLV( string& output ) { strAppend(output, "dsrlv\t%s, %s, %s", GPR_REG[DECODE_RD], GPR_REG[DECODE_RT], GPR_REG[DECODE_RS]); } -void DSRAV( string& output ) { strAppend(output, "dsrav\t%s, %s, %s", GPR_REG[DECODE_RD], GPR_REG[DECODE_RT], GPR_REG[DECODE_RS]); } -void MULT( string& output ) { strAppend(output, "mult\t%s, %s, %s", GPR_REG[DECODE_RD], GPR_REG[DECODE_RS], GPR_REG[DECODE_RT]);} -void MULTU( string& output ) { strAppend(output, "multu\t%s, %s, %s", GPR_REG[DECODE_RD], GPR_REG[DECODE_RS], GPR_REG[DECODE_RT]);} -void DIV( string& output ) { strAppend(output, "div\t%s, %s", GPR_REG[DECODE_RS], GPR_REG[DECODE_RT]); } -void DIVU( string& output ) { strAppend(output, "divu\t%s, %s", GPR_REG[DECODE_RS], GPR_REG[DECODE_RT]); } -void ADD( string& output ) { strAppend(output, "add\t%s, %s, %s", GPR_REG[DECODE_RD], GPR_REG[DECODE_RS], GPR_REG[DECODE_RT]); } -void ADDU( string& output ) { strAppend(output, "addu\t%s, %s, %s", GPR_REG[DECODE_RD], GPR_REG[DECODE_RS], GPR_REG[DECODE_RT]); } -void SUB( string& output ) { strAppend(output, "sub\t%s, %s, %s", GPR_REG[DECODE_RD], GPR_REG[DECODE_RS], GPR_REG[DECODE_RT]); } -void SUBU( string& output ) { strAppend(output, "subu\t%s, %s, %s", GPR_REG[DECODE_RD], GPR_REG[DECODE_RS], GPR_REG[DECODE_RT]); } -void AND( string& output ) { strAppend(output, "and\t%s, %s, %s", GPR_REG[DECODE_RD], GPR_REG[DECODE_RS], GPR_REG[DECODE_RT]); } -void OR( string& output ) { strAppend(output, "or\t%s, %s, %s", GPR_REG[DECODE_RD], GPR_REG[DECODE_RS], GPR_REG[DECODE_RT]); } -void XOR( string& output ) { strAppend(output, "xor\t%s, %s, %s", GPR_REG[DECODE_RD], GPR_REG[DECODE_RS], GPR_REG[DECODE_RT]); } -void NOR( string& output ) { strAppend(output, "nor\t%s, %s, %s", GPR_REG[DECODE_RD], GPR_REG[DECODE_RS], GPR_REG[DECODE_RT]); } -void SLT( string& output ) { strAppend(output, "slt\t%s, %s, %s", GPR_REG[DECODE_RD], GPR_REG[DECODE_RS], GPR_REG[DECODE_RT]); } -void SLTU( string& output ) { strAppend(output, "sltu\t%s, %s, %s", GPR_REG[DECODE_RD], GPR_REG[DECODE_RS], GPR_REG[DECODE_RT]); } -void DADD( string& output ) { strAppend(output, "dadd\t%s, %s, %s", GPR_REG[DECODE_RD], GPR_REG[DECODE_RS], GPR_REG[DECODE_RT]); } -void DADDU( string& output ) { strAppend(output, "daddu\t%s, %s, %s", GPR_REG[DECODE_RD], GPR_REG[DECODE_RS], GPR_REG[DECODE_RT]); } -void DSUB( string& output ) { strAppend(output, "dsub\t%s, %s, %s", GPR_REG[DECODE_RD], GPR_REG[DECODE_RS], GPR_REG[DECODE_RT]); } -void DSUBU( string& output ) { strAppend(output, "dsubu\t%s, %s, %s", GPR_REG[DECODE_RD], GPR_REG[DECODE_RS], GPR_REG[DECODE_RT]); } -void TGE( string& output ) { strAppend(output, "tge\t%s, %s", GPR_REG[DECODE_RS], GPR_REG[DECODE_RT]); } -void TGEU( string& output ) { strAppend(output, "tgeu\t%s, %s", GPR_REG[DECODE_RS], GPR_REG[DECODE_RT]); } -void TLT( string& output ) { strAppend(output, "tlt\t%s, %s", GPR_REG[DECODE_RS], GPR_REG[DECODE_RT]); } -void TLTU( string& output ) { strAppend(output, "tltu\t%s, %s", GPR_REG[DECODE_RS], GPR_REG[DECODE_RT]); } -void TEQ( string& output ) { strAppend(output, "teq\t%s, %s", GPR_REG[DECODE_RS], GPR_REG[DECODE_RT]); } -void TNE( string& output ) { strAppend(output, "tne\t%s, %s", GPR_REG[DECODE_RS], GPR_REG[DECODE_RT]); } -void DSLL( string& output ) { strAppend(output, "dsll\t%s, %s, 0x%02X", GPR_REG[DECODE_RD], GPR_REG[DECODE_RT], DECODE_SA); } -void DSRL( string& output ) { strAppend(output, "dsrl\t%s, %s, 0x%02X", GPR_REG[DECODE_RD], GPR_REG[DECODE_RT], DECODE_SA); } -void DSRA( string& output ) { strAppend(output, "dsra\t%s, %s, 0x%02X", GPR_REG[DECODE_RD], GPR_REG[DECODE_RT], DECODE_SA); } -void DSLL32( string& output ) { strAppend(output, "dsll32\t%s, %s, 0x%02X", GPR_REG[DECODE_RD], GPR_REG[DECODE_RT], DECODE_SA); } -void DSRL32( string& output ) { strAppend(output, "dsrl32\t%s, %s, 0x%02X", GPR_REG[DECODE_RD], GPR_REG[DECODE_RT], DECODE_SA); } -void DSRA32( string& output ) { strAppend(output, "dsra32\t%s, %s, 0x%02X", GPR_REG[DECODE_RD], GPR_REG[DECODE_RT], DECODE_SA); } -void MOVZ( string& output ) { strAppend(output, "movz\t%s, %s, %s", GPR_REG[DECODE_RD], GPR_REG[DECODE_RS], GPR_REG[DECODE_RT]); } -void MOVN( string& output ) { strAppend(output, "movn\t%s, %s, %s", GPR_REG[DECODE_RD], GPR_REG[DECODE_RS], GPR_REG[DECODE_RT]); } -void MFSA( string& output ) { strAppend(output, "mfsa\t%s", GPR_REG[DECODE_RD]);} -void MTSA( string& output ) { strAppend(output, "mtsa\t%s", GPR_REG[DECODE_RS]);} +void SYNC( string& output ) { output += "SYNC"; } +void MFHI( string& output ) { _sap("mfhi\t%s") GPR_REG[DECODE_RD]); } +void MTHI( string& output ) { _sap("mthi\t%s") GPR_REG[DECODE_RS]); } +void MFLO( string& output ) { _sap("mflo\t%s") GPR_REG[DECODE_RD]); } +void MTLO( string& output ) { _sap("mtlo\t%s") GPR_REG[DECODE_RS]); } +void DSLLV( string& output ) { _sap("dsllv\t%s, %s, %s") GPR_REG[DECODE_RD], GPR_REG[DECODE_RT], GPR_REG[DECODE_RS]); } +void DSRLV( string& output ) { _sap("dsrlv\t%s, %s, %s") GPR_REG[DECODE_RD], GPR_REG[DECODE_RT], GPR_REG[DECODE_RS]); } +void DSRAV( string& output ) { _sap("dsrav\t%s, %s, %s") GPR_REG[DECODE_RD], GPR_REG[DECODE_RT], GPR_REG[DECODE_RS]); } +void MULT( string& output ) { _sap("mult\t%s, %s, %s") GPR_REG[DECODE_RD], GPR_REG[DECODE_RS], GPR_REG[DECODE_RT]);} +void MULTU( string& output ) { _sap("multu\t%s, %s, %s") GPR_REG[DECODE_RD], GPR_REG[DECODE_RS], GPR_REG[DECODE_RT]);} +void DIV( string& output ) { _sap("div\t%s, %s") GPR_REG[DECODE_RS], GPR_REG[DECODE_RT]); } +void DIVU( string& output ) { _sap("divu\t%s, %s") GPR_REG[DECODE_RS], GPR_REG[DECODE_RT]); } +void ADD( string& output ) { _sap("add\t%s, %s, %s") GPR_REG[DECODE_RD], GPR_REG[DECODE_RS], GPR_REG[DECODE_RT]); } +void ADDU( string& output ) { _sap("addu\t%s, %s, %s") GPR_REG[DECODE_RD], GPR_REG[DECODE_RS], GPR_REG[DECODE_RT]); } +void SUB( string& output ) { _sap("sub\t%s, %s, %s") GPR_REG[DECODE_RD], GPR_REG[DECODE_RS], GPR_REG[DECODE_RT]); } +void SUBU( string& output ) { _sap("subu\t%s, %s, %s") GPR_REG[DECODE_RD], GPR_REG[DECODE_RS], GPR_REG[DECODE_RT]); } +void AND( string& output ) { _sap("and\t%s, %s, %s") GPR_REG[DECODE_RD], GPR_REG[DECODE_RS], GPR_REG[DECODE_RT]); } +void OR( string& output ) { _sap("or\t%s, %s, %s") GPR_REG[DECODE_RD], GPR_REG[DECODE_RS], GPR_REG[DECODE_RT]); } +void XOR( string& output ) { _sap("xor\t%s, %s, %s") GPR_REG[DECODE_RD], GPR_REG[DECODE_RS], GPR_REG[DECODE_RT]); } +void NOR( string& output ) { _sap("nor\t%s, %s, %s") GPR_REG[DECODE_RD], GPR_REG[DECODE_RS], GPR_REG[DECODE_RT]); } +void SLT( string& output ) { _sap("slt\t%s, %s, %s") GPR_REG[DECODE_RD], GPR_REG[DECODE_RS], GPR_REG[DECODE_RT]); } +void SLTU( string& output ) { _sap("sltu\t%s, %s, %s") GPR_REG[DECODE_RD], GPR_REG[DECODE_RS], GPR_REG[DECODE_RT]); } +void DADD( string& output ) { _sap("dadd\t%s, %s, %s") GPR_REG[DECODE_RD], GPR_REG[DECODE_RS], GPR_REG[DECODE_RT]); } +void DADDU( string& output ) { _sap("daddu\t%s, %s, %s") GPR_REG[DECODE_RD], GPR_REG[DECODE_RS], GPR_REG[DECODE_RT]); } +void DSUB( string& output ) { _sap("dsub\t%s, %s, %s") GPR_REG[DECODE_RD], GPR_REG[DECODE_RS], GPR_REG[DECODE_RT]); } +void DSUBU( string& output ) { _sap("dsubu\t%s, %s, %s") GPR_REG[DECODE_RD], GPR_REG[DECODE_RS], GPR_REG[DECODE_RT]); } +void TGE( string& output ) { _sap("tge\t%s, %s") GPR_REG[DECODE_RS], GPR_REG[DECODE_RT]); } +void TGEU( string& output ) { _sap("tgeu\t%s, %s") GPR_REG[DECODE_RS], GPR_REG[DECODE_RT]); } +void TLT( string& output ) { _sap("tlt\t%s, %s") GPR_REG[DECODE_RS], GPR_REG[DECODE_RT]); } +void TLTU( string& output ) { _sap("tltu\t%s, %s") GPR_REG[DECODE_RS], GPR_REG[DECODE_RT]); } +void TEQ( string& output ) { _sap("teq\t%s, %s") GPR_REG[DECODE_RS], GPR_REG[DECODE_RT]); } +void TNE( string& output ) { _sap("tne\t%s, %s") GPR_REG[DECODE_RS], GPR_REG[DECODE_RT]); } +void DSLL( string& output ) { _sap("dsll\t%s, %s, 0x%02X") GPR_REG[DECODE_RD], GPR_REG[DECODE_RT], DECODE_SA); } +void DSRL( string& output ) { _sap("dsrl\t%s, %s, 0x%02X") GPR_REG[DECODE_RD], GPR_REG[DECODE_RT], DECODE_SA); } +void DSRA( string& output ) { _sap("dsra\t%s, %s, 0x%02X") GPR_REG[DECODE_RD], GPR_REG[DECODE_RT], DECODE_SA); } +void DSLL32( string& output ) { _sap("dsll32\t%s, %s, 0x%02X") GPR_REG[DECODE_RD], GPR_REG[DECODE_RT], DECODE_SA); } +void DSRL32( string& output ) { _sap("dsrl32\t%s, %s, 0x%02X") GPR_REG[DECODE_RD], GPR_REG[DECODE_RT], DECODE_SA); } +void DSRA32( string& output ) { _sap("dsra32\t%s, %s, 0x%02X") GPR_REG[DECODE_RD], GPR_REG[DECODE_RT], DECODE_SA); } +void MOVZ( string& output ) { _sap("movz\t%s, %s, %s") GPR_REG[DECODE_RD], GPR_REG[DECODE_RS], GPR_REG[DECODE_RT]); } +void MOVN( string& output ) { _sap("movn\t%s, %s, %s") GPR_REG[DECODE_RD], GPR_REG[DECODE_RS], GPR_REG[DECODE_RT]); } +void MFSA( string& output ) { _sap("mfsa\t%s") GPR_REG[DECODE_RD]);} +void MTSA( string& output ) { _sap("mtsa\t%s") GPR_REG[DECODE_RS]);} //*** unsupport (yet) cpu opcodes -void SYSCALL( string& output ) { output.append( "syscall ---");/*strAppend(output, "syscall\t0x%05X", DECODE_SYSCALL);*/} -void BREAK( string& output ) { output.append( "break ---");/*strAppend(output, "break\t0x%05X", DECODE_BREAK); */} -void CACHE( string& output ) { output.append( "cache ---");/*strAppend(output, "cache\t%s, 0x%04X(%s)", GPR_REG[DECODE_RT], DECODE_IMMED, GPR_REG[DECODE_RS]); */} +void SYSCALL( string& output ) { output +="syscall ---";/*_sap("syscall\t0x%05X") DECODE_SYSCALL);*/} +void BREAK( string& output ) { output += "break ---";/*_sap("break\t0x%05X") DECODE_BREAK); */} +void CACHE( string& output ) { output += "cache ---";/*_sap("cache\t%s, 0x%04X(%s)") GPR_REG[DECODE_RT], DECODE_IMMED, GPR_REG[DECODE_RS]); */} //************************REGIMM OPCODES*************************** -void BLTZ( string& output ) { strAppend(output, "bltz\t%s, ", GPR_REG[DECODE_RS]); offset_decode(output); } -void BGEZ( string& output ) { strAppend(output, "bgez\t%s, ", GPR_REG[DECODE_RS]); offset_decode(output); } -void BLTZL( string& output ) { strAppend(output, "bltzl\t%s, ", GPR_REG[DECODE_RS]); offset_decode(output); } -void BGEZL( string& output ) { strAppend(output, "bgezl\t%s, ", GPR_REG[DECODE_RS]); offset_decode(output); } -void TGEI( string& output ) { strAppend(output, "tgei\t%s, 0x%04X", GPR_REG[DECODE_RS], DECODE_IMMED); } -void TGEIU( string& output ) { strAppend(output, "tgeiu\t%s,0x%04X", GPR_REG[DECODE_RS], DECODE_IMMED); } -void TLTI( string& output ) { strAppend(output, "tlti\t%s, 0x%04X", GPR_REG[DECODE_RS], DECODE_IMMED); } -void TLTIU( string& output ) { strAppend(output, "tltiu\t%s,0x%04X", GPR_REG[DECODE_RS], DECODE_IMMED); } -void TEQI( string& output ) { strAppend(output, "teqi\t%s, 0x%04X", GPR_REG[DECODE_RS], DECODE_IMMED); } -void TNEI( string& output ) { strAppend(output, "tnei\t%s, 0x%04X", GPR_REG[DECODE_RS], DECODE_IMMED); } -void BLTZAL( string& output ) { strAppend(output, "bltzal\t%s, ", GPR_REG[DECODE_RS]); offset_decode(output); } -void BGEZAL( string& output ) { strAppend(output, "bgezal\t%s, ", GPR_REG[DECODE_RS]); offset_decode(output); } -void BLTZALL( string& output ) { strAppend(output, "bltzall\t%s, ", GPR_REG[DECODE_RS]); offset_decode(output); } -void BGEZALL( string& output ) { strAppend(output, "bgezall\t%s, ", GPR_REG[DECODE_RS]); offset_decode(output); } -void MTSAB( string& output ) { strAppend(output, "mtsab\t%s, 0x%04X", GPR_REG[DECODE_RS], DECODE_IMMED);} -void MTSAH( string& output ) { strAppend(output, "mtsah\t%s, 0x%04X", GPR_REG[DECODE_RS], DECODE_IMMED);} +void BLTZ( string& output ) { _sap("bltz\t%s, ") GPR_REG[DECODE_RS]); offset_decode(output); } +void BGEZ( string& output ) { _sap("bgez\t%s, ") GPR_REG[DECODE_RS]); offset_decode(output); } +void BLTZL( string& output ) { _sap("bltzl\t%s, ") GPR_REG[DECODE_RS]); offset_decode(output); } +void BGEZL( string& output ) { _sap("bgezl\t%s, ") GPR_REG[DECODE_RS]); offset_decode(output); } +void TGEI( string& output ) { _sap("tgei\t%s, 0x%04X") GPR_REG[DECODE_RS], DECODE_IMMED); } +void TGEIU( string& output ) { _sap("tgeiu\t%s,0x%04X") GPR_REG[DECODE_RS], DECODE_IMMED); } +void TLTI( string& output ) { _sap("tlti\t%s, 0x%04X") GPR_REG[DECODE_RS], DECODE_IMMED); } +void TLTIU( string& output ) { _sap("tltiu\t%s,0x%04X") GPR_REG[DECODE_RS], DECODE_IMMED); } +void TEQI( string& output ) { _sap("teqi\t%s, 0x%04X") GPR_REG[DECODE_RS], DECODE_IMMED); } +void TNEI( string& output ) { _sap("tnei\t%s, 0x%04X") GPR_REG[DECODE_RS], DECODE_IMMED); } +void BLTZAL( string& output ) { _sap("bltzal\t%s, ") GPR_REG[DECODE_RS]); offset_decode(output); } +void BGEZAL( string& output ) { _sap("bgezal\t%s, ") GPR_REG[DECODE_RS]); offset_decode(output); } +void BLTZALL( string& output ) { _sap("bltzall\t%s, ") GPR_REG[DECODE_RS]); offset_decode(output); } +void BGEZALL( string& output ) { _sap("bgezall\t%s, ") GPR_REG[DECODE_RS]); offset_decode(output); } +void MTSAB( string& output ) { _sap("mtsab\t%s, 0x%04X") GPR_REG[DECODE_RS], DECODE_IMMED);} +void MTSAH( string& output ) { _sap("mtsah\t%s, 0x%04X") GPR_REG[DECODE_RS], DECODE_IMMED);} //***************************SPECIAL 2 CPU OPCODES******************* const char* pmfhl_sub[] = { "lw", "uw", "slw", "lh", "sh" }; -void MADD( string& output ) { strAppend(output, "madd\t%s, %s %s", GPR_REG[DECODE_RD],GPR_REG[DECODE_RS], GPR_REG[DECODE_RT]); } -void MADDU( string& output ) { strAppend(output, "maddu\t%s, %s %s", GPR_REG[DECODE_RD],GPR_REG[DECODE_RS], GPR_REG[DECODE_RT]);} -void PLZCW( string& output ) { strAppend(output, "plzcw\t%s, %s", GPR_REG[DECODE_RD], GPR_REG[DECODE_RS]); } -void MADD1( string& output ) { strAppend(output, "madd1\t%s, %s %s", GPR_REG[DECODE_RD],GPR_REG[DECODE_RS], GPR_REG[DECODE_RT]); } -void MADDU1( string& output ) { strAppend(output, "maddu1\t%s, %s %s", GPR_REG[DECODE_RD],GPR_REG[DECODE_RS], GPR_REG[DECODE_RT]); } -void MFHI1( string& output ) { strAppend(output, "mfhi1\t%s", GPR_REG[DECODE_RD]); } -void MTHI1( string& output ) { strAppend(output, "mthi1\t%s", GPR_REG[DECODE_RS]); } -void MFLO1( string& output ) { strAppend(output, "mflo1\t%s", GPR_REG[DECODE_RD]); } -void MTLO1( string& output ) { strAppend(output, "mtlo1\t%s", GPR_REG[DECODE_RS]); } -void MULT1( string& output ) { strAppend(output, "mult1\t%s, %s, %s", GPR_REG[DECODE_RD], GPR_REG[DECODE_RS], GPR_REG[DECODE_RT]); } -void MULTU1( string& output ) { strAppend(output, "multu1\t%s, %s, %s", GPR_REG[DECODE_RD], GPR_REG[DECODE_RS], GPR_REG[DECODE_RT]);} -void DIV1( string& output ) { strAppend(output, "div1\t%s, %s", GPR_REG[DECODE_RS], GPR_REG[DECODE_RT]); } -void DIVU1( string& output ) { strAppend(output, "divu1\t%s, %s", GPR_REG[DECODE_RS], GPR_REG[DECODE_RT]); } +void MADD( string& output ) { _sap("madd\t%s, %s %s") GPR_REG[DECODE_RD],GPR_REG[DECODE_RS], GPR_REG[DECODE_RT]); } +void MADDU( string& output ) { _sap("maddu\t%s, %s %s") GPR_REG[DECODE_RD],GPR_REG[DECODE_RS], GPR_REG[DECODE_RT]);} +void PLZCW( string& output ) { _sap("plzcw\t%s, %s") GPR_REG[DECODE_RD], GPR_REG[DECODE_RS]); } +void MADD1( string& output ) { _sap("madd1\t%s, %s %s") GPR_REG[DECODE_RD],GPR_REG[DECODE_RS], GPR_REG[DECODE_RT]); } +void MADDU1( string& output ) { _sap("maddu1\t%s, %s %s") GPR_REG[DECODE_RD],GPR_REG[DECODE_RS], GPR_REG[DECODE_RT]); } +void MFHI1( string& output ) { _sap("mfhi1\t%s") GPR_REG[DECODE_RD]); } +void MTHI1( string& output ) { _sap("mthi1\t%s") GPR_REG[DECODE_RS]); } +void MFLO1( string& output ) { _sap("mflo1\t%s") GPR_REG[DECODE_RD]); } +void MTLO1( string& output ) { _sap("mtlo1\t%s") GPR_REG[DECODE_RS]); } +void MULT1( string& output ) { _sap("mult1\t%s, %s, %s") GPR_REG[DECODE_RD], GPR_REG[DECODE_RS], GPR_REG[DECODE_RT]); } +void MULTU1( string& output ) { _sap("multu1\t%s, %s, %s") GPR_REG[DECODE_RD], GPR_REG[DECODE_RS], GPR_REG[DECODE_RT]);} +void DIV1( string& output ) { _sap("div1\t%s, %s") GPR_REG[DECODE_RS], GPR_REG[DECODE_RT]); } +void DIVU1( string& output ) { _sap("divu1\t%s, %s") GPR_REG[DECODE_RS], GPR_REG[DECODE_RT]); } //that have parametres that i haven't figure out how to display... -void PMFHL( string& output ) { strAppend(output, "pmfhl.%s \t%s", pmfhl_sub[DECODE_SA], GPR_REG[DECODE_RD]); } -void PMTHL( string& output ) { strAppend(output, "pmthl.%s \t%s", pmfhl_sub[DECODE_SA], GPR_REG[DECODE_RS]); } -void PSLLH( string& output ) { strAppend(output, "psllh \t%s, %s, 0x%02X", GPR_REG[DECODE_RD], GPR_REG[DECODE_RT], DECODE_SA); } -void PSRLH( string& output ) { strAppend(output, "psrlh \t%s, %s, 0x%02X", GPR_REG[DECODE_RD], GPR_REG[DECODE_RT], DECODE_SA);} -void PSRAH( string& output ) { strAppend(output, "psrah \t%s, %s, 0x%02X", GPR_REG[DECODE_RD], GPR_REG[DECODE_RT], DECODE_SA);} -void PSLLW( string& output ) { strAppend(output, "psllw \t%s, %s, 0x%02X", GPR_REG[DECODE_RD], GPR_REG[DECODE_RT], DECODE_SA);} -void PSRLW( string& output ) { strAppend(output, "psrlw \t%s, %s, 0x%02X", GPR_REG[DECODE_RD], GPR_REG[DECODE_RT], DECODE_SA);} -void PSRAW( string& output ) { strAppend(output, "psraw \t%s, %s, 0x%02X", GPR_REG[DECODE_RD], GPR_REG[DECODE_RT], DECODE_SA);} +void PMFHL( string& output ) { _sap("pmfhl.%s \t%s") pmfhl_sub[DECODE_SA], GPR_REG[DECODE_RD]); } +void PMTHL( string& output ) { _sap("pmthl.%s \t%s") pmfhl_sub[DECODE_SA], GPR_REG[DECODE_RS]); } +void PSLLH( string& output ) { _sap("psllh \t%s, %s, 0x%02X") GPR_REG[DECODE_RD], GPR_REG[DECODE_RT], DECODE_SA); } +void PSRLH( string& output ) { _sap("psrlh \t%s, %s, 0x%02X") GPR_REG[DECODE_RD], GPR_REG[DECODE_RT], DECODE_SA);} +void PSRAH( string& output ) { _sap("psrah \t%s, %s, 0x%02X") GPR_REG[DECODE_RD], GPR_REG[DECODE_RT], DECODE_SA);} +void PSLLW( string& output ) { _sap( "psllw \t%s, %s, 0x%02X") GPR_REG[DECODE_RD], GPR_REG[DECODE_RT], DECODE_SA);} +void PSRLW( string& output ) { _sap( "psrlw \t%s, %s, 0x%02X") GPR_REG[DECODE_RD], GPR_REG[DECODE_RT], DECODE_SA);} +void PSRAW( string& output ) { _sap( "psraw \t%s, %s, 0x%02X") GPR_REG[DECODE_RD], GPR_REG[DECODE_RT], DECODE_SA);} //***************************END OF SPECIAL OPCODES****************** //*************************MMI0 OPCODES************************ -void PADDW( string& output ){ strAppend(output, "paddw\t%s, %s, %s", GPR_REG[DECODE_RD], GPR_REG[DECODE_RS], GPR_REG[DECODE_RT]); } -void PSUBW( string& output ){ strAppend(output, "psubw\t%s, %s, %s", GPR_REG[DECODE_RD], GPR_REG[DECODE_RS], GPR_REG[DECODE_RT]); } -void PCGTW( string& output ){ strAppend(output, "pcgtw\t%s, %s, %s", GPR_REG[DECODE_RD], GPR_REG[DECODE_RS], GPR_REG[DECODE_RT]); } -void PMAXW( string& output ){ strAppend(output, "pmaxw\t%s, %s, %s", GPR_REG[DECODE_RD], GPR_REG[DECODE_RS], GPR_REG[DECODE_RT]); } -void PADDH( string& output ){ strAppend(output, "paddh\t%s, %s, %s", GPR_REG[DECODE_RD], GPR_REG[DECODE_RS], GPR_REG[DECODE_RT]); } -void PSUBH( string& output ){ strAppend(output, "psubh\t%s, %s, %s", GPR_REG[DECODE_RD], GPR_REG[DECODE_RS], GPR_REG[DECODE_RT]); } -void PCGTH( string& output ){ strAppend(output, "pcgth\t%s, %s, %s", GPR_REG[DECODE_RD], GPR_REG[DECODE_RS], GPR_REG[DECODE_RT]); } -void PMAXH( string& output ){ strAppend(output, "pmaxh\t%s, %s, %s", GPR_REG[DECODE_RD], GPR_REG[DECODE_RS], GPR_REG[DECODE_RT]); } -void PADDB( string& output ){ strAppend(output, "paddb\t%s, %s, %s", GPR_REG[DECODE_RD], GPR_REG[DECODE_RS], GPR_REG[DECODE_RT]); } -void PSUBB( string& output ){ strAppend(output, "psubb\t%s, %s, %s", GPR_REG[DECODE_RD], GPR_REG[DECODE_RS], GPR_REG[DECODE_RT]); } -void PCGTB( string& output ){ strAppend(output, "pcgtb\t%s, %s, %s", GPR_REG[DECODE_RD], GPR_REG[DECODE_RS], GPR_REG[DECODE_RT]); } -void PADDSW( string& output ){ strAppend(output, "paddsw\t%s, %s, %s", GPR_REG[DECODE_RD], GPR_REG[DECODE_RS], GPR_REG[DECODE_RT]); } -void PSUBSW( string& output ){ strAppend(output, "psubsw\t%s, %s, %s", GPR_REG[DECODE_RD], GPR_REG[DECODE_RS], GPR_REG[DECODE_RT]); } -void PEXTLW( string& output ){ strAppend(output, "pextlw\t%s, %s, %s", GPR_REG[DECODE_RD], GPR_REG[DECODE_RS], GPR_REG[DECODE_RT]); } -void PPACW( string& output ) { strAppend(output, "ppacw\t%s, %s, %s", GPR_REG[DECODE_RD], GPR_REG[DECODE_RS], GPR_REG[DECODE_RT]); } -void PADDSH( string& output ){ strAppend(output, "paddsh\t%s, %s, %s", GPR_REG[DECODE_RD], GPR_REG[DECODE_RS], GPR_REG[DECODE_RT]); } -void PSUBSH( string& output ){ strAppend(output, "psubsh\t%s, %s, %s", GPR_REG[DECODE_RD], GPR_REG[DECODE_RS], GPR_REG[DECODE_RT]); } -void PEXTLH( string& output ){ strAppend(output, "pextlh\t%s, %s, %s", GPR_REG[DECODE_RD], GPR_REG[DECODE_RS], GPR_REG[DECODE_RT]); } -void PPACH( string& output ) { strAppend(output, "ppach\t%s, %s, %s", GPR_REG[DECODE_RD], GPR_REG[DECODE_RS], GPR_REG[DECODE_RT]); } -void PADDSB( string& output ){ strAppend(output, "paddsb\t%s, %s, %s", GPR_REG[DECODE_RD], GPR_REG[DECODE_RS], GPR_REG[DECODE_RT]); } -void PSUBSB( string& output ){ strAppend(output, "psubsb\t%s, %s, %s", GPR_REG[DECODE_RD], GPR_REG[DECODE_RS], GPR_REG[DECODE_RT]); } -void PEXTLB( string& output ){ strAppend(output, "pextlb\t%s, %s, %s", GPR_REG[DECODE_RD], GPR_REG[DECODE_RS], GPR_REG[DECODE_RT]); } -void PPACB( string& output ) { strAppend(output, "ppacb\t%s, %s, %s", GPR_REG[DECODE_RD], GPR_REG[DECODE_RS], GPR_REG[DECODE_RT]); } -void PEXT5( string& output ) { strAppend(output, "pext5\t%s, %s", GPR_REG[DECODE_RD], GPR_REG[DECODE_RT]); } -void PPAC5( string& output ) { strAppend(output, "ppac5\t%s, %s", GPR_REG[DECODE_RD], GPR_REG[DECODE_RT]); } +void PADDW( string& output ){ _sap( "paddw\t%s, %s, %s") GPR_REG[DECODE_RD], GPR_REG[DECODE_RS], GPR_REG[DECODE_RT]); } +void PSUBW( string& output ){ _sap( "psubw\t%s, %s, %s") GPR_REG[DECODE_RD], GPR_REG[DECODE_RS], GPR_REG[DECODE_RT]); } +void PCGTW( string& output ){ _sap( "pcgtw\t%s, %s, %s") GPR_REG[DECODE_RD], GPR_REG[DECODE_RS], GPR_REG[DECODE_RT]); } +void PMAXW( string& output ){ _sap( "pmaxw\t%s, %s, %s") GPR_REG[DECODE_RD], GPR_REG[DECODE_RS], GPR_REG[DECODE_RT]); } +void PADDH( string& output ){ _sap( "paddh\t%s, %s, %s") GPR_REG[DECODE_RD], GPR_REG[DECODE_RS], GPR_REG[DECODE_RT]); } +void PSUBH( string& output ){ _sap( "psubh\t%s, %s, %s") GPR_REG[DECODE_RD], GPR_REG[DECODE_RS], GPR_REG[DECODE_RT]); } +void PCGTH( string& output ){ _sap( "pcgth\t%s, %s, %s") GPR_REG[DECODE_RD], GPR_REG[DECODE_RS], GPR_REG[DECODE_RT]); } +void PMAXH( string& output ){ _sap( "pmaxh\t%s, %s, %s") GPR_REG[DECODE_RD], GPR_REG[DECODE_RS], GPR_REG[DECODE_RT]); } +void PADDB( string& output ){ _sap( "paddb\t%s, %s, %s") GPR_REG[DECODE_RD], GPR_REG[DECODE_RS], GPR_REG[DECODE_RT]); } +void PSUBB( string& output ){ _sap( "psubb\t%s, %s, %s") GPR_REG[DECODE_RD], GPR_REG[DECODE_RS], GPR_REG[DECODE_RT]); } +void PCGTB( string& output ){ _sap( "pcgtb\t%s, %s, %s") GPR_REG[DECODE_RD], GPR_REG[DECODE_RS], GPR_REG[DECODE_RT]); } +void PADDSW( string& output ){ _sap( "paddsw\t%s, %s, %s") GPR_REG[DECODE_RD], GPR_REG[DECODE_RS], GPR_REG[DECODE_RT]); } +void PSUBSW( string& output ){ _sap( "psubsw\t%s, %s, %s") GPR_REG[DECODE_RD], GPR_REG[DECODE_RS], GPR_REG[DECODE_RT]); } +void PEXTLW( string& output ){ _sap( "pextlw\t%s, %s, %s") GPR_REG[DECODE_RD], GPR_REG[DECODE_RS], GPR_REG[DECODE_RT]); } +void PPACW( string& output ) { _sap( "ppacw\t%s, %s, %s") GPR_REG[DECODE_RD], GPR_REG[DECODE_RS], GPR_REG[DECODE_RT]); } +void PADDSH( string& output ){ _sap( "paddsh\t%s, %s, %s") GPR_REG[DECODE_RD], GPR_REG[DECODE_RS], GPR_REG[DECODE_RT]); } +void PSUBSH( string& output ){ _sap( "psubsh\t%s, %s, %s") GPR_REG[DECODE_RD], GPR_REG[DECODE_RS], GPR_REG[DECODE_RT]); } +void PEXTLH( string& output ){ _sap( "pextlh\t%s, %s, %s") GPR_REG[DECODE_RD], GPR_REG[DECODE_RS], GPR_REG[DECODE_RT]); } +void PPACH( string& output ) { _sap( "ppach\t%s, %s, %s") GPR_REG[DECODE_RD], GPR_REG[DECODE_RS], GPR_REG[DECODE_RT]); } +void PADDSB( string& output ){ _sap( "paddsb\t%s, %s, %s") GPR_REG[DECODE_RD], GPR_REG[DECODE_RS], GPR_REG[DECODE_RT]); } +void PSUBSB( string& output ){ _sap( "psubsb\t%s, %s, %s") GPR_REG[DECODE_RD], GPR_REG[DECODE_RS], GPR_REG[DECODE_RT]); } +void PEXTLB( string& output ){ _sap( "pextlb\t%s, %s, %s") GPR_REG[DECODE_RD], GPR_REG[DECODE_RS], GPR_REG[DECODE_RT]); } +void PPACB( string& output ) { _sap( "ppacb\t%s, %s, %s") GPR_REG[DECODE_RD], GPR_REG[DECODE_RS], GPR_REG[DECODE_RT]); } +void PEXT5( string& output ) { _sap( "pext5\t%s, %s") GPR_REG[DECODE_RD], GPR_REG[DECODE_RT]); } +void PPAC5( string& output ) { _sap( "ppac5\t%s, %s") GPR_REG[DECODE_RD], GPR_REG[DECODE_RT]); } //**********END OF MMI0 OPCODES********************************* //**********MMI1 OPCODES************************************** -void PABSW( string& output ){ strAppend(output, "pabsw%s, %s", GPR_REG[DECODE_RD], GPR_REG[DECODE_RT]); } -void PCEQW( string& output ){ strAppend(output, "pceqw\t%s, %s, %s", GPR_REG[DECODE_RD], GPR_REG[DECODE_RS], GPR_REG[DECODE_RT]); } -void PMINW( string& output ){ strAppend(output, "pminw\t%s, %s, %s", GPR_REG[DECODE_RD], GPR_REG[DECODE_RS], GPR_REG[DECODE_RT]); } -void PADSBH( string& output ){ strAppend(output, "padsbh\t%s, %s, %s", GPR_REG[DECODE_RD], GPR_REG[DECODE_RS], GPR_REG[DECODE_RT]); } -void PABSH( string& output ){ strAppend(output, "pabsh%s, %s", GPR_REG[DECODE_RD], GPR_REG[DECODE_RT]); } -void PCEQH( string& output ){ strAppend(output, "pceqh\t%s, %s, %s", GPR_REG[DECODE_RD], GPR_REG[DECODE_RS], GPR_REG[DECODE_RT]); } -void PMINH( string& output ){ strAppend(output, "pminh\t%s, %s, %s", GPR_REG[DECODE_RD], GPR_REG[DECODE_RS], GPR_REG[DECODE_RT]); } -void PCEQB( string& output ){ strAppend(output, "pceqb\t%s, %s, %s", GPR_REG[DECODE_RD], GPR_REG[DECODE_RS], GPR_REG[DECODE_RT]); } -void PADDUW( string& output ){ strAppend(output, "padduw\t%s, %s, %s", GPR_REG[DECODE_RD], GPR_REG[DECODE_RS], GPR_REG[DECODE_RT]); } -void PSUBUW( string& output ){ strAppend(output, "psubuw\t%s, %s, %s", GPR_REG[DECODE_RD], GPR_REG[DECODE_RS], GPR_REG[DECODE_RT]); } -void PEXTUW( string& output ){ strAppend(output, "pextuw\t%s, %s, %s", GPR_REG[DECODE_RD], GPR_REG[DECODE_RS], GPR_REG[DECODE_RT]); } -void PADDUH( string& output ){ strAppend(output, "padduh\t%s, %s, %s", GPR_REG[DECODE_RD], GPR_REG[DECODE_RS], GPR_REG[DECODE_RT]); } -void PSUBUH( string& output ){ strAppend(output, "psubuh\t%s, %s, %s", GPR_REG[DECODE_RD], GPR_REG[DECODE_RS], GPR_REG[DECODE_RT]); } -void PEXTUH( string& output ){ strAppend(output, "pextuh\t%s, %s, %s", GPR_REG[DECODE_RD], GPR_REG[DECODE_RS], GPR_REG[DECODE_RT]); } -void PADDUB( string& output ){ strAppend(output, "paddub\t%s, %s, %s", GPR_REG[DECODE_RD], GPR_REG[DECODE_RS], GPR_REG[DECODE_RT]); } -void PSUBUB( string& output ){ strAppend(output, "psubub\t%s, %s, %s", GPR_REG[DECODE_RD], GPR_REG[DECODE_RS], GPR_REG[DECODE_RT]); } -void PEXTUB( string& output ){ strAppend(output, "pextub\t%s, %s, %s", GPR_REG[DECODE_RD], GPR_REG[DECODE_RS], GPR_REG[DECODE_RT]); } -void QFSRV( string& output ) { strAppend(output, "qfsrv\t%s, %s, %s", GPR_REG[DECODE_RD], GPR_REG[DECODE_RS], GPR_REG[DECODE_RT]); } +void PABSW( string& output ){ _sap( "pabsw%s, %s") GPR_REG[DECODE_RD], GPR_REG[DECODE_RT]); } +void PCEQW( string& output ){ _sap( "pceqw\t%s, %s, %s") GPR_REG[DECODE_RD], GPR_REG[DECODE_RS], GPR_REG[DECODE_RT]); } +void PMINW( string& output ){ _sap( "pminw\t%s, %s, %s") GPR_REG[DECODE_RD], GPR_REG[DECODE_RS], GPR_REG[DECODE_RT]); } +void PADSBH( string& output ){ _sap( "padsbh\t%s, %s, %s") GPR_REG[DECODE_RD], GPR_REG[DECODE_RS], GPR_REG[DECODE_RT]); } +void PABSH( string& output ){ _sap( "pabsh%s, %s") GPR_REG[DECODE_RD], GPR_REG[DECODE_RT]); } +void PCEQH( string& output ){ _sap( "pceqh\t%s, %s, %s") GPR_REG[DECODE_RD], GPR_REG[DECODE_RS], GPR_REG[DECODE_RT]); } +void PMINH( string& output ){ _sap( "pminh\t%s, %s, %s") GPR_REG[DECODE_RD], GPR_REG[DECODE_RS], GPR_REG[DECODE_RT]); } +void PCEQB( string& output ){ _sap( "pceqb\t%s, %s, %s") GPR_REG[DECODE_RD], GPR_REG[DECODE_RS], GPR_REG[DECODE_RT]); } +void PADDUW( string& output ){ _sap( "padduw\t%s, %s, %s") GPR_REG[DECODE_RD], GPR_REG[DECODE_RS], GPR_REG[DECODE_RT]); } +void PSUBUW( string& output ){ _sap( "psubuw\t%s, %s, %s") GPR_REG[DECODE_RD], GPR_REG[DECODE_RS], GPR_REG[DECODE_RT]); } +void PEXTUW( string& output ){ _sap( "pextuw\t%s, %s, %s") GPR_REG[DECODE_RD], GPR_REG[DECODE_RS], GPR_REG[DECODE_RT]); } +void PADDUH( string& output ){ _sap( "padduh\t%s, %s, %s") GPR_REG[DECODE_RD], GPR_REG[DECODE_RS], GPR_REG[DECODE_RT]); } +void PSUBUH( string& output ){ _sap( "psubuh\t%s, %s, %s") GPR_REG[DECODE_RD], GPR_REG[DECODE_RS], GPR_REG[DECODE_RT]); } +void PEXTUH( string& output ){ _sap( "pextuh\t%s, %s, %s") GPR_REG[DECODE_RD], GPR_REG[DECODE_RS], GPR_REG[DECODE_RT]); } +void PADDUB( string& output ){ _sap( "paddub\t%s, %s, %s") GPR_REG[DECODE_RD], GPR_REG[DECODE_RS], GPR_REG[DECODE_RT]); } +void PSUBUB( string& output ){ _sap( "psubub\t%s, %s, %s") GPR_REG[DECODE_RD], GPR_REG[DECODE_RS], GPR_REG[DECODE_RT]); } +void PEXTUB( string& output ){ _sap( "pextub\t%s, %s, %s") GPR_REG[DECODE_RD], GPR_REG[DECODE_RS], GPR_REG[DECODE_RT]); } +void QFSRV( string& output ) { _sap( "qfsrv\t%s, %s, %s") GPR_REG[DECODE_RD], GPR_REG[DECODE_RS], GPR_REG[DECODE_RT]); } //********END OF MMI1 OPCODES*********************************** //*********MMI2 OPCODES*************************************** -void PMADDW( string& output ){ strAppend(output, "pmaddw\t%s, %s, %s", GPR_REG[DECODE_RD], GPR_REG[DECODE_RS], GPR_REG[DECODE_RT]); } -void PSLLVW( string& output ){ strAppend(output, "psllvw\t%s, %s, %s", GPR_REG[DECODE_RD], GPR_REG[DECODE_RS], GPR_REG[DECODE_RT]); } -void PSRLVW( string& output ){ strAppend(output, "psrlvw\t%s, %s, %s", GPR_REG[DECODE_RD], GPR_REG[DECODE_RS], GPR_REG[DECODE_RT]); } -void PMSUBW( string& output ){ strAppend(output, "msubw\t%s, %s, %s", GPR_REG[DECODE_RD], GPR_REG[DECODE_RS], GPR_REG[DECODE_RT]); } -void PMFHI( string& output ){ strAppend(output, "pmfhi\t%s", GPR_REG[DECODE_RD]); } -void PMFLO( string& output ){ strAppend(output, "pmflo\t%s", GPR_REG[DECODE_RD]); } -void PINTH( string& output ){ strAppend(output, "pinth\t%s, %s, %s", GPR_REG[DECODE_RD], GPR_REG[DECODE_RS], GPR_REG[DECODE_RT]); } -void PMULTW( string& output ){ strAppend(output, "pmultw\t%s, %s, %s", GPR_REG[DECODE_RD], GPR_REG[DECODE_RS], GPR_REG[DECODE_RT]); } -void PDIVW( string& output ){ strAppend(output, "pdivw\t%s, %s", GPR_REG[DECODE_RS], GPR_REG[DECODE_RT]); } -void PCPYLD( string& output ){ strAppend(output, "pcpyld\t%s, %s, %s", GPR_REG[DECODE_RD], GPR_REG[DECODE_RS], GPR_REG[DECODE_RT]); } -void PMADDH( string& output ){ strAppend(output, "pmaddh\t%s, %s, %s", GPR_REG[DECODE_RD], GPR_REG[DECODE_RS], GPR_REG[DECODE_RT]); } -void PHMADH( string& output ){ strAppend(output, "phmadh\t%s, %s, %s", GPR_REG[DECODE_RD], GPR_REG[DECODE_RS], GPR_REG[DECODE_RT]); } -void PAND( string& output ){ strAppend(output, "pand\t%s, %s, %s", GPR_REG[DECODE_RD], GPR_REG[DECODE_RS], GPR_REG[DECODE_RT]); } -void PXOR( string& output ){ strAppend(output, "pxor\t%s, %s, %s", GPR_REG[DECODE_RD], GPR_REG[DECODE_RS], GPR_REG[DECODE_RT]); } -void PMSUBH( string& output ){ strAppend(output, "pmsubh\t%s, %s, %s", GPR_REG[DECODE_RD], GPR_REG[DECODE_RS], GPR_REG[DECODE_RT]); } -void PHMSBH( string& output ){ strAppend(output, "phmsbh\t%s, %s, %s", GPR_REG[DECODE_RD], GPR_REG[DECODE_RS], GPR_REG[DECODE_RT]); } -void PEXEH( string& output ){ strAppend(output, "pexeh\t%s, %s", GPR_REG[DECODE_RD], GPR_REG[DECODE_RT]); } -void PREVH( string& output ){ strAppend(output, "prevh\t%s, %s", GPR_REG[DECODE_RD], GPR_REG[DECODE_RT]); } -void PMULTH( string& output ){ strAppend(output, "pmulth\t%s, %s, %s", GPR_REG[DECODE_RD], GPR_REG[DECODE_RS], GPR_REG[DECODE_RT]); } -void PDIVBW( string& output ){ strAppend(output, "pdivbw\t%s, %s", GPR_REG[DECODE_RS], GPR_REG[DECODE_RT]); } -void PEXEW( string& output ){ strAppend(output, "pexew\t%s, %s", GPR_REG[DECODE_RD], GPR_REG[DECODE_RT]); } -void PROT3W( string& output ){ strAppend(output, "prot3w\t%s, %s", GPR_REG[DECODE_RD], GPR_REG[DECODE_RT]); } +void PMADDW( string& output ){ _sap( "pmaddw\t%s, %s, %s") GPR_REG[DECODE_RD], GPR_REG[DECODE_RS], GPR_REG[DECODE_RT]); } +void PSLLVW( string& output ){ _sap( "psllvw\t%s, %s, %s") GPR_REG[DECODE_RD], GPR_REG[DECODE_RS], GPR_REG[DECODE_RT]); } +void PSRLVW( string& output ){ _sap( "psrlvw\t%s, %s, %s") GPR_REG[DECODE_RD], GPR_REG[DECODE_RS], GPR_REG[DECODE_RT]); } +void PMSUBW( string& output ){ _sap( "msubw\t%s, %s, %s") GPR_REG[DECODE_RD], GPR_REG[DECODE_RS], GPR_REG[DECODE_RT]); } +void PMFHI( string& output ){ _sap( "pmfhi\t%s") GPR_REG[DECODE_RD]); } +void PMFLO( string& output ){ _sap( "pmflo\t%s") GPR_REG[DECODE_RD]); } +void PINTH( string& output ){ _sap( "pinth\t%s, %s, %s") GPR_REG[DECODE_RD], GPR_REG[DECODE_RS], GPR_REG[DECODE_RT]); } +void PMULTW( string& output ){ _sap( "pmultw\t%s, %s, %s") GPR_REG[DECODE_RD], GPR_REG[DECODE_RS], GPR_REG[DECODE_RT]); } +void PDIVW( string& output ){ _sap( "pdivw\t%s, %s") GPR_REG[DECODE_RS], GPR_REG[DECODE_RT]); } +void PCPYLD( string& output ){ _sap( "pcpyld\t%s, %s, %s") GPR_REG[DECODE_RD], GPR_REG[DECODE_RS], GPR_REG[DECODE_RT]); } +void PMADDH( string& output ){ _sap( "pmaddh\t%s, %s, %s") GPR_REG[DECODE_RD], GPR_REG[DECODE_RS], GPR_REG[DECODE_RT]); } +void PHMADH( string& output ){ _sap( "phmadh\t%s, %s, %s") GPR_REG[DECODE_RD], GPR_REG[DECODE_RS], GPR_REG[DECODE_RT]); } +void PAND( string& output ){ _sap( "pand\t%s, %s, %s") GPR_REG[DECODE_RD], GPR_REG[DECODE_RS], GPR_REG[DECODE_RT]); } +void PXOR( string& output ){ _sap( "pxor\t%s, %s, %s") GPR_REG[DECODE_RD], GPR_REG[DECODE_RS], GPR_REG[DECODE_RT]); } +void PMSUBH( string& output ){ _sap( "pmsubh\t%s, %s, %s") GPR_REG[DECODE_RD], GPR_REG[DECODE_RS], GPR_REG[DECODE_RT]); } +void PHMSBH( string& output ){ _sap( "phmsbh\t%s, %s, %s") GPR_REG[DECODE_RD], GPR_REG[DECODE_RS], GPR_REG[DECODE_RT]); } +void PEXEH( string& output ){ _sap( "pexeh\t%s, %s") GPR_REG[DECODE_RD], GPR_REG[DECODE_RT]); } +void PREVH( string& output ){ _sap( "prevh\t%s, %s") GPR_REG[DECODE_RD], GPR_REG[DECODE_RT]); } +void PMULTH( string& output ){ _sap( "pmulth\t%s, %s, %s") GPR_REG[DECODE_RD], GPR_REG[DECODE_RS], GPR_REG[DECODE_RT]); } +void PDIVBW( string& output ){ _sap( "pdivbw\t%s, %s") GPR_REG[DECODE_RS], GPR_REG[DECODE_RT]); } +void PEXEW( string& output ){ _sap( "pexew\t%s, %s") GPR_REG[DECODE_RD], GPR_REG[DECODE_RT]); } +void PROT3W( string& output ){ _sap( "prot3w\t%s, %s") GPR_REG[DECODE_RD], GPR_REG[DECODE_RT]); } //*****END OF MMI2 OPCODES*********************************** //*************************MMI3 OPCODES************************ -void PMADDUW( string& output ){ strAppend(output, "pmadduw\t%s, %s, %s", GPR_REG[DECODE_RD], GPR_REG[DECODE_RT], GPR_REG[DECODE_RS]); } -void PSRAVW( string& output ){ strAppend(output, "psravw\t%s, %s, %s", GPR_REG[DECODE_RD], GPR_REG[DECODE_RT], GPR_REG[DECODE_RS]); } -void PMTHI( string& output ){ strAppend(output, "pmthi\t%s", GPR_REG[DECODE_RS]); } -void PMTLO( string& output ){ strAppend(output, "pmtlo\t%s", GPR_REG[DECODE_RS]); } -void PINTEH( string& output ){ strAppend(output, "pinteh\t%s, %s, %s", GPR_REG[DECODE_RD], GPR_REG[DECODE_RS], GPR_REG[DECODE_RT]); } -void PMULTUW( string& output ){ strAppend(output, "pmultuw\t%s, %s, %s", GPR_REG[DECODE_RD], GPR_REG[DECODE_RS], GPR_REG[DECODE_RT]); } -void PDIVUW( string& output ){ strAppend(output, "pdivuw\t%s, %s", GPR_REG[DECODE_RS], GPR_REG[DECODE_RT]); } -void PCPYUD( string& output ){ strAppend(output, "pcpyud\t%s, %s, %s", GPR_REG[DECODE_RD], GPR_REG[DECODE_RS], GPR_REG[DECODE_RT]); } -void POR( string& output ){ strAppend(output, "por\t%s, %s, %s", GPR_REG[DECODE_RD], GPR_REG[DECODE_RS], GPR_REG[DECODE_RT]); } -void PNOR( string& output ){ strAppend(output, "pnor\t%s, %s, %s", GPR_REG[DECODE_RD], GPR_REG[DECODE_RS], GPR_REG[DECODE_RT]); } -void PEXCH( string& output ){ strAppend(output, "pexch\t%s, %s", GPR_REG[DECODE_RD], GPR_REG[DECODE_RT]);} -void PCPYH( string& output ){ strAppend(output, "pcpyh\t%s, %s", GPR_REG[DECODE_RD], GPR_REG[DECODE_RT]);} -void PEXCW( string& output ){ strAppend(output, "pexcw\t%s, %s", GPR_REG[DECODE_RD], GPR_REG[DECODE_RT]);} +void PMADDUW( string& output ){ _sap("pmadduw\t%s, %s, %s") GPR_REG[DECODE_RD], GPR_REG[DECODE_RT], GPR_REG[DECODE_RS]); } +void PSRAVW( string& output ){ _sap("psravw\t%s, %s, %s") GPR_REG[DECODE_RD], GPR_REG[DECODE_RT], GPR_REG[DECODE_RS]); } +void PMTHI( string& output ){ _sap("pmthi\t%s") GPR_REG[DECODE_RS]); } +void PMTLO( string& output ){ _sap("pmtlo\t%s") GPR_REG[DECODE_RS]); } +void PINTEH( string& output ){ _sap("pinteh\t%s, %s, %s") GPR_REG[DECODE_RD], GPR_REG[DECODE_RS], GPR_REG[DECODE_RT]); } +void PMULTUW( string& output ){ _sap("pmultuw\t%s, %s, %s") GPR_REG[DECODE_RD], GPR_REG[DECODE_RS], GPR_REG[DECODE_RT]); } +void PDIVUW( string& output ){ _sap("pdivuw\t%s, %s") GPR_REG[DECODE_RS], GPR_REG[DECODE_RT]); } +void PCPYUD( string& output ){ _sap("pcpyud\t%s, %s, %s") GPR_REG[DECODE_RD], GPR_REG[DECODE_RS], GPR_REG[DECODE_RT]); } +void POR( string& output ){ _sap("por\t%s, %s, %s") GPR_REG[DECODE_RD], GPR_REG[DECODE_RS], GPR_REG[DECODE_RT]); } +void PNOR( string& output ){ _sap("pnor\t%s, %s, %s") GPR_REG[DECODE_RD], GPR_REG[DECODE_RS], GPR_REG[DECODE_RT]); } +void PEXCH( string& output ){ _sap("pexch\t%s, %s") GPR_REG[DECODE_RD], GPR_REG[DECODE_RT]);} +void PCPYH( string& output ){ _sap("pcpyh\t%s, %s") GPR_REG[DECODE_RD], GPR_REG[DECODE_RT]);} +void PEXCW( string& output ){ _sap("pexcw\t%s, %s") GPR_REG[DECODE_RD], GPR_REG[DECODE_RT]);} //**********************END OF MMI3 OPCODES******************** -} } } // End namespace EE::Debug::OpcodePrint - //**************************************************************************** //** COP0 ** //**************************************************************************** -void P_MFC0( string& output ){ strAppend(output, "mfc0\t%s, %s", GPR_REG[DECODE_RT], COP0_REG[DECODE_FS]); } -void P_MTC0( string& output ){ strAppend(output, "mtc0\t%s, %s", GPR_REG[DECODE_RT], COP0_REG[DECODE_FS]); } -void P_BC0F( string& output ){ output.append("bc0f\t"); offset_decode(output); } -void P_BC0T( string& output ){ output.append("bc0t\t"); offset_decode(output); } -void P_BC0FL( string& output ){ output.append("bc0fl\t"); offset_decode(output); } -void P_BC0TL( string& output ){ output.append("bc0tl\t"); offset_decode(output); } -void P_TLBR( string& output ){ output.append("tlbr");} -void P_TLBWI( string& output ){ output.append("tlbwi");} -void P_TLBWR( string& output ){ output.append("tlbwr");} -void P_TLBP( string& output ){ output.append("tlbp");} -void P_ERET( string& output ){ output.append("eret");} -void P_DI( string& output ){ output.append("di");} -void P_EI( string& output ){ output.append("ei");} +void MFC0( string& output ){ _sap("mfc0\t%s, %s") GPR_REG[DECODE_RT], COP0_REG[DECODE_FS]); } +void MTC0( string& output ){ _sap("mtc0\t%s, %s") GPR_REG[DECODE_RT], COP0_REG[DECODE_FS]); } +void BC0F( string& output ){ output += "bc0f\t"; offset_decode(output); } +void BC0T( string& output ){ output += "bc0t\t"; offset_decode(output); } +void BC0FL( string& output ){ output += "bc0fl\t"; offset_decode(output); } +void BC0TL( string& output ){ output += "bc0tl\t"; offset_decode(output); } +void TLBR( string& output ){ output += "tlbr";} +void TLBWI( string& output ){ output += "tlbwi";} +void TLBWR( string& output ){ output += "tlbwr";} +void TLBP( string& output ){ output += "tlbp";} +void ERET( string& output ){ output += "eret";} +void DI( string& output ){ output += "di";} +void EI( string& output ){ output += "ei";} //**************************************************************************** //** END OF COP0 ** //**************************************************************************** //**************************************************************************** //** COP1 - Floating Point Unit (FPU) ** //**************************************************************************** -void P_MFC1( string& output ){ strAppend(output, "mfc1\t%s, %s", GPR_REG[DECODE_RT], COP1_REG_FP[DECODE_FS]); } -void P_CFC1( string& output ){ strAppend(output, "cfc1\t%s, %s", GPR_REG[DECODE_RT], COP1_REG_FCR[DECODE_FS]); } -void P_MTC1( string& output ){ strAppend(output, "mtc1\t%s, %s", GPR_REG[DECODE_RT], COP1_REG_FP[DECODE_FS]); } -void P_CTC1( string& output ){ strAppend(output, "ctc1\t%s, %s", GPR_REG[DECODE_RT], COP1_REG_FCR[DECODE_FS]); } -void P_BC1F( string& output ){ output.append("bc1f\t"); offset_decode(output); } -void P_BC1T( string& output ){ output.append("bc1t\t"); offset_decode(output); } -void P_BC1FL( string& output ){ output.append("bc1fl\t"); offset_decode(output); } -void P_BC1TL( string& output ){ output.append("bc1tl\t"); offset_decode(output); } -void P_ADD_S( string& output ){ strAppend(output, "add.s\t%s, %s, %s", COP1_REG_FP[DECODE_FD], COP1_REG_FP[DECODE_FS], COP1_REG_FP[DECODE_FT]);} -void P_SUB_S( string& output ){ strAppend(output, "sub.s\t%s, %s, %s", COP1_REG_FP[DECODE_FD], COP1_REG_FP[DECODE_FS], COP1_REG_FP[DECODE_FT]);} -void P_MUL_S( string& output ){ strAppend(output, "mul.s\t%s, %s, %s", COP1_REG_FP[DECODE_FD], COP1_REG_FP[DECODE_FS], COP1_REG_FP[DECODE_FT]);} -void P_DIV_S( string& output ){ strAppend(output, "div.s\t%s, %s, %s", COP1_REG_FP[DECODE_FD], COP1_REG_FP[DECODE_FS], COP1_REG_FP[DECODE_FT]); } -void P_SQRT_S( string& output ){ strAppend(output, "sqrt.s\t%s, %s", COP1_REG_FP[DECODE_FD], COP1_REG_FP[DECODE_FT]); } -void P_ABS_S( string& output ){ strAppend(output, "abs.s\t%s, %s", COP1_REG_FP[DECODE_FD], COP1_REG_FP[DECODE_FS]); } -void P_MOV_S( string& output ){ strAppend(output, "mov.s\t%s, %s", COP1_REG_FP[DECODE_FD], COP1_REG_FP[DECODE_FS]); } -void P_NEG_S( string& output ){ strAppend(output, "neg.s\t%s, %s", COP1_REG_FP[DECODE_FD], COP1_REG_FP[DECODE_FS]);} -void P_RSQRT_S( string& output ){strAppend(output, "rsqrt.s\t%s, %s, %s", COP1_REG_FP[DECODE_FD], COP1_REG_FP[DECODE_FS], COP1_REG_FP[DECODE_FT]);} -void P_ADDA_S( string& output ){ strAppend(output, "adda.s\t%s, %s", COP1_REG_FP[DECODE_FS], COP1_REG_FP[DECODE_FT]); } -void P_SUBA_S( string& output ){ strAppend(output, "suba.s\t%s, %s", COP1_REG_FP[DECODE_FS], COP1_REG_FP[DECODE_FT]); } -void P_MULA_S( string& output ){ strAppend(output, "mula.s\t%s, %s", COP1_REG_FP[DECODE_FS], COP1_REG_FP[DECODE_FT]); } -void P_MADD_S( string& output ){ strAppend(output, "madd.s\t%s, %s, %s", COP1_REG_FP[DECODE_FD], COP1_REG_FP[DECODE_FS], COP1_REG_FP[DECODE_FT]); } -void P_MSUB_S( string& output ){ strAppend(output, "msub.s\t%s, %s, %s", COP1_REG_FP[DECODE_FD], COP1_REG_FP[DECODE_FS], COP1_REG_FP[DECODE_FT]); } -void P_MADDA_S( string& output ){strAppend(output, "madda.s\t%s, %s", COP1_REG_FP[DECODE_FS], COP1_REG_FP[DECODE_FT]); } -void P_MSUBA_S( string& output ){strAppend(output, "msuba.s\t%s, %s", COP1_REG_FP[DECODE_FS], COP1_REG_FP[DECODE_FT]); } -void P_CVT_W( string& output ){ strAppend(output, "cvt.w.s\t%s, %s", COP1_REG_FP[DECODE_FD], COP1_REG_FP[DECODE_FS]); } -void P_MAX_S( string& output ){ strAppend(output, "max.s\t%s, %s, %s", COP1_REG_FP[DECODE_FD], COP1_REG_FP[DECODE_FS], COP1_REG_FP[DECODE_FT]);} -void P_MIN_S( string& output ){ strAppend(output, "min.s\t%s, %s, %s", COP1_REG_FP[DECODE_FD], COP1_REG_FP[DECODE_FS], COP1_REG_FP[DECODE_FT]);} -void P_C_F( string& output ){ strAppend(output, "c.f.s\t%s, %s", COP1_REG_FP[DECODE_FS], COP1_REG_FP[DECODE_FT]); } -void P_C_EQ( string& output ){ strAppend(output, "c.eq.s\t%s, %s", COP1_REG_FP[DECODE_FS], COP1_REG_FP[DECODE_FT]); } -void P_C_LT( string& output ){ strAppend(output, "c.lt.s\t%s, %s", COP1_REG_FP[DECODE_FS], COP1_REG_FP[DECODE_FT]); } -void P_C_LE( string& output ){ strAppend(output, "c.le.s\t%s, %s", COP1_REG_FP[DECODE_FS], COP1_REG_FP[DECODE_FT]); } -void P_CVT_S( string& output ){ strAppend(output, "cvt.s.w\t%s, %s", COP1_REG_FP[DECODE_FD], COP1_REG_FP[DECODE_FS]); } +void MFC1( string& output ){ _sap("mfc1\t%s, %s") GPR_REG[DECODE_RT], COP1_REG_FP[DECODE_FS]); } +void CFC1( string& output ){ _sap("cfc1\t%s, %s") GPR_REG[DECODE_RT], COP1_REG_FCR[DECODE_FS]); } +void MTC1( string& output ){ _sap("mtc1\t%s, %s") GPR_REG[DECODE_RT], COP1_REG_FP[DECODE_FS]); } +void CTC1( string& output ){ _sap("ctc1\t%s, %s") GPR_REG[DECODE_RT], COP1_REG_FCR[DECODE_FS]); } +void BC1F( string& output ){ output += "bc1f\t"; offset_decode(output); } +void BC1T( string& output ){ output += "bc1t\t"; offset_decode(output); } +void BC1FL( string& output ){ output += "bc1fl\t"; offset_decode(output); } +void BC1TL( string& output ){ output += "bc1tl\t"; offset_decode(output); } +void ADD_S( string& output ){ _sap("add.s\t%s, %s, %s") COP1_REG_FP[DECODE_FD], COP1_REG_FP[DECODE_FS], COP1_REG_FP[DECODE_FT]);} +void SUB_S( string& output ){ _sap("sub.s\t%s, %s, %s") COP1_REG_FP[DECODE_FD], COP1_REG_FP[DECODE_FS], COP1_REG_FP[DECODE_FT]);} +void MUL_S( string& output ){ _sap("mul.s\t%s, %s, %s") COP1_REG_FP[DECODE_FD], COP1_REG_FP[DECODE_FS], COP1_REG_FP[DECODE_FT]);} +void DIV_S( string& output ){ _sap("div.s\t%s, %s, %s") COP1_REG_FP[DECODE_FD], COP1_REG_FP[DECODE_FS], COP1_REG_FP[DECODE_FT]); } +void SQRT_S( string& output ){ _sap("sqrt.s\t%s, %s") COP1_REG_FP[DECODE_FD], COP1_REG_FP[DECODE_FT]); } +void ABS_S( string& output ){ _sap("abs.s\t%s, %s") COP1_REG_FP[DECODE_FD], COP1_REG_FP[DECODE_FS]); } +void MOV_S( string& output ){ _sap("mov.s\t%s, %s") COP1_REG_FP[DECODE_FD], COP1_REG_FP[DECODE_FS]); } +void NEG_S( string& output ){ _sap("neg.s\t%s, %s") COP1_REG_FP[DECODE_FD], COP1_REG_FP[DECODE_FS]);} +void RSQRT_S( string& output ){_sap("rsqrt.s\t%s, %s, %s") COP1_REG_FP[DECODE_FD], COP1_REG_FP[DECODE_FS], COP1_REG_FP[DECODE_FT]);} +void ADDA_S( string& output ){ _sap("adda.s\t%s, %s") COP1_REG_FP[DECODE_FS], COP1_REG_FP[DECODE_FT]); } +void SUBA_S( string& output ){ _sap("suba.s\t%s, %s") COP1_REG_FP[DECODE_FS], COP1_REG_FP[DECODE_FT]); } +void MULA_S( string& output ){ _sap("mula.s\t%s, %s") COP1_REG_FP[DECODE_FS], COP1_REG_FP[DECODE_FT]); } +void MADD_S( string& output ){ _sap("madd.s\t%s, %s, %s") COP1_REG_FP[DECODE_FD], COP1_REG_FP[DECODE_FS], COP1_REG_FP[DECODE_FT]); } +void MSUB_S( string& output ){ _sap("msub.s\t%s, %s, %s") COP1_REG_FP[DECODE_FD], COP1_REG_FP[DECODE_FS], COP1_REG_FP[DECODE_FT]); } +void MADDA_S( string& output ){_sap("madda.s\t%s, %s") COP1_REG_FP[DECODE_FS], COP1_REG_FP[DECODE_FT]); } +void MSUBA_S( string& output ){_sap("msuba.s\t%s, %s") COP1_REG_FP[DECODE_FS], COP1_REG_FP[DECODE_FT]); } +void CVT_W( string& output ){ _sap("cvt.w.s\t%s, %s") COP1_REG_FP[DECODE_FD], COP1_REG_FP[DECODE_FS]); } +void MAX_S( string& output ){ _sap("max.s\t%s, %s, %s") COP1_REG_FP[DECODE_FD], COP1_REG_FP[DECODE_FS], COP1_REG_FP[DECODE_FT]);} +void MIN_S( string& output ){ _sap("min.s\t%s, %s, %s") COP1_REG_FP[DECODE_FD], COP1_REG_FP[DECODE_FS], COP1_REG_FP[DECODE_FT]);} +void C_F( string& output ){ _sap("c.f.s\t%s, %s") COP1_REG_FP[DECODE_FS], COP1_REG_FP[DECODE_FT]); } +void C_EQ( string& output ){ _sap("c.eq.s\t%s, %s") COP1_REG_FP[DECODE_FS], COP1_REG_FP[DECODE_FT]); } +void C_LT( string& output ){ _sap("c.lt.s\t%s, %s") COP1_REG_FP[DECODE_FS], COP1_REG_FP[DECODE_FT]); } +void C_LE( string& output ){ _sap("c.le.s\t%s, %s") COP1_REG_FP[DECODE_FS], COP1_REG_FP[DECODE_FT]); } +void CVT_S( string& output ){ _sap("cvt.s.w\t%s, %s") COP1_REG_FP[DECODE_FD], COP1_REG_FP[DECODE_FS]); } //**************************************************************************** //** END OF COP1 ** //**************************************************************************** + +} // End namespace R5900::OpcodeDisasm + //**************************************************************************** //** COP2 - (VU0) ** //**************************************************************************** -void P_QMFC2( string& output ){ strAppend(output, "qmfc2\t%s, %s", GPR_REG[DECODE_RT], COP2_REG_FP[DECODE_FS]); } -void P_CFC2( string& output ){ strAppend(output, "cfc2\t%s, %s", GPR_REG[DECODE_RT], COP2_REG_CTL[DECODE_FS]); } -void P_QMTC2( string& output ){ strAppend(output, "qmtc2\t%s, %s", GPR_REG[DECODE_RT], COP2_REG_FP[DECODE_FS]); } -void P_CTC2( string& output ){ strAppend(output, "ctc2\t%s, %s", GPR_REG[DECODE_RT], COP2_REG_CTL[DECODE_FS]); } -void P_BC2F( string& output ){ output.append("bc2f\t"); offset_decode(output); } -void P_BC2T( string& output ){ output.append("bc2t\t"); offset_decode(output); } -void P_BC2FL( string& output ){ output.append("bc2fl\t"); offset_decode(output); } -void P_BC2TL( string& output ){ output.append("bc2tl\t"); offset_decode(output); } +void P_QMFC2( string& output ){ _sap("qmfc2\t%s, %s") GPR_REG[DECODE_RT], COP2_REG_FP[DECODE_FS]); } +void P_CFC2( string& output ){ _sap("cfc2\t%s, %s") GPR_REG[DECODE_RT], COP2_REG_CTL[DECODE_FS]); } +void P_QMTC2( string& output ){ _sap("qmtc2\t%s, %s") GPR_REG[DECODE_RT], COP2_REG_FP[DECODE_FS]); } +void P_CTC2( string& output ){ _sap("ctc2\t%s, %s") GPR_REG[DECODE_RT], COP2_REG_CTL[DECODE_FS]); } +void P_BC2F( string& output ){ output += "bc2f\t"; offset_decode(output); } +void P_BC2T( string& output ){ output += "bc2t\t"; offset_decode(output); } +void P_BC2FL( string& output ){ output += "bc2fl\t"; offset_decode(output); } +void P_BC2TL( string& output ){ output += "bc2tl\t"; offset_decode(output); } //******************************SPECIAL 1 VUO TABLE**************************************** #define _X ((cpuRegs.code>>24) & 1) #define _Y ((cpuRegs.code>>23) & 1) @@ -1216,126 +1065,128 @@ char dest_ftf() return arr[(cpuRegs.code>>23)&3]; } -void P_VADDx( string& output ){strAppend(output, "vaddx.%s %s, %s, %sx", dest_string(),COP2_REG_FP[DECODE_FD], COP2_REG_FP[DECODE_FS],COP2_REG_FP[DECODE_FT]); } -void P_VADDy( string& output ){strAppend(output, "vaddy.%s %s, %s, %sy", dest_string(),COP2_REG_FP[DECODE_FD], COP2_REG_FP[DECODE_FS],COP2_REG_FP[DECODE_FT]); } -void P_VADDz( string& output ){strAppend(output, "vaddz.%s %s, %s, %sz", dest_string(),COP2_REG_FP[DECODE_FD], COP2_REG_FP[DECODE_FS],COP2_REG_FP[DECODE_FT]); } -void P_VADDw( string& output ){strAppend(output, "vaddw.%s %s, %s, %sw", dest_string(),COP2_REG_FP[DECODE_FD], COP2_REG_FP[DECODE_FS],COP2_REG_FP[DECODE_FT]); } -void P_VSUBx( string& output ){strAppend(output, "vsubx.%s %s, %s, %sx", dest_string(),COP2_REG_FP[DECODE_FD], COP2_REG_FP[DECODE_FS],COP2_REG_FP[DECODE_FT]); } -void P_VSUBy( string& output ){strAppend(output, "vsuby.%s %s, %s, %sy", dest_string(),COP2_REG_FP[DECODE_FD], COP2_REG_FP[DECODE_FS],COP2_REG_FP[DECODE_FT]); } -void P_VSUBz( string& output ){strAppend(output, "vsubz.%s %s, %s, %sz", dest_string(),COP2_REG_FP[DECODE_FD], COP2_REG_FP[DECODE_FS],COP2_REG_FP[DECODE_FT]); } -void P_VSUBw( string& output ){strAppend(output, "vsubw.%s %s, %s, %sw", dest_string(),COP2_REG_FP[DECODE_FD], COP2_REG_FP[DECODE_FS],COP2_REG_FP[DECODE_FT]); } -void P_VMADDx( string& output ){strAppend(output, "vmaddx.%s %s, %s, %sx", dest_string(),COP2_REG_FP[DECODE_FD], COP2_REG_FP[DECODE_FS],COP2_REG_FP[DECODE_FT]); } -void P_VMADDy( string& output ){strAppend(output, "vmaddy.%s %s, %s, %sy", dest_string(),COP2_REG_FP[DECODE_FD], COP2_REG_FP[DECODE_FS],COP2_REG_FP[DECODE_FT]); } -void P_VMADDz( string& output ){strAppend(output, "vmaddz.%s %s, %s, %sz", dest_string(),COP2_REG_FP[DECODE_FD], COP2_REG_FP[DECODE_FS],COP2_REG_FP[DECODE_FT]); } -void P_VMADDw( string& output ){strAppend(output, "vmaddw.%s %s, %s, %sw", dest_string(),COP2_REG_FP[DECODE_FD], COP2_REG_FP[DECODE_FS],COP2_REG_FP[DECODE_FT]); } -void P_VMSUBx( string& output ){strAppend(output, "vmsubx.%s %s, %s, %sx", dest_string(),COP2_REG_FP[DECODE_FD], COP2_REG_FP[DECODE_FS],COP2_REG_FP[DECODE_FT]); } -void P_VMSUBy( string& output ){strAppend(output, "vmsuby.%s %s, %s, %sy", dest_string(),COP2_REG_FP[DECODE_FD], COP2_REG_FP[DECODE_FS],COP2_REG_FP[DECODE_FT]); } -void P_VMSUBz( string& output ){strAppend(output, "vmsubz.%s %s, %s, %sz", dest_string(),COP2_REG_FP[DECODE_FD], COP2_REG_FP[DECODE_FS],COP2_REG_FP[DECODE_FT]); } -void P_VMSUBw( string& output ){strAppend(output, "vmsubw.%s %s, %s, %sw", dest_string(),COP2_REG_FP[DECODE_FD], COP2_REG_FP[DECODE_FS],COP2_REG_FP[DECODE_FT]); } -void P_VMAXx( string& output ){strAppend(output, "vmaxx.%s %s, %s, %sx", dest_string(),COP2_REG_FP[DECODE_FD], COP2_REG_FP[DECODE_FS],COP2_REG_FP[DECODE_FT]); } -void P_VMAXy( string& output ){strAppend(output, "vmaxy.%s %s, %s, %sy", dest_string(),COP2_REG_FP[DECODE_FD], COP2_REG_FP[DECODE_FS],COP2_REG_FP[DECODE_FT]); } -void P_VMAXz( string& output ){strAppend(output, "vmaxz.%s %s, %s, %sz", dest_string(),COP2_REG_FP[DECODE_FD], COP2_REG_FP[DECODE_FS],COP2_REG_FP[DECODE_FT]); } -void P_VMAXw( string& output ){strAppend(output, "vmaxw.%s %s, %s, %sw", dest_string(),COP2_REG_FP[DECODE_FD], COP2_REG_FP[DECODE_FS],COP2_REG_FP[DECODE_FT]); } -void P_VMINIx( string& output ){strAppend(output, "vminix.%s %s, %s, %sx", dest_string(),COP2_REG_FP[DECODE_FD], COP2_REG_FP[DECODE_FS],COP2_REG_FP[DECODE_FT]); } -void P_VMINIy( string& output ){strAppend(output, "vminiy.%s %s, %s, %sy", dest_string(),COP2_REG_FP[DECODE_FD], COP2_REG_FP[DECODE_FS],COP2_REG_FP[DECODE_FT]); ;} -void P_VMINIz( string& output ){strAppend(output, "vminiz.%s %s, %s, %sz", dest_string(),COP2_REG_FP[DECODE_FD], COP2_REG_FP[DECODE_FS],COP2_REG_FP[DECODE_FT]); } -void P_VMINIw( string& output ){strAppend(output, "vminiw.%s %s, %s, %sw", dest_string(),COP2_REG_FP[DECODE_FD], COP2_REG_FP[DECODE_FS],COP2_REG_FP[DECODE_FT]); } -void P_VMULx( string& output ){strAppend(output,"vmulx.%s %s,%s,%sx", dest_string(),COP2_REG_FP[DECODE_FD], COP2_REG_FP[DECODE_FS],COP2_REG_FP[DECODE_FT]); } -void P_VMULy( string& output ){strAppend(output,"vmuly.%s %s,%s,%sy", dest_string(),COP2_REG_FP[DECODE_FD], COP2_REG_FP[DECODE_FS],COP2_REG_FP[DECODE_FT]); } -void P_VMULz( string& output ){strAppend(output,"vmulz.%s %s,%s,%sz", dest_string(),COP2_REG_FP[DECODE_FD], COP2_REG_FP[DECODE_FS],COP2_REG_FP[DECODE_FT]); } -void P_VMULw( string& output ){strAppend(output,"vmulw.%s %s,%s,%sw", dest_string(),COP2_REG_FP[DECODE_FD], COP2_REG_FP[DECODE_FS],COP2_REG_FP[DECODE_FT]); } -void P_VMULq( string& output ){strAppend(output,"vmulq.%s %s,%s,Q",dest_string(),COP2_REG_FP[DECODE_FD], COP2_REG_FP[DECODE_FS]); } -void P_VMAXi( string& output ){strAppend(output,"vmaxi.%s %s,%s,I",dest_string(),COP2_REG_FP[DECODE_FD], COP2_REG_FP[DECODE_FS]); } -void P_VMULi( string& output ){strAppend(output,"vmuli.%s %s,%s,I",dest_string(),COP2_REG_FP[DECODE_FD], COP2_REG_FP[DECODE_FS]); } -void P_VMINIi( string& output ){strAppend(output,"vminii.%s %s,%s,I",dest_string(),COP2_REG_FP[DECODE_FD], COP2_REG_FP[DECODE_FS]); } -void P_VADDq( string& output ){strAppend(output,"vaddq.%s %s,%s,Q",dest_string(),COP2_REG_FP[DECODE_FD], COP2_REG_FP[DECODE_FS]); } -void P_VMADDq( string& output ){strAppend(output,"vmaddq.%s %s,%s,Q",dest_string(),COP2_REG_FP[DECODE_FD], COP2_REG_FP[DECODE_FS]); } -void P_VADDi( string& output ){strAppend(output,"vaddi.%s %s,%s,I",dest_string(),COP2_REG_FP[DECODE_FD], COP2_REG_FP[DECODE_FS]); } -void P_VMADDi( string& output ){strAppend(output,"vmaddi.%s %s,%s,I",dest_string(),COP2_REG_FP[DECODE_FD], COP2_REG_FP[DECODE_FS]); } -void P_VSUBq( string& output ){strAppend(output,"vsubq.%s %s,%s,Q",dest_string(),COP2_REG_FP[DECODE_FD], COP2_REG_FP[DECODE_FS]); } -void P_VMSUBq( string& output ){strAppend(output,"vmsubq.%s %s,%s,Q",dest_string(),COP2_REG_FP[DECODE_FD], COP2_REG_FP[DECODE_FS]); } -void P_VSUbi( string& output ){strAppend(output,"vsubi.%s %s,%s,I",dest_string(),COP2_REG_FP[DECODE_FD], COP2_REG_FP[DECODE_FS]); } -void P_VMSUBi( string& output ){strAppend(output,"vmsubi.%s %s,%s,I",dest_string(),COP2_REG_FP[DECODE_FD], COP2_REG_FP[DECODE_FS]); } -void P_VADD( string& output ){strAppend(output, "vadd.%s %s, %s, %s", dest_string(),COP2_REG_FP[DECODE_FD], COP2_REG_FP[DECODE_FS],COP2_REG_FP[DECODE_FT]); } -void P_VMADD( string& output ){strAppend(output, "vmadd.%s %s, %s, %s", dest_string(),COP2_REG_FP[DECODE_FD], COP2_REG_FP[DECODE_FS],COP2_REG_FP[DECODE_FT]); } -void P_VMUL( string& output ){strAppend(output, "vmul.%s %s, %s, %s", dest_string(),COP2_REG_FP[DECODE_FD], COP2_REG_FP[DECODE_FS],COP2_REG_FP[DECODE_FT]); } -void P_VMAX( string& output ){strAppend(output, "vmax.%s %s, %s, %s", dest_string(),COP2_REG_FP[DECODE_FD], COP2_REG_FP[DECODE_FS],COP2_REG_FP[DECODE_FT]); } -void P_VSUB( string& output ){strAppend(output, "vsub.%s %s, %s, %s", dest_string(),COP2_REG_FP[DECODE_FD], COP2_REG_FP[DECODE_FS],COP2_REG_FP[DECODE_FT]); } -void P_VMSUB( string& output ){strAppend(output, "vmsub.%s %s, %s, %s", dest_string(),COP2_REG_FP[DECODE_FD], COP2_REG_FP[DECODE_FS],COP2_REG_FP[DECODE_FT]); } -void P_VOPMSUB( string& output ){strAppend(output, "vopmsub.xyz %s, %s, %s", COP2_REG_FP[DECODE_FD], COP2_REG_FP[DECODE_FS],COP2_REG_FP[DECODE_FT]); } -void P_VMINI( string& output ){strAppend(output, "vmini.%s %s, %s, %s", dest_string(),COP2_REG_FP[DECODE_FD], COP2_REG_FP[DECODE_FS],COP2_REG_FP[DECODE_FT]); } -void P_VIADD( string& output ){strAppend(output,"viadd %s, %s, %s", COP2_REG_CTL[DECODE_SA], COP2_REG_CTL[DECODE_FS], COP2_REG_CTL[DECODE_FT]);} -void P_VISUB( string& output ){strAppend(output,"visub %s, %s, %s", COP2_REG_CTL[DECODE_SA], COP2_REG_CTL[DECODE_FS], COP2_REG_CTL[DECODE_FT]);} -void P_VIADDI( string& output ){strAppend(output,"viaddi %s, %s, 0x%x", COP2_REG_CTL[DECODE_FT], COP2_REG_CTL[DECODE_FS], DECODE_SA);} -void P_VIAND( string& output ){strAppend(output,"viand %s, %s, %s", COP2_REG_CTL[DECODE_SA], COP2_REG_CTL[DECODE_FS], COP2_REG_CTL[DECODE_FT]);} -void P_VIOR( string& output ){strAppend(output,"vior %s, %s, %s", COP2_REG_CTL[DECODE_SA], COP2_REG_CTL[DECODE_FS], COP2_REG_CTL[DECODE_FT]);} -void P_VCALLMS( string& output ){output.append("vcallms");} -void P_CALLMSR( string& output ){output.append("callmsr");} +void P_VADDx( string& output ){_sap("vaddx.%s %s, %s, %sx") dest_string(),COP2_REG_FP[DECODE_FD], COP2_REG_FP[DECODE_FS],COP2_REG_FP[DECODE_FT]); } +void P_VADDy( string& output ){_sap("vaddy.%s %s, %s, %sy") dest_string(),COP2_REG_FP[DECODE_FD], COP2_REG_FP[DECODE_FS],COP2_REG_FP[DECODE_FT]); } +void P_VADDz( string& output ){_sap("vaddz.%s %s, %s, %sz") dest_string(),COP2_REG_FP[DECODE_FD], COP2_REG_FP[DECODE_FS],COP2_REG_FP[DECODE_FT]); } +void P_VADDw( string& output ){_sap("vaddw.%s %s, %s, %sw") dest_string(),COP2_REG_FP[DECODE_FD], COP2_REG_FP[DECODE_FS],COP2_REG_FP[DECODE_FT]); } +void P_VSUBx( string& output ){_sap("vsubx.%s %s, %s, %sx") dest_string(),COP2_REG_FP[DECODE_FD], COP2_REG_FP[DECODE_FS],COP2_REG_FP[DECODE_FT]); } +void P_VSUBy( string& output ){_sap("vsuby.%s %s, %s, %sy") dest_string(),COP2_REG_FP[DECODE_FD], COP2_REG_FP[DECODE_FS],COP2_REG_FP[DECODE_FT]); } +void P_VSUBz( string& output ){_sap("vsubz.%s %s, %s, %sz") dest_string(),COP2_REG_FP[DECODE_FD], COP2_REG_FP[DECODE_FS],COP2_REG_FP[DECODE_FT]); } +void P_VSUBw( string& output ){_sap("vsubw.%s %s, %s, %sw") dest_string(),COP2_REG_FP[DECODE_FD], COP2_REG_FP[DECODE_FS],COP2_REG_FP[DECODE_FT]); } +void P_VMADDx( string& output ){_sap("vmaddx.%s %s, %s, %sx") dest_string(),COP2_REG_FP[DECODE_FD], COP2_REG_FP[DECODE_FS],COP2_REG_FP[DECODE_FT]); } +void P_VMADDy( string& output ){_sap("vmaddy.%s %s, %s, %sy") dest_string(),COP2_REG_FP[DECODE_FD], COP2_REG_FP[DECODE_FS],COP2_REG_FP[DECODE_FT]); } +void P_VMADDz( string& output ){_sap("vmaddz.%s %s, %s, %sz") dest_string(),COP2_REG_FP[DECODE_FD], COP2_REG_FP[DECODE_FS],COP2_REG_FP[DECODE_FT]); } +void P_VMADDw( string& output ){_sap("vmaddw.%s %s, %s, %sw") dest_string(),COP2_REG_FP[DECODE_FD], COP2_REG_FP[DECODE_FS],COP2_REG_FP[DECODE_FT]); } +void P_VMSUBx( string& output ){_sap("vmsubx.%s %s, %s, %sx") dest_string(),COP2_REG_FP[DECODE_FD], COP2_REG_FP[DECODE_FS],COP2_REG_FP[DECODE_FT]); } +void P_VMSUBy( string& output ){_sap("vmsuby.%s %s, %s, %sy") dest_string(),COP2_REG_FP[DECODE_FD], COP2_REG_FP[DECODE_FS],COP2_REG_FP[DECODE_FT]); } +void P_VMSUBz( string& output ){_sap("vmsubz.%s %s, %s, %sz") dest_string(),COP2_REG_FP[DECODE_FD], COP2_REG_FP[DECODE_FS],COP2_REG_FP[DECODE_FT]); } +void P_VMSUBw( string& output ){_sap("vmsubw.%s %s, %s, %sw") dest_string(),COP2_REG_FP[DECODE_FD], COP2_REG_FP[DECODE_FS],COP2_REG_FP[DECODE_FT]); } +void P_VMAXx( string& output ){_sap("vmaxx.%s %s, %s, %sx") dest_string(),COP2_REG_FP[DECODE_FD], COP2_REG_FP[DECODE_FS],COP2_REG_FP[DECODE_FT]); } +void P_VMAXy( string& output ){_sap("vmaxy.%s %s, %s, %sy") dest_string(),COP2_REG_FP[DECODE_FD], COP2_REG_FP[DECODE_FS],COP2_REG_FP[DECODE_FT]); } +void P_VMAXz( string& output ){_sap("vmaxz.%s %s, %s, %sz") dest_string(),COP2_REG_FP[DECODE_FD], COP2_REG_FP[DECODE_FS],COP2_REG_FP[DECODE_FT]); } +void P_VMAXw( string& output ){_sap("vmaxw.%s %s, %s, %sw") dest_string(),COP2_REG_FP[DECODE_FD], COP2_REG_FP[DECODE_FS],COP2_REG_FP[DECODE_FT]); } +void P_VMINIx( string& output ){_sap("vminix.%s %s, %s, %sx") dest_string(),COP2_REG_FP[DECODE_FD], COP2_REG_FP[DECODE_FS],COP2_REG_FP[DECODE_FT]); } +void P_VMINIy( string& output ){_sap("vminiy.%s %s, %s, %sy") dest_string(),COP2_REG_FP[DECODE_FD], COP2_REG_FP[DECODE_FS],COP2_REG_FP[DECODE_FT]); ;} +void P_VMINIz( string& output ){_sap("vminiz.%s %s, %s, %sz") dest_string(),COP2_REG_FP[DECODE_FD], COP2_REG_FP[DECODE_FS],COP2_REG_FP[DECODE_FT]); } +void P_VMINIw( string& output ){_sap("vminiw.%s %s, %s, %sw") dest_string(),COP2_REG_FP[DECODE_FD], COP2_REG_FP[DECODE_FS],COP2_REG_FP[DECODE_FT]); } +void P_VMULx( string& output ){_sap("vmulx.%s %s,%s,%sx") dest_string(),COP2_REG_FP[DECODE_FD], COP2_REG_FP[DECODE_FS],COP2_REG_FP[DECODE_FT]); } +void P_VMULy( string& output ){_sap("vmuly.%s %s,%s,%sy") dest_string(),COP2_REG_FP[DECODE_FD], COP2_REG_FP[DECODE_FS],COP2_REG_FP[DECODE_FT]); } +void P_VMULz( string& output ){_sap("vmulz.%s %s,%s,%sz") dest_string(),COP2_REG_FP[DECODE_FD], COP2_REG_FP[DECODE_FS],COP2_REG_FP[DECODE_FT]); } +void P_VMULw( string& output ){_sap("vmulw.%s %s,%s,%sw") dest_string(),COP2_REG_FP[DECODE_FD], COP2_REG_FP[DECODE_FS],COP2_REG_FP[DECODE_FT]); } +void P_VMULq( string& output ){_sap("vmulq.%s %s,%s,Q") dest_string(),COP2_REG_FP[DECODE_FD], COP2_REG_FP[DECODE_FS]); } +void P_VMAXi( string& output ){_sap("vmaxi.%s %s,%s,I") dest_string(),COP2_REG_FP[DECODE_FD], COP2_REG_FP[DECODE_FS]); } +void P_VMULi( string& output ){_sap("vmuli.%s %s,%s,I") dest_string(),COP2_REG_FP[DECODE_FD], COP2_REG_FP[DECODE_FS]); } +void P_VMINIi( string& output ){_sap("vminii.%s %s,%s,I") dest_string(),COP2_REG_FP[DECODE_FD], COP2_REG_FP[DECODE_FS]); } +void P_VADDq( string& output ){_sap("vaddq.%s %s,%s,Q") dest_string(),COP2_REG_FP[DECODE_FD], COP2_REG_FP[DECODE_FS]); } +void P_VMADDq( string& output ){_sap("vmaddq.%s %s,%s,Q") dest_string(),COP2_REG_FP[DECODE_FD], COP2_REG_FP[DECODE_FS]); } +void P_VADDi( string& output ){_sap("vaddi.%s %s,%s,I") dest_string(),COP2_REG_FP[DECODE_FD], COP2_REG_FP[DECODE_FS]); } +void P_VMADDi( string& output ){_sap("vmaddi.%s %s,%s,I") dest_string(),COP2_REG_FP[DECODE_FD], COP2_REG_FP[DECODE_FS]); } +void P_VSUBq( string& output ){_sap("vsubq.%s %s,%s,Q") dest_string(),COP2_REG_FP[DECODE_FD], COP2_REG_FP[DECODE_FS]); } +void P_VMSUBq( string& output ){_sap("vmsubq.%s %s,%s,Q") dest_string(),COP2_REG_FP[DECODE_FD], COP2_REG_FP[DECODE_FS]); } +void P_VSUbi( string& output ){_sap("vsubi.%s %s,%s,I") dest_string(),COP2_REG_FP[DECODE_FD], COP2_REG_FP[DECODE_FS]); } +void P_VMSUBi( string& output ){_sap("vmsubi.%s %s,%s,I") dest_string(),COP2_REG_FP[DECODE_FD], COP2_REG_FP[DECODE_FS]); } +void P_VADD( string& output ){_sap("vadd.%s %s, %s, %s") dest_string(),COP2_REG_FP[DECODE_FD], COP2_REG_FP[DECODE_FS],COP2_REG_FP[DECODE_FT]); } +void P_VMADD( string& output ){_sap("vmadd.%s %s, %s, %s") dest_string(),COP2_REG_FP[DECODE_FD], COP2_REG_FP[DECODE_FS],COP2_REG_FP[DECODE_FT]); } +void P_VMUL( string& output ){_sap("vmul.%s %s, %s, %s") dest_string(),COP2_REG_FP[DECODE_FD], COP2_REG_FP[DECODE_FS],COP2_REG_FP[DECODE_FT]); } +void P_VMAX( string& output ){_sap("vmax.%s %s, %s, %s") dest_string(),COP2_REG_FP[DECODE_FD], COP2_REG_FP[DECODE_FS],COP2_REG_FP[DECODE_FT]); } +void P_VSUB( string& output ){_sap("vsub.%s %s, %s, %s") dest_string(),COP2_REG_FP[DECODE_FD], COP2_REG_FP[DECODE_FS],COP2_REG_FP[DECODE_FT]); } +void P_VMSUB( string& output ){_sap("vmsub.%s %s, %s, %s") dest_string(),COP2_REG_FP[DECODE_FD], COP2_REG_FP[DECODE_FS],COP2_REG_FP[DECODE_FT]); } +void P_VOPMSUB( string& output ){_sap("vopmsub.xyz %s, %s, %s") COP2_REG_FP[DECODE_FD], COP2_REG_FP[DECODE_FS],COP2_REG_FP[DECODE_FT]); } +void P_VMINI( string& output ){_sap("vmini.%s %s, %s, %s") dest_string(),COP2_REG_FP[DECODE_FD], COP2_REG_FP[DECODE_FS],COP2_REG_FP[DECODE_FT]); } +void P_VIADD( string& output ){_sap("viadd %s, %s, %s") COP2_REG_CTL[DECODE_SA], COP2_REG_CTL[DECODE_FS], COP2_REG_CTL[DECODE_FT]);} +void P_VISUB( string& output ){_sap("visub %s, %s, %s") COP2_REG_CTL[DECODE_SA], COP2_REG_CTL[DECODE_FS], COP2_REG_CTL[DECODE_FT]);} +void P_VIADDI( string& output ){_sap("viaddi %s, %s, 0x%x") COP2_REG_CTL[DECODE_FT], COP2_REG_CTL[DECODE_FS], DECODE_SA);} +void P_VIAND( string& output ){_sap("viand %s, %s, %s") COP2_REG_CTL[DECODE_SA], COP2_REG_CTL[DECODE_FS], COP2_REG_CTL[DECODE_FT]);} +void P_VIOR( string& output ){_sap("vior %s, %s, %s") COP2_REG_CTL[DECODE_SA], COP2_REG_CTL[DECODE_FS], COP2_REG_CTL[DECODE_FT]);} +void P_VCALLMS( string& output ){output += "vcallms";} +void P_CALLMSR( string& output ){output += "callmsr";} //***********************************END OF SPECIAL1 VU0 TABLE***************************** //******************************SPECIAL2 VUO TABLE***************************************** -void P_VADDAx( string& output ){strAppend(output,"vaddax.%s ACC,%s,%sx",dest_string(),COP2_REG_FP[DECODE_FS],COP2_REG_FP[DECODE_FT]);} -void P_VADDAy( string& output ){strAppend(output,"vadday.%s ACC,%s,%sy",dest_string(),COP2_REG_FP[DECODE_FS],COP2_REG_FP[DECODE_FT]);} -void P_VADDAz( string& output ){strAppend(output,"vaddaz.%s ACC,%s,%sz",dest_string(),COP2_REG_FP[DECODE_FS],COP2_REG_FP[DECODE_FT]);} -void P_VADDAw( string& output ){strAppend(output,"vaddaw.%s ACC,%s,%sw",dest_string(),COP2_REG_FP[DECODE_FS],COP2_REG_FP[DECODE_FT]);} -void P_VSUBAx( string& output ){strAppend(output,"vsubax.%s ACC,%s,%sx",dest_string(),COP2_REG_FP[DECODE_FS],COP2_REG_FP[DECODE_FT]);} -void P_VSUBAy( string& output ){strAppend(output,"vsubay.%s ACC,%s,%sy",dest_string(),COP2_REG_FP[DECODE_FS],COP2_REG_FP[DECODE_FT]);} -void P_VSUBAz( string& output ){strAppend(output,"vsubaz.%s ACC,%s,%sz",dest_string(),COP2_REG_FP[DECODE_FS],COP2_REG_FP[DECODE_FT]);} -void P_VSUBAw( string& output ){strAppend(output,"vsubaw.%s ACC,%s,%sw",dest_string(),COP2_REG_FP[DECODE_FS],COP2_REG_FP[DECODE_FT]);} -void P_VMADDAx( string& output ){strAppend(output,"vmaddax.%s ACC,%s,%sx",dest_string(),COP2_REG_FP[DECODE_FS],COP2_REG_FP[DECODE_FT]);} -void P_VMADDAy( string& output ){strAppend(output,"vmadday.%s ACC,%s,%sy",dest_string(),COP2_REG_FP[DECODE_FS],COP2_REG_FP[DECODE_FT]);} -void P_VMADDAz( string& output ){strAppend(output,"vmaddaz.%s ACC,%s,%sz",dest_string(),COP2_REG_FP[DECODE_FS],COP2_REG_FP[DECODE_FT]);} -void P_VMADDAw( string& output ){strAppend(output,"vmaddaw.%s ACC,%s,%sw",dest_string(),COP2_REG_FP[DECODE_FS],COP2_REG_FP[DECODE_FT]);} -void P_VMSUBAx( string& output ){strAppend(output,"vmsubax.%s ACC,%s,%sx",dest_string(),COP2_REG_FP[DECODE_FS],COP2_REG_FP[DECODE_FT]);} -void P_VMSUBAy( string& output ){strAppend(output,"vmsubay.%s ACC,%s,%sy",dest_string(),COP2_REG_FP[DECODE_FS],COP2_REG_FP[DECODE_FT]);} -void P_VMSUBAz( string& output ){strAppend(output,"vmsubaz.%s ACC,%s,%sz",dest_string(),COP2_REG_FP[DECODE_FS],COP2_REG_FP[DECODE_FT]);} -void P_VMSUBAw( string& output ){strAppend(output,"vmsubaw.%s ACC,%s,%sw",dest_string(),COP2_REG_FP[DECODE_FS],COP2_REG_FP[DECODE_FT]);} -void P_VITOF0( string& output ){strAppend(output, "vitof0.%s %s, %s", dest_string(),COP2_REG_FP[DECODE_FT], COP2_REG_FP[DECODE_FS]); } -void P_VITOF4( string& output ){strAppend(output, "vitof4.%s %s, %s", dest_string(),COP2_REG_FP[DECODE_FT], COP2_REG_FP[DECODE_FS]); } -void P_VITOF12( string& output ){strAppend(output, "vitof12.%s %s, %s", dest_string(),COP2_REG_FP[DECODE_FT], COP2_REG_FP[DECODE_FS]); } -void P_VITOF15( string& output ){strAppend(output, "vitof15.%s %s, %s", dest_string(),COP2_REG_FP[DECODE_FT], COP2_REG_FP[DECODE_FS]); } -void P_VFTOI0( string& output ) {strAppend(output, "vftoi0.%s %s, %s", dest_string(),COP2_REG_FP[DECODE_FT], COP2_REG_FP[DECODE_FS]); } -void P_VFTOI4( string& output ) {strAppend(output, "vftoi4.%s %s, %s", dest_string(),COP2_REG_FP[DECODE_FT], COP2_REG_FP[DECODE_FS]); } -void P_VFTOI12( string& output ){strAppend(output, "vftoi12.%s %s, %s", dest_string(),COP2_REG_FP[DECODE_FT], COP2_REG_FP[DECODE_FS]); } -void P_VFTOI15( string& output ){strAppend(output, "vftoi15.%s %s, %s", dest_string(),COP2_REG_FP[DECODE_FT], COP2_REG_FP[DECODE_FS]); } -void P_VMULAx( string& output ){strAppend(output,"vmulax.%s ACC,%s,%sx",dest_string(),COP2_REG_FP[DECODE_FS],COP2_REG_FP[DECODE_FT]);} -void P_VMULAy( string& output ){strAppend(output,"vmulay.%s ACC,%s,%sy",dest_string(),COP2_REG_FP[DECODE_FS],COP2_REG_FP[DECODE_FT]);} -void P_VMULAz( string& output ){strAppend(output,"vmulaz.%s ACC,%s,%sz",dest_string(),COP2_REG_FP[DECODE_FS],COP2_REG_FP[DECODE_FT]);} -void P_VMULAw( string& output ){strAppend(output,"vmulaw.%s ACC,%s,%sw",dest_string(),COP2_REG_FP[DECODE_FS],COP2_REG_FP[DECODE_FT]);} -void P_VMULAq( string& output ){strAppend(output,"vmulaq.%s ACC %s, Q" ,dest_string(), COP2_REG_FP[DECODE_FS]); } -void P_VABS( string& output ){strAppend(output, "vabs.%s %s, %s", dest_string(),COP2_REG_FP[DECODE_FT], COP2_REG_FP[DECODE_FS]);} -void P_VMULAi( string& output ){strAppend(output,"vmulaq.%s ACC %s, I" ,dest_string(), COP2_REG_FP[DECODE_FS]); } -void P_VCLIPw( string& output ){strAppend(output,"vclip %sxyz, %sw", COP2_REG_FP[DECODE_FS], COP2_REG_FP[DECODE_FT]);} -void P_VADDAq( string& output ){strAppend(output,"vaddaq.%s ACC %s, Q" ,dest_string(), COP2_REG_FP[DECODE_FS]); } -void P_VMADDAq( string& output ){strAppend(output,"vmaddaq.%s ACC %s, Q" ,dest_string(), COP2_REG_FP[DECODE_FS]); } -void P_VADDAi( string& output ){strAppend(output,"vaddai.%s ACC %s, I" ,dest_string(), COP2_REG_FP[DECODE_FS]); } -void P_VMADDAi( string& output ){strAppend(output,"vmaddai.%s ACC %s, Q" ,dest_string(), COP2_REG_FP[DECODE_FS]); } -void P_VSUBAq( string& output ){strAppend(output,"vsubaq.%s ACC %s, Q" ,dest_string(), COP2_REG_FP[DECODE_FS]); } -void P_VMSUBAq( string& output ){strAppend(output,"vmsubaq.%s ACC %s, Q" ,dest_string(), COP2_REG_FP[DECODE_FS]); } -void P_VSUBAi( string& output ){strAppend(output,"vsubai.%s ACC %s, I" ,dest_string(), COP2_REG_FP[DECODE_FS]); } -void P_VMSUBAi( string& output ){strAppend(output,"vmsubai.%s ACC %s, I" ,dest_string(), COP2_REG_FP[DECODE_FS]); } -void P_VADDA( string& output ){strAppend(output,"vadda.%s ACC %s, %s" ,dest_string(), COP2_REG_FP[DECODE_FS],COP2_REG_FP[DECODE_FT]); } -void P_VMADDA( string& output ){strAppend(output,"vmadda.%s ACC %s, %s" ,dest_string(), COP2_REG_FP[DECODE_FS],COP2_REG_FP[DECODE_FT]); } -void P_VMULA( string& output ){strAppend(output,"vmula.%s ACC %s, %s" ,dest_string(), COP2_REG_FP[DECODE_FS],COP2_REG_FP[DECODE_FT]); } -void P_VSUBA( string& output ){strAppend(output,"vsuba.%s ACC %s, %s" ,dest_string(), COP2_REG_FP[DECODE_FS],COP2_REG_FP[DECODE_FT]); } -void P_VMSUBA( string& output ){strAppend(output,"vmsuba.%s ACC %s, %s" ,dest_string(), COP2_REG_FP[DECODE_FS],COP2_REG_FP[DECODE_FT]); } -void P_VOPMULA( string& output ){strAppend(output,"vopmula.xyz %sxyz, %sxyz" ,COP2_REG_FP[DECODE_FS],COP2_REG_FP[DECODE_FT]); } -void P_VNOP( string& output ){output.append("vnop");} -void P_VMONE( string& output ){strAppend(output,"vmove.%s, %s, %s" ,dest_string(), COP2_REG_FP[DECODE_FT],COP2_REG_FP[DECODE_FS]); } -void P_VMR32( string& output ){strAppend(output,"vmr32.%s, %s, %s" ,dest_string(), COP2_REG_FP[DECODE_FT],COP2_REG_FP[DECODE_FS]); } -void P_VLQI( string& output ){strAppend(output,"vlqi %s%s, (%s++)", COP2_REG_FP[DECODE_FT], dest_string(), COP2_REG_CTL[DECODE_FS]);} -void P_VSQI( string& output ){strAppend(output,"vsqi %s%s, (%s++)", COP2_REG_FP[DECODE_FS], dest_string(), COP2_REG_CTL[DECODE_FT]);} -void P_VLQD( string& output ){strAppend(output,"vlqd %s%s, (--%s)", COP2_REG_FP[DECODE_FT], dest_string(), COP2_REG_CTL[DECODE_FS]);} -void P_VSQD( string& output ){strAppend(output,"vsqd %s%s, (--%s)", COP2_REG_FP[DECODE_FS], dest_string(), COP2_REG_CTL[DECODE_FT]);} -void P_VDIV( string& output ){strAppend(output,"vdiv Q, %s%c, %s%c", COP2_REG_FP[DECODE_FS], dest_fsf(), COP2_REG_FP[DECODE_FT], dest_ftf());} -void P_VSQRT( string& output ){strAppend(output,"vsqrt Q, %s%c", COP2_REG_FP[DECODE_FT], dest_ftf());} -void P_VRSQRT( string& output ){strAppend(output,"vrsqrt Q, %s%c, %s%c", COP2_REG_FP[DECODE_FS], dest_fsf(), COP2_REG_FP[DECODE_FT], dest_ftf());} -void P_VWAITQ( string& output ){strAppend(output,"vwaitq");} -void P_VMTIR( string& output ){strAppend(output,"vmtir %s, %s%c", COP2_REG_CTL[DECODE_FT], COP2_REG_FP[DECODE_FS], dest_fsf());} -void P_VMFIR( string& output ){strAppend(output,"vmfir %s%c, %s", COP2_REG_FP[DECODE_FT], dest_string(), COP2_REG_CTL[DECODE_FS]);} -void P_VILWR( string& output ){strAppend(output,"vilwr %s, (%s)%s", COP2_REG_CTL[DECODE_FT], COP2_REG_CTL[DECODE_FS], dest_string());} -void P_VISWR( string& output ){strAppend(output,"viswr %s, (%s)%s", COP2_REG_CTL[DECODE_FT], COP2_REG_CTL[DECODE_FS], dest_string());} -void P_VRNEXT( string& output ){strAppend(output,"vrnext %s%s, R", COP2_REG_CTL[DECODE_FT], dest_string());} -void P_VRGET( string& output ){strAppend(output,"vrget %s%s, R", COP2_REG_CTL[DECODE_FT], dest_string());} -void P_VRINIT( string& output ){strAppend(output,"vrinit R, %s%s", COP2_REG_CTL[DECODE_FS], dest_string());} -void P_VRXOR( string& output ){strAppend(output,"vrxor R, %s%s", COP2_REG_CTL[DECODE_FS], dest_string());} +void P_VADDAx( string& output ){_sap("vaddax.%s ACC,%s,%sx") dest_string(),COP2_REG_FP[DECODE_FS],COP2_REG_FP[DECODE_FT]);} +void P_VADDAy( string& output ){_sap("vadday.%s ACC,%s,%sy") dest_string(),COP2_REG_FP[DECODE_FS],COP2_REG_FP[DECODE_FT]);} +void P_VADDAz( string& output ){_sap("vaddaz.%s ACC,%s,%sz") dest_string(),COP2_REG_FP[DECODE_FS],COP2_REG_FP[DECODE_FT]);} +void P_VADDAw( string& output ){_sap("vaddaw.%s ACC,%s,%sw") dest_string(),COP2_REG_FP[DECODE_FS],COP2_REG_FP[DECODE_FT]);} +void P_VSUBAx( string& output ){_sap("vsubax.%s ACC,%s,%sx") dest_string(),COP2_REG_FP[DECODE_FS],COP2_REG_FP[DECODE_FT]);} +void P_VSUBAy( string& output ){_sap("vsubay.%s ACC,%s,%sy") dest_string(),COP2_REG_FP[DECODE_FS],COP2_REG_FP[DECODE_FT]);} +void P_VSUBAz( string& output ){_sap("vsubaz.%s ACC,%s,%sz") dest_string(),COP2_REG_FP[DECODE_FS],COP2_REG_FP[DECODE_FT]);} +void P_VSUBAw( string& output ){_sap("vsubaw.%s ACC,%s,%sw") dest_string(),COP2_REG_FP[DECODE_FS],COP2_REG_FP[DECODE_FT]);} +void P_VMADDAx( string& output ){_sap("vmaddax.%s ACC,%s,%sx") dest_string(),COP2_REG_FP[DECODE_FS],COP2_REG_FP[DECODE_FT]);} +void P_VMADDAy( string& output ){_sap("vmadday.%s ACC,%s,%sy") dest_string(),COP2_REG_FP[DECODE_FS],COP2_REG_FP[DECODE_FT]);} +void P_VMADDAz( string& output ){_sap("vmaddaz.%s ACC,%s,%sz") dest_string(),COP2_REG_FP[DECODE_FS],COP2_REG_FP[DECODE_FT]);} +void P_VMADDAw( string& output ){_sap("vmaddaw.%s ACC,%s,%sw") dest_string(),COP2_REG_FP[DECODE_FS],COP2_REG_FP[DECODE_FT]);} +void P_VMSUBAx( string& output ){_sap("vmsubax.%s ACC,%s,%sx") dest_string(),COP2_REG_FP[DECODE_FS],COP2_REG_FP[DECODE_FT]);} +void P_VMSUBAy( string& output ){_sap("vmsubay.%s ACC,%s,%sy") dest_string(),COP2_REG_FP[DECODE_FS],COP2_REG_FP[DECODE_FT]);} +void P_VMSUBAz( string& output ){_sap("vmsubaz.%s ACC,%s,%sz") dest_string(),COP2_REG_FP[DECODE_FS],COP2_REG_FP[DECODE_FT]);} +void P_VMSUBAw( string& output ){_sap("vmsubaw.%s ACC,%s,%sw") dest_string(),COP2_REG_FP[DECODE_FS],COP2_REG_FP[DECODE_FT]);} +void P_VITOF0( string& output ){_sap("vitof0.%s %s, %s") dest_string(),COP2_REG_FP[DECODE_FT], COP2_REG_FP[DECODE_FS]); } +void P_VITOF4( string& output ){_sap("vitof4.%s %s, %s") dest_string(),COP2_REG_FP[DECODE_FT], COP2_REG_FP[DECODE_FS]); } +void P_VITOF12( string& output ){_sap("vitof12.%s %s, %s") dest_string(),COP2_REG_FP[DECODE_FT], COP2_REG_FP[DECODE_FS]); } +void P_VITOF15( string& output ){_sap("vitof15.%s %s, %s") dest_string(),COP2_REG_FP[DECODE_FT], COP2_REG_FP[DECODE_FS]); } +void P_VFTOI0( string& output ) {_sap("vftoi0.%s %s, %s") dest_string(),COP2_REG_FP[DECODE_FT], COP2_REG_FP[DECODE_FS]); } +void P_VFTOI4( string& output ) {_sap("vftoi4.%s %s, %s") dest_string(),COP2_REG_FP[DECODE_FT], COP2_REG_FP[DECODE_FS]); } +void P_VFTOI12( string& output ){_sap("vftoi12.%s %s, %s") dest_string(),COP2_REG_FP[DECODE_FT], COP2_REG_FP[DECODE_FS]); } +void P_VFTOI15( string& output ){_sap("vftoi15.%s %s, %s") dest_string(),COP2_REG_FP[DECODE_FT], COP2_REG_FP[DECODE_FS]); } +void P_VMULAx( string& output ){_sap("vmulax.%s ACC,%s,%sx") dest_string(),COP2_REG_FP[DECODE_FS],COP2_REG_FP[DECODE_FT]);} +void P_VMULAy( string& output ){_sap("vmulay.%s ACC,%s,%sy") dest_string(),COP2_REG_FP[DECODE_FS],COP2_REG_FP[DECODE_FT]);} +void P_VMULAz( string& output ){_sap("vmulaz.%s ACC,%s,%sz") dest_string(),COP2_REG_FP[DECODE_FS],COP2_REG_FP[DECODE_FT]);} +void P_VMULAw( string& output ){_sap("vmulaw.%s ACC,%s,%sw") dest_string(),COP2_REG_FP[DECODE_FS],COP2_REG_FP[DECODE_FT]);} +void P_VMULAq( string& output ){_sap("vmulaq.%s ACC %s, Q") dest_string(), COP2_REG_FP[DECODE_FS]); } +void P_VABS( string& output ){_sap("vabs.%s %s, %s") dest_string(),COP2_REG_FP[DECODE_FT], COP2_REG_FP[DECODE_FS]);} +void P_VMULAi( string& output ){_sap("vmulaq.%s ACC %s, I") dest_string(), COP2_REG_FP[DECODE_FS]); } +void P_VCLIPw( string& output ){_sap("vclip %sxyz, %sw") COP2_REG_FP[DECODE_FS], COP2_REG_FP[DECODE_FT]);} +void P_VADDAq( string& output ){_sap("vaddaq.%s ACC %s, Q") dest_string(), COP2_REG_FP[DECODE_FS]); } +void P_VMADDAq( string& output ){_sap("vmaddaq.%s ACC %s, Q") dest_string(), COP2_REG_FP[DECODE_FS]); } +void P_VADDAi( string& output ){_sap("vaddai.%s ACC %s, I") dest_string(), COP2_REG_FP[DECODE_FS]); } +void P_VMADDAi( string& output ){_sap("vmaddai.%s ACC %s, Q") dest_string(), COP2_REG_FP[DECODE_FS]); } +void P_VSUBAq( string& output ){_sap("vsubaq.%s ACC %s, Q") dest_string(), COP2_REG_FP[DECODE_FS]); } +void P_VMSUBAq( string& output ){_sap("vmsubaq.%s ACC %s, Q") dest_string(), COP2_REG_FP[DECODE_FS]); } +void P_VSUBAi( string& output ){_sap("vsubai.%s ACC %s, I") dest_string(), COP2_REG_FP[DECODE_FS]); } +void P_VMSUBAi( string& output ){_sap("vmsubai.%s ACC %s, I") dest_string(), COP2_REG_FP[DECODE_FS]); } +void P_VADDA( string& output ){_sap("vadda.%s ACC %s, %s") dest_string(), COP2_REG_FP[DECODE_FS],COP2_REG_FP[DECODE_FT]); } +void P_VMADDA( string& output ){_sap("vmadda.%s ACC %s, %s") dest_string(), COP2_REG_FP[DECODE_FS],COP2_REG_FP[DECODE_FT]); } +void P_VMULA( string& output ){_sap("vmula.%s ACC %s, %s") dest_string(), COP2_REG_FP[DECODE_FS],COP2_REG_FP[DECODE_FT]); } +void P_VSUBA( string& output ){_sap("vsuba.%s ACC %s, %s") dest_string(), COP2_REG_FP[DECODE_FS],COP2_REG_FP[DECODE_FT]); } +void P_VMSUBA( string& output ){_sap("vmsuba.%s ACC %s, %s") dest_string(), COP2_REG_FP[DECODE_FS],COP2_REG_FP[DECODE_FT]); } +void P_VOPMULA( string& output ){_sap("vopmula.xyz %sxyz, %sxyz") COP2_REG_FP[DECODE_FS],COP2_REG_FP[DECODE_FT]); } +void P_VNOP( string& output ){output += "vnop";} +void P_VMONE( string& output ){_sap("vmove.%s, %s, %s") dest_string(), COP2_REG_FP[DECODE_FT],COP2_REG_FP[DECODE_FS]); } +void P_VMR32( string& output ){_sap("vmr32.%s, %s, %s") dest_string(), COP2_REG_FP[DECODE_FT],COP2_REG_FP[DECODE_FS]); } +void P_VLQI( string& output ){_sap("vlqi %s%s, (%s++)") COP2_REG_FP[DECODE_FT], dest_string(), COP2_REG_CTL[DECODE_FS]);} +void P_VSQI( string& output ){_sap("vsqi %s%s, (%s++)") COP2_REG_FP[DECODE_FS], dest_string(), COP2_REG_CTL[DECODE_FT]);} +void P_VLQD( string& output ){_sap("vlqd %s%s, (--%s)") COP2_REG_FP[DECODE_FT], dest_string(), COP2_REG_CTL[DECODE_FS]);} +void P_VSQD( string& output ){_sap("vsqd %s%s, (--%s)") COP2_REG_FP[DECODE_FS], dest_string(), COP2_REG_CTL[DECODE_FT]);} +void P_VDIV( string& output ){_sap("vdiv Q, %s%c, %s%c") COP2_REG_FP[DECODE_FS], dest_fsf(), COP2_REG_FP[DECODE_FT], dest_ftf());} +void P_VSQRT( string& output ){_sap("vsqrt Q, %s%c") COP2_REG_FP[DECODE_FT], dest_ftf());} +void P_VRSQRT( string& output ){_sap("vrsqrt Q, %s%c, %s%c") COP2_REG_FP[DECODE_FS], dest_fsf(), COP2_REG_FP[DECODE_FT], dest_ftf());} +void P_VWAITQ( string& output ){output += "vwaitq";} +void P_VMTIR( string& output ){_sap("vmtir %s, %s%c") COP2_REG_CTL[DECODE_FT], COP2_REG_FP[DECODE_FS], dest_fsf());} +void P_VMFIR( string& output ){_sap("vmfir %s%c, %s") COP2_REG_FP[DECODE_FT], dest_string(), COP2_REG_CTL[DECODE_FS]);} +void P_VILWR( string& output ){_sap("vilwr %s, (%s)%s") COP2_REG_CTL[DECODE_FT], COP2_REG_CTL[DECODE_FS], dest_string());} +void P_VISWR( string& output ){_sap("viswr %s, (%s)%s") COP2_REG_CTL[DECODE_FT], COP2_REG_CTL[DECODE_FS], dest_string());} +void P_VRNEXT( string& output ){_sap("vrnext %s%s, R") COP2_REG_CTL[DECODE_FT], dest_string());} +void P_VRGET( string& output ){_sap("vrget %s%s, R") COP2_REG_CTL[DECODE_FT], dest_string());} +void P_VRINIT( string& output ){_sap("vrinit R, %s%s") COP2_REG_CTL[DECODE_FS], dest_string());} +void P_VRXOR( string& output ){_sap("vrxor R, %s%s") COP2_REG_CTL[DECODE_FS], dest_string());} //************************************END OF SPECIAL2 VUO TABLE**************************** + +} \ No newline at end of file diff --git a/pcsx2/DebugTools/cpuopsDebug.cpp b/pcsx2/DebugTools/cpuopsDebug.cpp deleted file mode 100644 index 20293721ea..0000000000 --- a/pcsx2/DebugTools/cpuopsDebug.cpp +++ /dev/null @@ -1,1064 +0,0 @@ -/* Pcsx2 - Pc Ps2 Emulator - * Copyright (C) 2002-2008 Pcsx2 Team - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA - */ - -#include "PrecompiledHeader.h" - -#include "Common.h" -#include "Debug.h" -#include "cpuopsDebug.h" - -void UpdateR5900op() -{ - FILE *fp; - fp=fopen("cpuops.txt", "wt"); - fprintf(fp, "------------\n"); - fprintf(fp, "--R5900ops--\n"); - fprintf(fp, "------------\n"); - if(L_ADD>0) fprintf(fp, "Add %d\n", L_ADD); - if(L_ADDI>0) fprintf(fp, "Addi %d\n", L_ADDI); - if(L_ADDIU>0) fprintf(fp, "Addiu %d\n", L_ADDIU); - if(L_ADDU>0) fprintf(fp, "Addu %d\n", L_ADDU); - if(L_AND>0) fprintf(fp, "And %d\n", L_AND); - if(L_ANDI>0) fprintf(fp, "Andi %d\n", L_ANDI); - if(L_BEQ>0) fprintf(fp, "Beq %d\n", L_BEQ); - if(L_BEQL>0) fprintf(fp, "Beql %d\n", L_BEQL); - if(L_BGEZ>0) fprintf(fp, "Bgez %d\n", L_BGEZ); - if(L_BGEZAL>0) fprintf(fp, "Bgezal %d\n", L_BGEZAL); - if(L_BGEZALL>0) fprintf(fp, "Bgezall %d\n", L_BGEZALL); - if(L_BGEZL>0) fprintf(fp, "Bgezl %d\n", L_BGEZL); - if( L_BGTZ>0) fprintf(fp, "Bgtz %d\n", L_BGTZ); - if( L_BGTZL>0) fprintf(fp, "Bgtzl %d\n", L_BGTZL); - if(L_BLEZ>0) fprintf(fp, "Blez %d\n", L_BLEZ); - if(L_BLEZL>0) fprintf(fp, "blezl %d\n", L_BLEZL); - if(L_BLTZ>0) fprintf(fp, "bltz %d\n", L_BLTZ); - if(L_BLTZAL>0) fprintf(fp, "bltzal %d\n", L_BLTZAL); - if(L_BLTZALL>0) fprintf(fp, "bltzall %d\n", L_BLTZALL); - if(L_BLTZL>0) fprintf(fp, "bltzl %d\n", L_BLTZL); - if(L_BNE>0) fprintf(fp, "bne %d\n", L_BNE); - if(L_BNEL>0) fprintf(fp, "bnel %d\n", L_BNEL); - if(L_BREAK>0) fprintf(fp, "break %d\n", L_BREAK); - if(L_CACHE>0) fprintf(fp, "cache %d\n", L_CACHE); - if(L_DADD>0) fprintf(fp, "dadd %d\n", L_DADD); - if(L_DADDI>0) fprintf(fp, "daddi %d\n", L_DADDI); - if(L_DADDIU>0) fprintf(fp, "daddiu %d\n", L_DADDIU); - if(L_DADDU>0) fprintf(fp, "daddu %d\n", L_DADDU); - if(L_DIV>0) fprintf(fp, "div %d\n", L_DIV); - if(L_DIVU>0) fprintf(fp, "divu %d\n", L_DIVU); - if(L_DSLL>0) fprintf(fp, "dsll %d\n", L_DSLL); - if(L_DSLL32>0) fprintf(fp, "dsll32 %d\n", L_DSLL32); - if(L_DSLLV>0) fprintf(fp, "dsllv %d\n", L_DSLLV); - if(L_DSRA>0) fprintf(fp, "dsra %d\n", L_DSRA); - if(L_DSRA32>0) fprintf(fp, "dsra32 %d\n", L_DSRA32); - if(L_DSRAV>0) fprintf(fp, "dsrav %d\n", L_DSRAV); - if(L_DSRL>0) fprintf(fp, "dsrl %d\n", L_DSRL); - if(L_DSRL32>0) fprintf(fp, "dsr32 %d\n", L_DSRL32); - if(L_DSRLV>0) fprintf(fp, "dsrlv %d\n", L_DSRLV); - if(L_DSUB>0) fprintf(fp, "dsub %d\n", L_DSUB); - if(L_DSUBU>0) fprintf(fp, "dsubu %d\n", L_DSUBU); - if(L_J>0) fprintf(fp, "j %d\n", L_J); - if(L_JAL>0) fprintf(fp, "jal %d\n", L_JAL); - if(L_JALR>0) fprintf(fp, "jalr %d\n", L_JALR); - if(L_JR>0) fprintf(fp, "jr %d\n", L_JR); - if(L_LB>0) fprintf(fp, "lb %d\n", L_LB); - if(L_LBU>0) fprintf(fp, "lbu %d\n", L_LBU); - if(L_LD>0) fprintf(fp, "ld %d\n", L_LD); - if(L_LDL>0) fprintf(fp, "ldl %d\n", L_LDL); - if(L_LDR>0) fprintf(fp, "ldr %d\n", L_LDR); - if(L_LH>0) fprintf(fp, "lh %d\n", L_LH); - if(L_LHU>0) fprintf(fp, "lhu %d\n", L_LHU); - if(L_LQ>0) fprintf(fp, "lq %d\n", L_LQ); - if(L_LUI>0) fprintf(fp, "lui %d\n", L_LUI); - if(L_LW>0) fprintf(fp, "lw %d\n", L_LW); - if(L_LWL>0) fprintf(fp, "lwl %d\n", L_LWL); - if(L_LWR>0) fprintf(fp, "lwr %d\n", L_LWR); - if(L_LWU>0) fprintf(fp, "lwu %d\n", L_LWU); - if(L_MFHI>0) fprintf(fp, "mfhi %d\n", L_MFHI); - if(L_MFLO>0) fprintf(fp, "mflo %d\n", L_MFLO); - if(L_MFSA>0) fprintf(fp, "mfsa %d\n", L_MFSA); - if(L_MOVN>0) fprintf(fp, "movn %d\n", L_MOVN); - if(L_MOVZ>0) fprintf(fp, "movz %d\n", L_MOVZ); - if(L_MTHI>0) fprintf(fp, "mthi %d\n", L_MTHI); - if(L_MTLO>0) fprintf(fp, "mtlo %d\n", L_MTLO); - if(L_MTSA>0) fprintf(fp, "mtsa %d\n", L_MTSA); - if(L_MTSAB>0) fprintf(fp, "mtsab %d\n", L_MTSAB); - if(L_MTSAH>0) fprintf(fp, "mtsah %d\n", L_MTSAH); - if(L_MULT>0) fprintf(fp, "mult %d\n", L_MULT); - if(L_MULTU>0) fprintf(fp, "multu %d\n", L_MULTU); - if(L_NOR>0) fprintf(fp, "nor %d\n", L_NOR); - if(L_OR>0) fprintf(fp, "or %d\n", L_OR); - if(L_ORI>0) fprintf(fp, "ori %d\n", L_ORI); - if(L_PREF>0) fprintf(fp, "pref %d\n", L_PREF); - if(L_SB>0) fprintf(fp, "sb %d\n", L_SB); - if(L_SD>0) fprintf(fp, "sd %d\n", L_SD); - if(L_SDL>0) fprintf(fp, "sdl %d\n", L_SDL); - if(L_SDR>0) fprintf(fp, "sdr %d\n", L_SDR); - if(L_SH>0) fprintf(fp, "sh %d\n", L_SH); - if(L_SLL>0) fprintf(fp, "sll %d\n", L_SLL); - if(L_SLLV>0) fprintf(fp, "sllv %d\n", L_SLLV); - if(L_SLT>0) fprintf(fp, "slt %d\n", L_SLT); - if(L_SLTI>0) fprintf(fp, "slti %d\n", L_SLTI); - if(L_SLTIU>0) fprintf(fp, "sltiu %d\n", L_SLTIU); - if(L_SLTU>0) fprintf(fp, "sltu %d\n", L_SLTU); - if(L_SQ>0) fprintf(fp, "sq %d\n", L_SQ); - if(L_SRA>0) fprintf(fp, "sra %d\n", L_SRA); - if(L_SRAV>0) fprintf(fp, "srav %d\n", L_SRAV); - if(L_SRL>0) fprintf(fp, "srl %d\n", L_SRL); - if(L_SRLV>0) fprintf(fp, "srlv %d\n", L_SRLV); - if(L_SUB>0) fprintf(fp, "sub %d\n", L_SUB); - if(L_SUBU>0) fprintf(fp, "subu %d\n", L_SUBU); - if(L_SW>0) fprintf(fp, "sw %d\n", L_SW); - if(L_SWL>0) fprintf(fp, "swl %d\n", L_SWL); - if(L_SWR>0) fprintf(fp, "swr %d\n", L_SWR); - if(L_SYNC>0) fprintf(fp, "sync %d\n", L_SYNC); - if(L_SYSCALL>0) fprintf(fp, "syscall %d\n", L_SYSCALL); - if(L_TEQ>0) fprintf(fp, "teq %d\n", L_TEQ); - if(L_TEQI>0) fprintf(fp, "teqi %d\n", L_TEQI); - if(L_TGE>0) fprintf(fp, "tge %d\n", L_TGE); - if(L_TGEI>0) fprintf(fp, "tgei %d\n", L_TGEI); - if(L_TGEIU>0) fprintf(fp, "tgeiu %d\n", L_TGEIU); - if(L_TGEU>0) fprintf(fp, "tgeu %d\n", L_TGEU); - if(L_TLT>0) fprintf(fp, "tlt %d\n", L_TLT); - if(L_TLTI>0) fprintf(fp, "tlti %d\n", L_TLTI); - if(L_TLTIU>0) fprintf(fp, "tltiu %d\n", L_TLTIU); - if(L_TLTU>0) fprintf(fp, "tltu %d\n", L_TLTU); - if(L_TNE>0) fprintf(fp, "tne %d\n", L_TNE); - if(L_TNEI>0) fprintf(fp, "tnei %d\n", L_TNEI); - if(L_XOR>0) fprintf(fp, "xor %d\n", L_XOR); - if(L_XORI>0) fprintf(fp, "xori %d\n", L_XORI); - fprintf(fp, "------------\n"); - fprintf(fp, "--MMI ops--\n"); - fprintf(fp, "------------\n"); - if(L_DIV1>0) fprintf(fp, "div1 %d\n", L_DIV1); - if(L_DIVU1>0) fprintf(fp, "divu1 %d\n", L_DIVU1); - if(L_MADD>0) fprintf(fp, "madd %d\n", L_MADD); - if(L_MADD1>0) fprintf(fp, "madd1 %d\n", L_MADD1); - if(L_MADDU>0) fprintf(fp, "maddu %d\n", L_MADDU); - if(L_MADDU1>0) fprintf(fp, "maddu1 %d\n", L_MADDU1); - if(L_MFHI1>0) fprintf(fp, "mfhi1 %d\n", L_MFHI1); - if(L_MFLO1>0) fprintf(fp, "mflo1 %d\n", L_MFLO1); - if(L_MTHI1>0) fprintf(fp, "mthi1 %d\n", L_MTHI1); - if(L_MTLO1>0) fprintf(fp, "mtlo1 %d\n", L_MTLO1); - if(L_MULT1>0) fprintf(fp, "mult1 %d\n", L_MULT1); - if(L_MULTU1>0) fprintf(fp, "multu1 %d\n", L_MULTU1); - if(L_PABSH>0) fprintf(fp, "pabsh %d\n", L_PABSH); - if(L_PABSW>0) fprintf(fp, "pabsw %d\n", L_PABSW); - if(L_PADDB>0) fprintf(fp, "paddb %d\n", L_PADDB); - if(L_PADDH>0) fprintf(fp, "paddh %d\n", L_PADDH); - if(L_PADDSB>0) fprintf(fp, "paddsb %d\n", L_PADDSB); - if(L_PADDSH>0) fprintf(fp, "paddsh %d\n", L_PADDSH); - if(L_PADDSW>0) fprintf(fp, "paddsw %d\n", L_PADDSW); - if(L_PADDUB>0) fprintf(fp, "paddub %d\n", L_PADDUB); - if(L_PADDUH>0) fprintf(fp, "padduh %d\n", L_PADDUH); - if(L_PADDUW>0) fprintf(fp, "padduw %d\n", L_PADDUW); - if(L_PADDW>0) fprintf(fp, "paddw %d\n", L_PADDW); - if(L_PADSBH>0) fprintf(fp, "padsbh %d\n", L_PADSBH); - if(L_PAND>0) fprintf(fp, "pand %d\n", L_PAND); - if(L_PCEQB>0) fprintf(fp, "pceqb %d\n", L_PCEQB); - if(L_PCEQH>0) fprintf(fp, "pceqh %d\n", L_PCEQH); - if(L_PCEQW>0) fprintf(fp, "pceqw %d\n", L_PCEQW); - if(L_PCGTB>0) fprintf(fp, "pcgtb %d\n", L_PCGTB); - if(L_PCGTH>0) fprintf(fp, "pcgth %d\n", L_PCGTH); - if(L_PCGTW>0) fprintf(fp, "pcgtw %d\n", L_PCGTW); - if(L_PCPYH>0) fprintf(fp, "pcpyh %d\n", L_PCPYH); - if(L_PCPYLD>0) fprintf(fp, "pcpyld %d\n", L_PCPYLD); - if(L_PCPYUD>0) fprintf(fp, "pcpyud %d\n", L_PCPYUD); - if(L_PDIVBW>0) fprintf(fp, "pdivbw %d\n", L_PDIVBW); - if(L_PDIVUW>0) fprintf(fp, "pdivuw %d\n", L_PDIVUW); - if(L_PDIVW>0) fprintf(fp, "pdivw %d\n", L_PDIVW); - if(L_PEXCH>0) fprintf(fp, "pexch %d\n", L_PEXCH); - if(L_PEXCW>0) fprintf(fp, "pexcw %d\n", L_PEXCW); - if(L_PEXEH>0) fprintf(fp, "pexeh %d\n", L_PEXEH); - if(L_PEXEW>0) fprintf(fp, "pexew %d\n", L_PEXEW); - if(L_PEXT5>0) fprintf(fp, "pext5 %d\n", L_PEXT5); - if(L_PEXTLB>0) fprintf(fp, "pextlb %d\n", L_PEXTLB); - if(L_PEXTLH>0) fprintf(fp, "pextlh %d\n", L_PEXTLH); - if(L_PEXTLW>0) fprintf(fp, "pextlw %d\n", L_PEXTLW); - if(L_PEXTUB>0) fprintf(fp, "pextub %d\n", L_PEXTUB); - if(L_PEXTUH>0) fprintf(fp, "pextuh %d\n", L_PEXTUH); - if(L_PEXTUW>0) fprintf(fp, "pextuw %d\n", L_PEXTUW); - if(L_PHMADH>0) fprintf(fp, "phmadh %d\n", L_PHMADH); - if(L_PHMSBH>0) fprintf(fp, "phmsbh %d\n", L_PHMSBH); - if(L_PINTEH>0) fprintf(fp, "pinteh %d\n", L_PINTEH); - if(L_PINTH>0) fprintf(fp, "pinth %d\n", L_PINTH); - if(L_PLZCW>0) fprintf(fp, "plzcw %d\n", L_PLZCW); - if(L_PMADDH>0) fprintf(fp, "pmaddh %d\n", L_PMADDH); - if(L_PMADDUW>0) fprintf(fp, "pmadduw %d\n", L_PMADDUW); - if(L_PMADDW>0) fprintf(fp, "pmaddw %d\n", L_PMADDW); - if(L_PMAXH>0) fprintf(fp, "pmaxh %d\n", L_PMAXH); - if(L_PMAXW>0) fprintf(fp, "pmaxw %d\n", L_PMAXW); - if(L_PMFHI>0) fprintf(fp, "pmfhi %d\n", L_PMFHI); - if(L_PMFHL>0) fprintf(fp, "pmfhl %d\n", L_PMFHL); - if(L_PMFLO>0) fprintf(fp, "pmflo %d\n", L_PMFLO); - if(L_PMINH>0) fprintf(fp, "pminh %d\n", L_PMINH); - if(L_PMINW>0) fprintf(fp, "pminw %d\n", L_PMINW); - if(L_PMSUBH>0) fprintf(fp, "pmsubh %d\n", L_PMSUBH); - if(L_PMSUBW>0) fprintf(fp, "pmsubw %d\n", L_PMSUBW); - if(L_PMTHI>0) fprintf(fp, "pmthi %d\n", L_PMTHI); - if(L_PMTHL>0) fprintf(fp, "pmthl %d\n", L_PMTHL); - if(L_PMTLO>0) fprintf(fp, "pmtlo %d\n", L_PMTLO); - if(L_PMULTH>0) fprintf(fp, "pmulth %d\n", L_PMULTH); - if(L_PMULTUW>0) fprintf(fp, "pmultuw %d\n", L_PMULTUW); - if(L_PMULTW>0) fprintf(fp, "pmultw %d\n", L_PMULTW); - if(L_PNOR>0) fprintf(fp, "pnor %d\n", L_PNOR); - if(L_POR>0) fprintf(fp, "por %d\n", L_POR); - if(L_PPAC5>0) fprintf(fp, "ppac5 %d\n", L_PPAC5); - if(L_PPACB>0) fprintf(fp, "ppacb %d\n", L_PPACB); - if(L_PPACH>0) fprintf(fp, "ppach %d\n", L_PPACH); - if(L_PPACW>0) fprintf(fp, "ppacw %d\n", L_PPACW); - if(L_PREVH>0) fprintf(fp, "prevh %d\n", L_PREVH); - if(L_PROT3W>0) fprintf(fp, "prot3w %d\n", L_PROT3W); - if(L_PSLLH>0) fprintf(fp, "psllh %d\n", L_PSLLH); - if(L_PSLLVW>0) fprintf(fp, "psllvw %d\n", L_PSLLVW); - if(L_PSLLW>0) fprintf(fp, "psllw %d\n", L_PSLLW); - if(L_PSRAH>0) fprintf(fp, "psrah %d\n", L_PSRAH); - if(L_PSRAVW>0) fprintf(fp, "psravw %d\n", L_PSRAVW); - if(L_PSRAW>0) fprintf(fp, "psraw %d\n", L_PSRAW); - if(L_PSRLH>0) fprintf(fp, "psrlh %d\n", L_PSRLH); - if(L_PSRLVW>0) fprintf(fp, "psrlvw %d\n", L_PSRLVW); - if(L_PSRLW>0) fprintf(fp, "psrlw %d\n", L_PSRLW); - if(L_PSUBB>0) fprintf(fp, "psubb %d\n", L_PSUBB); - if(L_PSUBH>0) fprintf(fp, "psubh %d\n", L_PSUBH); - if(L_PSUBSB>0) fprintf(fp, "psubsb %d\n", L_PSUBSB); - if(L_PSUBSH>0) fprintf(fp, "psubsh %d\n", L_PSUBSH); - if(L_PSUBSW>0) fprintf(fp, "psubsw %d\n", L_PSUBSW); - if(L_PSUBUB>0) fprintf(fp, "psubub %d\n", L_PSUBUB); - if(L_PSUBUH>0) fprintf(fp, "psubuh %d\n", L_PSUBUH); - if(L_PSUBUW>0) fprintf(fp, "psubuw %d\n", L_PSUBUW); - if(L_PSUBW>0) fprintf(fp, "psubw %d\n", L_PSUBW); - if(L_PXOR>0) fprintf(fp, "pxor %d\n", L_PXOR); - if(L_QFSRV>0) fprintf(fp, "qfsrv %d\n", L_QFSRV); - fprintf(fp, "------------\n"); - fprintf(fp, "--COP0 ops--\n"); - fprintf(fp, "------------\n"); - if(L_BC0F>0) fprintf(fp, "bc0f %d\n", L_BC0F); - if(L_BC0FL>0) fprintf(fp, "bc0fl %d\n", L_BC0FL); - if(L_BC0T>0) fprintf(fp, "bc0t %d\n", L_BC0T); - if(L_BC0TL>0) fprintf(fp, "bc0tl %d\n", L_BC0TL); - if(L_DI>0) fprintf(fp, "di %d\n", L_DI); - if(L_EI>0) fprintf(fp, "ei %d\n", L_EI); - if(L_ERET>0) fprintf(fp, "eret %d\n", L_ERET); - if(L_MTC0>0) fprintf(fp, "mtc0 %d\n", L_MTC0); - if(L_TLBP>0) fprintf(fp, "tlbp %d\n", L_TLBP); - if(L_TLBR>0) fprintf(fp, "tlbr %d\n", L_TLBR); - if(L_TLBWI>0) fprintf(fp, "tlbwi %d\n", L_TLBWI); - if(L_TLBWR>0) fprintf(fp, "tlbwr %d\n", L_TLBWR); - if(L_MFC0>0) fprintf(fp, "mfc0 %d\n", L_MFC0); - fprintf(fp, "------------\n"); - fprintf(fp, "--COP1 ops--\n"); - fprintf(fp, "------------\n"); - if(L_LWC1>0) fprintf(fp, "lwc1 %d\n", L_LWC1); - if(L_SWC1>0) fprintf(fp, "swc1 %d\n", L_SWC1); - if(L_ABS_S>0) fprintf(fp, "abs_s %d\n", L_ABS_S); - if(L_ADD_S>0) fprintf(fp, "add_s %d\n", L_ADD_S); - if(L_ADDA_S>0) fprintf(fp, "adda_s %d\n", L_ADDA_S); - if(L_BC1F>0) fprintf(fp, "bc1f %d\n", L_BC1F); - if(L_BC1FL>0) fprintf(fp, "bc1fl %d\n", L_BC1FL); - if(L_BC1T>0) fprintf(fp, "bc1t %d\n", L_BC1T); - if(L_BC1TL>0) fprintf(fp, "bc1tl %d\n", L_BC1TL); - if(L_C_EQ>0) fprintf(fp, "c_eq %d\n", L_C_EQ); - if(L_C_F>0) fprintf(fp, "c_f %d\n", L_C_F); - if(L_C_LE>0) fprintf(fp, "c_le %d\n", L_C_LE); - if(L_C_LT>0) fprintf(fp, "c_lt %d\n", L_C_LT); - if(L_CFC1>0) fprintf(fp, "cfc1 %d\n", L_CFC1); - if(L_CTC1>0) fprintf(fp, "ctc1 %d\n", L_CTC1); - if(L_CVT_S>0) fprintf(fp, "cvt_s %d\n", L_CVT_S); - if(L_CVT_W>0) fprintf(fp, "cvt_w %d\n", L_CVT_W); - if(L_DIV_S>0) fprintf(fp, "div_s %d\n", L_DIV_S); - if(L_MADD_S>0) fprintf(fp, "madd_s %d\n", L_MADD_S); - if(L_MADDA_S>0) fprintf(fp, "madda_s %d\n", L_MADDA_S); - if(L_MAX_S>0) fprintf(fp, "max_s %d\n", L_MAX_S); - if(L_MFC1>0) fprintf(fp, "mfc1 %d\n", L_MFC1); - if(L_MIN_S>0) fprintf(fp, "min_s %d\n", L_MIN_S); - if(L_MOV_S>0) fprintf(fp, "mov_s %d\n", L_MOV_S); - if(L_MSUB_S>0) fprintf(fp, "msub_s %d\n", L_MSUB_S); - if(L_MSUBA_S>0) fprintf(fp, "msuba_s %d\n", L_MSUBA_S); - if(L_MTC1>0) fprintf(fp, "mtc1 %d\n", L_MTC1); - if(L_MUL_S>0) fprintf(fp, "mul_s %d\n", L_MUL_S); - if(L_MULA_S>0) fprintf(fp, "mula_s %d\n", L_MULA_S); - if(L_NEG_S>0) fprintf(fp, "neg_s %d\n", L_NEG_S); - if(L_RSQRT_S>0) fprintf(fp, "rsqrt_s %d\n", L_RSQRT_S); - if(L_SQRT_S>0) fprintf(fp, "sqrt_s %d\n", L_SQRT_S); - if(L_SUB_S>0) fprintf(fp, "sub_s %d\n", L_SUB_S); - if(L_SUBA_S>0) fprintf(fp, "suba_s %d\n", L_SUBA_S); - fprintf(fp, "------------\n"); - fprintf(fp, "--COP2 ops--\n"); - fprintf(fp, "------------\n"); - if(L_LQC2>0) fprintf(fp, "lqc2 %d\n", L_LQC2); - if(L_SQC2>0) fprintf(fp, "sqc2 %d\n", L_SQC2); - if(L_BC2F>0) fprintf(fp, "bc2f %d\n", L_BC2F); - if(L_BC2FL>0) fprintf(fp, "bc2fl %d\n", L_BC2FL); - if(L_BC2T>0) fprintf(fp, "bc2t %d\n", L_BC2T); - if(L_BC2TL>0) fprintf(fp, "bc2tl %d\n", L_BC2TL); - if(L_CFC2>0) fprintf(fp, "cfc2 %d\n", L_CFC2); - if(L_CTC2>0) fprintf(fp, "ctc2 %d\n", L_CTC2); - if(L_QMFC2>0) fprintf(fp, "qmfc2 %d\n", L_QMFC2); - if(L_QMTC2>0) fprintf(fp, "qmtc2 %d\n", L_QMTC2); - if(L_VABS>0) fprintf(fp, "vabs %d\n", L_VABS); - if(L_VADD>0) fprintf(fp, "vadd %d\n", L_VADD); - if(L_VADDA>0) fprintf(fp, "vadda %d\n", L_VADDA); - if(L_VADDAi>0) fprintf(fp, "vaddai %d\n", L_VADDAi); - if(L_VADDAq>0) fprintf(fp, "vaddaq %d\n", L_VADDAq); - if(L_VADDAw>0) fprintf(fp, "vaddaw %d\n", L_VADDAw); - if(L_VADDAx>0) fprintf(fp, "vaddax %d\n", L_VADDAx); - if(L_VADDAy>0) fprintf(fp, "vadday %d\n", L_VADDAy); - if(L_VADDAz>0) fprintf(fp, "vaddaz %d\n", L_VADDAz); - if(L_VADDi>0) fprintf(fp, "vaddi %d\n", L_VADDi); - if(L_VADDq>0) fprintf(fp, "vaddq %d\n", L_VADDq); - if(L_VADDw>0) fprintf(fp, "vaddw %d\n", L_VADDw); - if(L_VADDx>0) fprintf(fp, "vaddx %d\n", L_VADDx); - if(L_VADDy>0) fprintf(fp, "vaddy %d\n", L_VADDy); - if(L_VADDz>0) fprintf(fp, "vaddz %d\n", L_VADDz); - if(L_VCALLMS>0) fprintf(fp, "vcallms %d\n", L_VCALLMS); - if(L_VCALLMSR>0) fprintf(fp, "vcallmsr %d\n", L_VCALLMSR); - if(L_VCLIPw>0) fprintf(fp, "vclip %d\n", L_VCLIPw); - if(L_VDIV>0) fprintf(fp, "vdiv %d\n", L_VDIV); - if(L_VFTOI0>0) fprintf(fp, "vftoi0 %d\n", L_VFTOI0); - if(L_VFTOI12>0) fprintf(fp, "vftoi12 %d\n", L_VFTOI12); - if(L_VFTOI15>0) fprintf(fp, "vftoi15 %d\n", L_VFTOI15); - if(L_VFTOI4>0) fprintf(fp, "vftoi14 %d\n", L_VFTOI4); - if(L_VIADD>0) fprintf(fp, "viadd %d\n", L_VIADD); - if(L_VIADDI>0) fprintf(fp, "viaddi %d\n", L_VIADDI); - if(L_VIAND>0) fprintf(fp, "viand %d\n", L_VIAND); - if(L_VILWR>0) fprintf(fp, "vilwr %d\n", L_VILWR); - if(L_VIOR>0) fprintf(fp, "vior %d\n", L_VIOR); - if(L_VISUB>0) fprintf(fp, "visub %d\n", L_VISUB); - if(L_VISWR>0) fprintf(fp, "viswr %d\n", L_VISWR); - if(L_VITOF0>0) fprintf(fp, "vitof0 %d\n", L_VITOF0); - if(L_VITOF12>0) fprintf(fp, "vitof12 %d\n", L_VITOF12); - if(L_VITOF15>0) fprintf(fp, "vitof15 %d\n", L_VITOF15); - if(L_VITOF4>0) fprintf(fp, "vitof4 %d\n", L_VITOF4); - if(L_VLQD>0) fprintf(fp, "vlqd %d\n", L_VLQD); - if(L_VLQI>0) fprintf(fp, "vlqi %d\n", L_VLQI); - if(L_VMADD>0) fprintf(fp, "vmadd %d\n", L_VMADD); - if(L_VMADDA>0) fprintf(fp, "vmadda %d\n", L_VMADDA); - if(L_VMADDAi>0) fprintf(fp, "vmaddai %d\n", L_VMADDAi); - if(L_VMADDAq>0) fprintf(fp, "vmaddaq %d\n", L_VMADDAq); - if(L_VMADDAw>0) fprintf(fp, "vmaddaw %d\n", L_VMADDAw); - if(L_VMADDAx>0) fprintf(fp, "vmaddax %d\n", L_VMADDAx); - if(L_VMADDAy>0) fprintf(fp, "vmadday %d\n", L_VMADDAy); - if(L_VMADDAz>0) fprintf(fp, "vmaddaz %d\n", L_VMADDAz); - if(L_VMADDi>0) fprintf(fp, "vmaddi %d\n", L_VMADDi); - if(L_VMADDq>0) fprintf(fp, "vmaddq %d\n", L_VMADDq); - if(L_VMADDw>0) fprintf(fp, "vmaddw %d\n", L_VMADDw); - if(L_VMADDx>0) fprintf(fp, "vmaddx %d\n", L_VMADDx); - if(L_VMADDy>0) fprintf(fp, "vmaddy %d\n", L_VMADDy); - if(L_VMADDz>0) fprintf(fp, "vmaddz %d\n", L_VMADDz); - if(L_VMAX>0) fprintf(fp, "vmax %d\n", L_VMAX); - if(L_VMAXi>0) fprintf(fp, "vmaxi %d\n", L_VMAXi); - if(L_VMAXw>0) fprintf(fp, "vmaxw %d\n", L_VMAXw); - if(L_VMAXx>0) fprintf(fp, "vmaxx %d\n", L_VMAXx); - if(L_VMAXy>0) fprintf(fp, "vmaxy %d\n", L_VMAXy); - if(L_VMAXz>0) fprintf(fp, "vmaxz %d\n", L_VMAXz); - if(L_VMFIR>0) fprintf(fp, "vmfir %d\n", L_VMFIR); - if(L_VMINI>0) fprintf(fp, "vmini %d\n", L_VMINI); - if(L_VMINIi>0) fprintf(fp, "vminii %d\n", L_VMINIi); - if(L_VMINIw>0) fprintf(fp, "vminiw %d\n", L_VMINIw); - if(L_VMINIx>0) fprintf(fp, "vminix %d\n", L_VMINIx); - if(L_VMINIy>0) fprintf(fp, "vminiy %d\n", L_VMINIy); - if(L_VMINIz>0) fprintf(fp, "vminiz %d\n", L_VMINIz); - if(L_VMOVE>0) fprintf(fp, "vmove %d\n", L_VMOVE); - if(L_VMR32>0) fprintf(fp, "vmr32 %d\n", L_VMR32); - if(L_VMSUB>0) fprintf(fp, "vmsub %d\n", L_VMSUB); - if(L_VMSUBA>0) fprintf(fp, "vmsuba %d\n", L_VMSUBA); - if(L_VMSUBAi>0) fprintf(fp, "vmsubai %d\n", L_VMSUBAi); - if(L_VMSUBAq>0) fprintf(fp, "vmsubaq %d\n", L_VMSUBAq); - if(L_VMSUBAw>0) fprintf(fp, "vmsubaw %d\n", L_VMSUBAw); - if(L_VMSUBAx>0) fprintf(fp, "vmsubax %d\n", L_VMSUBAx); - if(L_VMSUBAy>0) fprintf(fp, "vmsubay %d\n", L_VMSUBAy); - if(L_VMSUBAz>0) fprintf(fp, "vmsubaz %d\n", L_VMSUBAz); - if(L_VMSUBi>0) fprintf(fp, "vmsubi %d\n", L_VMSUBi); - if(L_VMSUBq>0) fprintf(fp, "vmsubq %d\n", L_VMSUBq); - if(L_VMSUBw>0) fprintf(fp, "vmsubw %d\n", L_VMSUBw); - if(L_VMSUBx>0) fprintf(fp, "vmsubx %d\n", L_VMSUBx); - if(L_VMSUBy>0) fprintf(fp, "vmsuby %d\n", L_VMSUBy); - if(L_VMSUBz>0) fprintf(fp, "vmsubz %d\n", L_VMSUBz); - if(L_VMTIR>0) fprintf(fp, "vmtir %d\n", L_VMTIR); - if(L_VMUL>0) fprintf(fp, "vmul %d\n", L_VMUL); - if(L_VMULA>0) fprintf(fp, "vmula %d\n", L_VMULA); - if(L_VMULAi>0) fprintf(fp, "vmulai %d\n", L_VMULAi); - if(L_VMULAq>0) fprintf(fp, "vmulaq %d\n", L_VMULAq); - if(L_VMULAw>0) fprintf(fp, "vmulaw %d\n", L_VMULAw); - if(L_VMULAx>0) fprintf(fp, "vmulax %d\n", L_VMULAx); - if(L_VMULAy>0) fprintf(fp, "vmulay %d\n", L_VMULAy); - if(L_VMULAz>0) fprintf(fp, "vmulaz %d\n", L_VMULAz); - if(L_VMULi>0) fprintf(fp, "vmuli %d\n", L_VMULi); - if(L_VMULq>0) fprintf(fp, "vmulq %d\n", L_VMULq); - if(L_VMULw>0) fprintf(fp, "vmulw %d\n", L_VMULw); - if(L_VMULx>0) fprintf(fp, "vmulx %d\n", L_VMULx); - if(L_VMULy>0) fprintf(fp, "vmuly %d\n", L_VMULy); - if(L_VMULz>0) fprintf(fp, "vmulz %d\n", L_VMULz); - if(L_VNOP>0) fprintf(fp, "vnop %d\n", L_VNOP); - if(L_VOPMSUB>0) fprintf(fp, "vopmsub %d\n", L_VOPMSUB); - if(L_VOPMULA>0) fprintf(fp, "vopmula %d\n", L_VOPMULA); - if(L_VRGET>0) fprintf(fp, "vrget %d\n", L_VRGET); - if(L_VRINIT>0) fprintf(fp, "vrinit %d\n", L_VRINIT); - if(L_VRNEXT>0) fprintf(fp, "vrnext %d\n", L_VRNEXT); - if(L_VRSQRT>0) fprintf(fp, "vrsqrt %d\n", L_VRSQRT); - if(L_VRXOR>0) fprintf(fp, "vrxor %d\n", L_VRXOR); - if(L_VSQD>0) fprintf(fp, "vsqd %d\n", L_VSQD); - if(L_VSQI>0) fprintf(fp, "vsqi %d\n", L_VSQI); - if(L_VSQRT>0) fprintf(fp, "vsqrt %d\n", L_VSQRT ); - if(L_VSUB>0) fprintf(fp, "vsub %d\n", L_VSUB); - if(L_VSUBA>0) fprintf(fp, "vsuba %d\n", L_VSUBA); - if(L_VSUBAi>0) fprintf(fp, "vsubai %d\n", L_VSUBAi); - if(L_VSUBAq>0) fprintf(fp, "vsubaq %d\n", L_VSUBAq); - if(L_VSUBAw>0) fprintf(fp, "vsubaw %d\n", L_VSUBAw); - if(L_VSUBAx>0) fprintf(fp, "vsubax %d\n", L_VSUBAx); - if(L_VSUBAy>0) fprintf(fp, "vsubay %d\n", L_VSUBAy); - if(L_VSUBAz>0) fprintf(fp, "vsubaz %d\n", L_VSUBAz); - if(L_VSUBi>0) fprintf(fp, "vsubi %d\n", L_VSUBi); - if(L_VSUBq>0) fprintf(fp, "vsubq %d\n", L_VSUBq); - if(L_VSUBw>0) fprintf(fp, "vsubw %d\n", L_VSUBw); - if(L_VSUBx>0) fprintf(fp, "vsubx %d\n", L_VSUBx); - if(L_VSUBy>0) fprintf(fp, "vsuby %d\n", L_VSUBy); - if(L_VSUBz>0) fprintf(fp, "vsubz %d\n", L_VSUBz); - if(L_VWAITQ>0) fprintf(fp, "vwaitq %d\n", L_VWAITQ); - - fclose(fp); - -} - - - - - - - - - - - -/***************/ -//R5900 -void LT_SPECIAL() {LT_SpecialPrintTable[_Funct_]();} -void LT_REGIMM() {LT_REGIMMPrintTable[_Rt_](); } -void LT_UnknownOpcode() {} -void LT_ADDI() { L_ADDI++;} -void LT_ADDIU() { L_ADDIU++;} -void LT_DADDI() { L_DADDI++;} -void LT_DADDIU(){ L_DADDIU++;} -void LT_ANDI() { L_ANDI++;} -void LT_ORI() { L_ORI++;} -void LT_XORI() {L_XORI++;} -void LT_SLTI() {L_SLTI++;} -void LT_SLTIU() {L_SLTIU++;} -void LT_ADD() { L_ADD++;} -void LT_ADDU() { L_ADDU++;} -void LT_DADD() { L_DADD++;} -void LT_DADDU() { L_DADDU++;} -void LT_SUB() { L_SUB++;} -void LT_SUBU() { L_SUBU++;} -void LT_DSUB() { L_DSUB++;} -void LT_DSUBU() { L_DSUBU++;} -void LT_AND() { L_AND++;} -void LT_OR() { L_OR++;} -void LT_XOR() { L_XOR++;} -void LT_NOR() { L_NOR++;} -void LT_SLT() { L_SLT++;} -void LT_SLTU() { L_SLTU++;} -void LT_J() { L_J++;} -void LT_JAL() { L_JAL++;} -void LT_JR() { L_JR++;} -void LT_JALR() { L_JALR++;} -void LT_DIV() { L_DIV++;} -void LT_DIVU() { L_DIVU++;} -void LT_MULT() { L_MULT++;} -void LT_MULTU() { L_MULTU++;} -void LT_LUI() { L_LUI++;} -void LT_MFHI() { L_MFHI++;} -void LT_MFLO() { L_MFLO++;} -void LT_MTHI() { L_MTHI++;} -void LT_MTLO() { L_MTLO++;} -void LT_SLL() { L_SLL++;} -void LT_DSLL() { L_DSLL++;} -void LT_DSLL32(){ L_DSLL32++;} -void LT_SRA() { L_SRA++;} -void LT_DSRA() { L_DSRA++;} -void LT_DSRA32(){ L_DSRA32++;} -void LT_SRL() { L_SRL++;} -void LT_DSRL() { L_DSRL++;} -void LT_DSRL32(){ L_DSRL32++;} -void LT_SLLV() { L_SLLV++;} -void LT_SRAV() { L_SRAV++;} -void LT_SRLV() { L_SRLV++;} -void LT_DSLLV() { L_DSLLV++;} -void LT_DSRAV() { L_DSRAV++;} -void LT_DSRLV() { L_DSRLV++;} -void LT_BEQ() { L_BEQ++;} -void LT_BNE() { L_BNE++;} -void LT_BGEZ() { L_BGEZ++;} -void LT_BGEZAL(){ L_BGEZAL++;} -void LT_BGTZ() { L_BGTZ++;} -void LT_BLEZ() { L_BLEZ++;} -void LT_BLTZ() { L_BLTZ++;} -void LT_BLTZAL(){ L_BLTZAL++;} -void LT_BEQL() { L_BEQL++;} -void LT_BNEL() { L_BNEL++;} -void LT_BLEZL() { L_BLEZL++;} -void LT_BGTZL() { L_BGTZL++;} -void LT_BLTZL() { L_BLTZL++;} -void LT_BGEZL() { L_BGEZL++;} -void LT_BLTZALL(){ L_BLTZALL++;} -void LT_BGEZALL(){ L_BGEZALL++;} -void LT_LB() {L_LB++;} -void LT_LBU() {L_LBU++;} -void LT_LH() {L_LH++;} -void LT_LHU() {L_LHU++;} -void LT_LW() {L_LW++;} -void LT_LWU() {L_LWU++;} -void LT_LWL() {L_LWL++;} -void LT_LWR() {L_LWR++;} -void LT_LD() {L_LD++;} -void LT_LDL() {L_LDL++;} -void LT_LDR() {L_LDR++;} -void LT_LQ() {L_LQ++;} -void LT_SB() {L_SB++;} -void LT_SH() {L_SH++;} -void LT_SW() {L_SW++;} -void LT_SWL() {L_SWL++;} -void LT_SWR() {L_SWR++;} -void LT_SD() {L_SD++;} -void LT_SDL() {L_SDL++;} -void LT_SDR() {L_SDR++;} -void LT_SQ() {L_SQ++;} -void LT_MOVZ() {L_MOVZ++;} -void LT_MOVN() {L_MOVN++;} -void LT_SYSCALL() {L_SYSCALL++;} -void LT_BREAK() {L_BREAK++;} -void LT_CACHE() {L_CACHE++;} -void LT_MFSA() {L_MFSA++;} -void LT_MTSA() {L_MTSA++;} -void LT_SYNC() {L_SYNC++;} -void LT_PREF() {L_PREF++;} -void LT_TGE() {L_TGE++;} -void LT_TGEU() {L_TGEU++;} -void LT_TLT() {L_TLT++;} -void LT_TLTU() {L_TLTU++;} -void LT_TEQ() {L_TEQ++;} -void LT_TNE() {L_TNE++;} -void LT_TGEI() {L_TGEI++;} -void LT_TGEIU() {L_TGEIU++;} -void LT_TLTI() {L_TLTI++;} -void LT_TLTIU() {L_TLTIU++;} -void LT_TEQI() {L_TEQI++;} -void LT_TNEI() {L_TNEI++;} -void LT_MTSAB() {L_MTSAB++;} -void LT_MTSAH() {L_MTSAH++;} -//cop0 -void LT_COP0(){ LT_COP0PrintTable[_Rs_]();} -void LT_COP0_BC0() {LT_COP0BC0PrintTable[(cpuRegs.code >> 16) & 0x03]();} -void LT_COP0_Func() { LT_COP0C0PrintTable[_Funct_](); } -void LT_COP0_Unknown() { } -void LT_MFC0() {L_MFC0++;} -void LT_MTC0() {L_MTC0++;} -void LT_BC0F() {L_BC0F++;} -void LT_BC0T() {L_BC0T++;} -void LT_BC0FL(){L_BC0FL++;} -void LT_BC0TL(){L_BC0TL++;} -void LT_TLBR() {L_TLBR++;} -void LT_TLBWI(){L_TLBWI++;} -void LT_TLBWR(){L_TLBWR++;} -void LT_TLBP() {L_TLBP++;} -void LT_ERET() {L_ERET++;} -void LT_DI() {L_DI++;} -void LT_EI() {L_EI++;} -//mmi -void LT_MMI() {LT_MMIPrintTable[_Funct_]();} -void LT_MMI0() {LT_MMI0PrintTable[_Sa_]();} -void LT_MMI1() {LT_MMI1PrintTable[_Sa_]();} -void LT_MMI2() {LT_MMI2PrintTable[_Sa_]();} -void LT_MMI3() {LT_MMI3PrintTable[_Sa_]();} -void LT_MMI_Unknown() {} -void LT_MADD() {L_MADD++;} -void LT_MADDU(){L_MADDU++;} -void LT_PLZCW(){L_PLZCW++;} -void LT_MADD1(){L_MADD1++;} -void LT_MADDU1(){L_MADDU1++;} -void LT_MFHI1(){L_MFHI1++;} -void LT_MTHI1(){L_MTHI1++;} -void LT_MFLO1(){L_MFLO1++;} -void LT_MTLO1(){L_MTLO1++;} -void LT_MULT1(){L_MULT1++;} -void LT_MULTU1(){L_MULTU1++;} -void LT_DIV1(){L_DIV1++;} -void LT_DIVU1(){L_DIVU1++;} -void LT_PMFHL(){L_PMFHL++;} -void LT_PMTHL(){L_PMTHL++;} -void LT_PSLLH(){L_PSLLH++;} -void LT_PSRLH(){L_PSRLH++;} -void LT_PSRAH(){L_PSRAH++;} -void LT_PSLLW(){L_PSLLW++;} -void LT_PSRLW(){L_PSRLW++;} -void LT_PSRAW(){L_PSRAW++;} -void LT_PADDW(){L_PADDW++;} -void LT_PSUBW(){L_PSUBW++;} -void LT_PCGTW(){L_PCGTW++;} -void LT_PMAXW(){L_PMAXW++;} -void LT_PADDH(){L_PADDH++;} -void LT_PSUBH(){L_PSUBH++;} -void LT_PCGTH(){L_PCGTH++;} -void LT_PMAXH(){L_PMAXH++;} -void LT_PADDB(){L_PADDB++;} -void LT_PSUBB(){L_PSUBB++;} -void LT_PCGTB(){L_PCGTB++;} -void LT_PADDSW(){L_PADDSW++;} -void LT_PSUBSW(){L_PSUBSW++;} -void LT_PEXTLW(){L_PEXTLW++;} -void LT_PPACW(){L_PPACW++;} -void LT_PADDSH(){L_PADDSH++;} -void LT_PSUBSH(){L_PSUBSH++;} -void LT_PEXTLH(){L_PEXTLH++;} -void LT_PPACH(){L_PPACH++;} -void LT_PADDSB(){L_PADDSB++;} -void LT_PSUBSB(){L_PSUBSB++;} -void LT_PEXTLB(){L_PEXTLB++;} -void LT_PPACB(){L_PPACB++;} -void LT_PEXT5(){L_PEXT5++;} -void LT_PPAC5(){L_PPAC5++;} -void LT_PABSW(){L_PABSW++;} -void LT_PCEQW(){L_PCEQW++;} -void LT_PMINW(){L_PMINW++;} -void LT_PADSBH(){L_PADSBH++;} -void LT_PABSH(){L_PABSH++;} -void LT_PCEQH(){L_PCEQH++;} -void LT_PMINH(){L_PMINH++;} -void LT_PCEQB(){L_PCEQB++;} -void LT_PADDUW(){L_PADDUW++;} -void LT_PSUBUW(){L_PSUBUW++;} -void LT_PEXTUW(){L_PEXTUW++;} -void LT_PADDUH(){L_PADDUH++;} -void LT_PSUBUH(){L_PSUBUH++;} -void LT_PEXTUH(){L_PEXTUH++;} -void LT_PADDUB(){L_PADDUB++;} -void LT_PSUBUB(){L_PSUBUB++;} -void LT_PEXTUB(){L_PEXTUB++;} -void LT_QFSRV(){L_QFSRV++;} -void LT_PMADDW(){L_PMADDW++;} -void LT_PSLLVW(){L_PSLLVW++;} -void LT_PSRLVW(){L_PSRLVW++;} -void LT_PMSUBW(){L_PMSUBW++;} -void LT_PMFHI(){L_PMFHI++;} -void LT_PMFLO(){L_PMFLO++;} -void LT_PINTH(){L_PINTH++;} -void LT_PMULTW(){L_PMULTW++;} -void LT_PDIVW(){L_PDIVW++;} -void LT_PCPYLD(){L_PCPYLD++;} -void LT_PMADDH(){L_PMADDH++;} -void LT_PHMADH(){L_PHMADH++;} -void LT_PAND(){L_PAND++;} -void LT_PXOR(){L_PXOR++;} -void LT_PMSUBH(){L_PMSUBH++;} -void LT_PHMSBH(){L_PHMSBH++;} -void LT_PEXEH(){L_PEXEH++;} -void LT_PREVH(){L_PREVH++;} -void LT_PMULTH(){L_PMULTH++;} -void LT_PDIVBW(){L_PDIVBW++;} -void LT_PEXEW(){L_PEXEW++;} -void LT_PROT3W(){L_PROT3W++;} -void LT_PMADDUW(){L_PMADDUW++;} -void LT_PSRAVW(){L_PSRAVW++;} -void LT_PMTHI(){L_MTHI++;} -void LT_PMTLO(){L_PMTLO++;} -void LT_PINTEH(){L_PINTEH++;} -void LT_PMULTUW(){L_PMULTUW++;} -void LT_PDIVUW(){L_PDIVUW++;} -void LT_PCPYUD(){L_PCPYUD++;} -void LT_POR(){L_POR++;} -void LT_PNOR(){L_PNOR++;} -void LT_PEXCH(){L_PEXCH++;} -void LT_PCPYH(){L_PCPYH++;} -void LT_PEXCW(){L_PEXCW++;} -//COP1 -void LT_COP1() {LT_COP1PrintTable[_Rs_]();} -void LT_LWC1() {L_LWC1++;} -void LT_SWC1() {L_SWC1++;} -void LT_COP1_BC1() {LT_COP1BC1PrintTable[_Rt_]();} -void LT_COP1_S() {LT_COP1SPrintTable[_Funct_]();} -void LT_COP1_W() {LT_COP1WPrintTable[_Funct_]();} -void LT_COP1_Unknown() {} -void LT_MFC1(){L_MFC1++;} -void LT_CFC1(){L_CFC1++;} -void LT_MTC1(){L_MTC1++;} -void LT_CTC1(){L_CTC1++;} -void LT_BC1F(){L_BC1F++;} -void LT_BC1T(){L_BC1T++;} -void LT_BC1FL(){L_BC1FL++;} -void LT_BC1TL(){L_BC1TL++;} -void LT_ADD_S(){L_ADD_S++;} -void LT_SUB_S(){L_SUB_S++;} -void LT_MUL_S(){L_MUL_S++;} -void LT_DIV_S(){L_DIV_S++;} -void LT_SQRT_S(){L_SQRT_S++;} -void LT_ABS_S(){L_ABS_S++;} -void LT_MOV_S(){L_MOV_S++;} -void LT_NEG_S(){L_NEG_S++;} -void LT_RSQRT_S(){L_RSQRT_S++;} -void LT_ADDA_S(){L_ADDA_S++;} -void LT_SUBA_S(){L_SUBA_S++;} -void LT_MULA_S(){L_MULA_S++;} -void LT_MADD_S(){L_MADD_S++;} -void LT_MSUB_S(){L_MSUB_S++;} -void LT_MADDA_S(){L_MADDA_S++;} -void LT_MSUBA_S(){L_MSUBA_S++;} -void LT_CVT_W(){L_CVT_W++;} -void LT_MAX_S(){L_MAX_S++;} -void LT_MIN_S(){L_MIN_S++;} -void LT_C_F(){L_C_F++;} -void LT_C_EQ(){L_C_EQ++;} -void LT_C_LT(){L_C_LT++;} -void LT_C_LE(){L_C_LE++;} -void LT_CVT_S(){L_CVT_S++;} -//cop2 - -void LT_LQC2() {L_LQC2++;} -void LT_SQC2() {L_SQC2++;} -void LT_COP2() {LT_COP2PrintTable[_Rs_]();} -void LT_COP2_BC2() {LT_COP2BC2PrintTable[_Rt_]();} -void LT_COP2_SPECIAL() { LT_COP2SPECIAL1PrintTable[_Funct_]();} -void LT_COP2_SPECIAL2() {LT_COP2SPECIAL2PrintTable[(cpuRegs.code & 0x3) | ((cpuRegs.code >> 4) & 0x7c)]();} -void LT_COP2_Unknown(){} -void LT_QMFC2(){L_QMFC2++;} -void LT_CFC2(){L_CFC2++;} -void LT_QMTC2(){L_QMTC2++;} -void LT_CTC2(){L_CTC2++;} -void LT_BC2F(){L_BC2F++;} -void LT_BC2T(){L_BC2T++;} -void LT_BC2FL(){L_BC2FL++;} -void LT_BC2TL(){L_BC2TL++;} -void LT_VADDx(){L_VADDx++;} -void LT_VADDy(){L_VADDy++;} -void LT_VADDz(){L_VADDz++;} -void LT_VADDw(){L_VADDw++;} -void LT_VSUBx(){L_VSUBx++;} -void LT_VSUBy(){L_VSUBy++;} -void LT_VSUBz(){L_VSUBz++;} -void LT_VSUBw(){L_VSUBw++;} -void LT_VMADDx(){L_VMADDx++;} -void LT_VMADDy(){L_VMADDy++;} -void LT_VMADDz(){L_VMADDz++;} -void LT_VMADDw(){L_VMADDw++;} -void LT_VMSUBx(){L_VMSUBx++;} -void LT_VMSUBy(){L_VMSUBy++;} -void LT_VMSUBz(){L_VMSUBz++;} -void LT_VMSUBw(){L_VMSUBw++;} -void LT_VMAXx(){L_VMAXx++;} -void LT_VMAXy(){L_VMAXy++;} -void LT_VMAXz(){L_VMAXz++;} -void LT_VMAXw(){L_VMAXw++;} -void LT_VMINIx(){L_VMINIx++;} -void LT_VMINIy(){L_VMINIy++;} -void LT_VMINIz(){L_VMINIz++;} -void LT_VMINIw(){L_VMINIw++;} -void LT_VMULx(){L_VMULx++;} -void LT_VMULy(){L_VMULy++;} -void LT_VMULz(){L_VMULz++;} -void LT_VMULw(){L_VMULw++;} -void LT_VMULq(){L_VMULq++;} -void LT_VMAXi(){L_VMAXi++;} -void LT_VMULi(){L_VMULi++;} -void LT_VMINIi(){L_VMINIi++;} -void LT_VADDq(){L_VADDq++;} -void LT_VMADDq(){L_VMADDq++;} -void LT_VADDi(){L_VADDi++;} -void LT_VMADDi(){L_VMADDi++;} -void LT_VSUBq(){L_VSUBq++;} -void LT_VMSUBq(){L_VMSUBq++;} -void LT_VSUBi(){L_VSUBi++;} -void LT_VMSUBi(){L_VMSUBi++;} -void LT_VADD(){L_VADD++;} -void LT_VMADD(){L_VMADD++;} -void LT_VMUL(){L_VMUL++;} -void LT_VMAX(){L_VMAX++;} -void LT_VSUB(){L_VSUB++;} -void LT_VMSUB(){L_VMSUB++;} -void LT_VOPMSUB(){L_VOPMSUB++;} -void LT_VMINI(){L_VMINI++;} -void LT_VIADD(){L_VIADD++;} -void LT_VISUB(){L_VISUB++;} -void LT_VIADDI(){L_VIADDI++;} -void LT_VIAND(){L_VIAND++;} -void LT_VIOR(){L_VIOR++;} -void LT_VCALLMS(){L_VCALLMS++;} -void LT_VCALLMSR(){L_VCALLMSR++;} -void LT_VADDAx(){L_VADDAx++;} -void LT_VADDAy(){L_VADDAy++;} -void LT_VADDAz(){L_VADDAz++;} -void LT_VADDAw(){L_VADDAw++;} -void LT_VSUBAx(){L_VSUBAx++;} -void LT_VSUBAy(){L_VSUBAy++;} -void LT_VSUBAz(){L_VSUBAz++;} -void LT_VSUBAw(){L_VSUBAw++;} -void LT_VMADDAx(){L_VMADDAx++;} -void LT_VMADDAy(){L_VMADDAy++;} -void LT_VMADDAz(){L_VMADDAz++;} -void LT_VMADDAw(){L_VMADDAw++;} -void LT_VMSUBAx(){L_VMSUBAx++;} -void LT_VMSUBAy(){L_VMSUBAy++;} -void LT_VMSUBAz(){L_VMSUBAz++;} -void LT_VMSUBAw(){L_VMSUBAw++;} -void LT_VITOF0(){L_VITOF0++;} -void LT_VITOF4(){L_VITOF4++;} -void LT_VITOF12(){L_VITOF12++;} -void LT_VITOF15(){L_VITOF15++;} -void LT_VFTOI0(){L_VFTOI0++;} -void LT_VFTOI4(){L_VFTOI4++;} -void LT_VFTOI12(){L_VFTOI12++;} -void LT_VFTOI15(){L_VFTOI15++;} -void LT_VMULAx(){L_VMULAx++;} -void LT_VMULAy(){L_VMULAy++;} -void LT_VMULAz(){L_VMULAz++;} -void LT_VMULAw(){L_VMULAw++;} -void LT_VMULAq(){L_VMULAq++;} -void LT_VABS(){L_VABS++;} -void LT_VMULAi(){L_VMULAi++;} -void LT_VCLIPw(){L_VCLIPw++;} -void LT_VADDAq(){L_VADDAq++;} -void LT_VMADDAq(){L_VMADDAq++;} -void LT_VADDAi(){L_VADDAi++;} -void LT_VMADDAi(){L_VMADDAi++;} -void LT_VSUBAq(){L_VSUBAq++;} -void LT_VMSUBAq(){L_VMSUBAq++;} -void LT_VSUBAi(){L_VSUBAi++;} -void LT_VMSUBAi(){L_VMSUBAi++;} -void LT_VADDA(){L_VADDA++;} -void LT_VMADDA(){L_VMADDA++;} -void LT_VMULA(){L_VMULA++;} -void LT_VSUBA(){L_VSUBA++;} -void LT_VMSUBA(){L_VMSUBA++;} -void LT_VOPMULA(){L_VOPMULA++;} -void LT_VNOP(){L_VNOP++;} -void LT_VMOVE(){L_VMOVE++;} -void LT_VMR32(){L_VMR32++;} -void LT_VLQI(){L_VLQI++;} -void LT_VSQI(){L_VSQI++;} -void LT_VLQD(){L_VLQD++;} -void LT_VSQD(){L_VSQD++;} -void LT_VDIV(){L_VDIV++;} -void LT_VSQRT(){L_VSQRT++;} -void LT_VRSQRT(){L_VRSQRT++;} -void LT_VWAITQ(){L_VWAITQ++;} -void LT_VMTIR(){L_VMTIR++;} -void LT_VMFIR(){L_VMFIR++;} -void LT_VILWR(){L_VILWR++;} -void LT_VISWR(){L_VISWR++;} -void LT_VRNEXT(){L_VRNEXT++;} -void LT_VRGET(){L_VRGET++;} -void LT_VRINIT(){L_VRINIT++;} -void LT_VRXOR(){L_VRXOR++;} - -void (*LT_OpcodePrintTable[64])() = -{ - LT_SPECIAL, LT_REGIMM, LT_J, LT_JAL, LT_BEQ, LT_BNE, LT_BLEZ, LT_BGTZ, - LT_ADDI, LT_ADDIU, LT_SLTI, LT_SLTIU, LT_ANDI, LT_ORI, LT_XORI, LT_LUI, - LT_COP0, LT_COP1, LT_COP2, LT_UnknownOpcode, LT_BEQL, LT_BNEL, LT_BLEZL, LT_BGTZL, - LT_DADDI, LT_DADDIU, LT_LDL, LT_LDR, LT_MMI, LT_UnknownOpcode, LT_LQ, LT_SQ, - LT_LB, LT_LH, LT_LWL, LT_LW, LT_LBU, LT_LHU, LT_LWR, LT_LWU, - LT_SB, LT_SH, LT_SWL, LT_SW, LT_SDL, LT_SDR, LT_SWR, LT_CACHE, - LT_UnknownOpcode, LT_LWC1, LT_UnknownOpcode, LT_PREF, LT_UnknownOpcode,LT_UnknownOpcode, LT_LQC2, LT_LD, - LT_UnknownOpcode, LT_SWC1, LT_UnknownOpcode, LT_UnknownOpcode, LT_UnknownOpcode,LT_UnknownOpcode, LT_SQC2, LT_SD -}; - - -void (*LT_SpecialPrintTable[64])() = -{ - LT_SLL, LT_UnknownOpcode, LT_SRL, LT_SRA, LT_SLLV, LT_UnknownOpcode, LT_SRLV, LT_SRAV, - LT_JR, LT_JALR, LT_MOVZ, LT_MOVN, LT_SYSCALL, LT_BREAK, LT_UnknownOpcode, LT_SYNC, - LT_MFHI, LT_MTHI, LT_MFLO, LT_MTLO, LT_DSLLV, LT_UnknownOpcode, LT_DSRLV, LT_DSRAV, - LT_MULT, LT_MULTU, LT_DIV, LT_DIVU, LT_UnknownOpcode,LT_UnknownOpcode,LT_UnknownOpcode,LT_UnknownOpcode, - LT_ADD, LT_ADDU, LT_SUB, LT_SUBU, LT_AND, LT_OR, LT_XOR, LT_NOR, - LT_MFSA , LT_MTSA , LT_SLT, LT_SLTU, LT_DADD, LT_DADDU, LT_DSUB, LT_DSUBU, - LT_TGE, LT_TGEU, LT_TLT, LT_TLTU, LT_TEQ, LT_UnknownOpcode, LT_TNE, LT_UnknownOpcode, - LT_DSLL, LT_UnknownOpcode, LT_DSRL, LT_DSRA, LT_DSLL32, LT_UnknownOpcode, LT_DSRL32, LT_DSRA32 -}; - -void (*LT_REGIMMPrintTable[32])() = { - LT_BLTZ, LT_BGEZ, LT_BLTZL, LT_BGEZL, LT_UnknownOpcode, LT_UnknownOpcode, LT_UnknownOpcode, LT_UnknownOpcode, - LT_TGEI, LT_TGEIU, LT_TLTI, LT_TLTIU, LT_TEQI, LT_UnknownOpcode, LT_TNEI, LT_UnknownOpcode, - LT_BLTZAL, LT_BGEZAL, LT_BLTZALL, LT_BGEZALL, LT_UnknownOpcode, LT_UnknownOpcode, LT_UnknownOpcode, LT_UnknownOpcode, - LT_MTSAB, LT_MTSAH , LT_UnknownOpcode, LT_UnknownOpcode, LT_UnknownOpcode, LT_UnknownOpcode, LT_UnknownOpcode, LT_UnknownOpcode, -}; -void (*LT_MMIPrintTable[64])() = -{ - LT_MADD, LT_MADDU, LT_MMI_Unknown, LT_MMI_Unknown, LT_PLZCW, LT_MMI_Unknown, LT_MMI_Unknown, LT_MMI_Unknown, - LT_MMI0, LT_MMI2, LT_MMI_Unknown, LT_MMI_Unknown, LT_MMI_Unknown, LT_MMI_Unknown, LT_MMI_Unknown, LT_MMI_Unknown, - LT_MFHI1, LT_MTHI1, LT_MFLO1, LT_MTLO1, LT_MMI_Unknown, LT_MMI_Unknown, LT_MMI_Unknown, LT_MMI_Unknown, - LT_MULT1, LT_MULTU1, LT_DIV1, LT_DIVU1, LT_MMI_Unknown, LT_MMI_Unknown, LT_MMI_Unknown, LT_MMI_Unknown, - LT_MADD1, LT_MADDU1, LT_MMI_Unknown, LT_MMI_Unknown, LT_MMI_Unknown, LT_MMI_Unknown, LT_MMI_Unknown, LT_MMI_Unknown, - LT_MMI1 , LT_MMI3, LT_MMI_Unknown, LT_MMI_Unknown, LT_MMI_Unknown, LT_MMI_Unknown, LT_MMI_Unknown, LT_MMI_Unknown, - LT_PMFHL, LT_PMTHL, LT_MMI_Unknown, LT_MMI_Unknown, LT_PSLLH, LT_MMI_Unknown, LT_PSRLH, LT_PSRAH, - LT_MMI_Unknown, LT_MMI_Unknown, LT_MMI_Unknown, LT_MMI_Unknown, LT_PSLLW, LT_MMI_Unknown, LT_PSRLW, LT_PSRAW, -}; - -void (*LT_MMI0PrintTable[32])() = -{ - LT_PADDW, LT_PSUBW, LT_PCGTW, LT_PMAXW, - LT_PADDH, LT_PSUBH, LT_PCGTH, LT_PMAXH, - LT_PADDB, LT_PSUBB, LT_PCGTB, LT_MMI_Unknown, - LT_MMI_Unknown, LT_MMI_Unknown, LT_MMI_Unknown, LT_MMI_Unknown, - LT_PADDSW, LT_PSUBSW, LT_PEXTLW, LT_PPACW, - LT_PADDSH, LT_PSUBSH, LT_PEXTLH, LT_PPACH, - LT_PADDSB, LT_PSUBSB, LT_PEXTLB, LT_PPACB, - LT_MMI_Unknown, LT_MMI_Unknown, LT_PEXT5, LT_PPAC5, -}; - -void (*LT_MMI1PrintTable[32])() = -{ - LT_MMI_Unknown, LT_PABSW, LT_PCEQW, LT_PMINW, - LT_PADSBH, LT_PABSH, LT_PCEQH, LT_PMINH, - LT_MMI_Unknown, LT_MMI_Unknown, LT_PCEQB, LT_MMI_Unknown, - LT_MMI_Unknown, LT_MMI_Unknown, LT_MMI_Unknown, LT_MMI_Unknown, - LT_PADDUW, LT_PSUBUW, LT_PEXTUW, LT_MMI_Unknown, - LT_PADDUH, LT_PSUBUH, LT_PEXTUH, LT_MMI_Unknown, - LT_PADDUB, LT_PSUBUB, LT_PEXTUB, LT_QFSRV, - LT_MMI_Unknown, LT_MMI_Unknown, LT_MMI_Unknown, LT_MMI_Unknown, -}; - - -void (*LT_MMI2PrintTable[32])() = -{ - LT_PMADDW, LT_MMI_Unknown, LT_PSLLVW, LT_PSRLVW, - LT_PMSUBW, LT_MMI_Unknown, LT_MMI_Unknown, LT_MMI_Unknown, - LT_PMFHI, LT_PMFLO, LT_PINTH, LT_MMI_Unknown, - LT_PMULTW, LT_PDIVW, LT_PCPYLD, LT_MMI_Unknown, - LT_PMADDH, LT_PHMADH, LT_PAND, LT_PXOR, - LT_PMSUBH, LT_PHMSBH, LT_MMI_Unknown, LT_MMI_Unknown, - LT_MMI_Unknown, LT_MMI_Unknown, LT_PEXEH, LT_PREVH, - LT_PMULTH, LT_PDIVBW, LT_PEXEW, LT_PROT3W, -}; - -void (*LT_MMI3PrintTable[32])() = -{ - LT_PMADDUW, LT_MMI_Unknown, LT_MMI_Unknown, LT_PSRAVW, - LT_MMI_Unknown, LT_MMI_Unknown, LT_MMI_Unknown, LT_MMI_Unknown, - LT_PMTHI, LT_PMTLO, LT_PINTEH, LT_MMI_Unknown, - LT_PMULTUW, LT_PDIVUW, LT_PCPYUD, LT_MMI_Unknown, - LT_MMI_Unknown, LT_MMI_Unknown, LT_POR, LT_PNOR, - LT_MMI_Unknown, LT_MMI_Unknown, LT_MMI_Unknown, LT_MMI_Unknown, - LT_MMI_Unknown, LT_MMI_Unknown, LT_PEXCH, LT_PCPYH, - LT_MMI_Unknown, LT_MMI_Unknown, LT_PEXCW, LT_MMI_Unknown, -}; - -void (*LT_COP0PrintTable[32])() = -{ - LT_MFC0, LT_COP0_Unknown, LT_COP0_Unknown, LT_COP0_Unknown, LT_MTC0, LT_COP0_Unknown, LT_COP0_Unknown, LT_COP0_Unknown, - LT_COP0_BC0, LT_COP0_Unknown, LT_COP0_Unknown, LT_COP0_Unknown, LT_COP0_Unknown, LT_COP0_Unknown, LT_COP0_Unknown, LT_COP0_Unknown, - LT_COP0_Func, LT_COP0_Unknown, LT_COP0_Unknown, LT_COP0_Unknown, LT_COP0_Unknown, LT_COP0_Unknown, LT_COP0_Unknown, LT_COP0_Unknown, - LT_COP0_Unknown, LT_COP0_Unknown, LT_COP0_Unknown, LT_COP0_Unknown, LT_COP0_Unknown, LT_COP0_Unknown, LT_COP0_Unknown, LT_COP0_Unknown, -}; - -void (*LT_COP0BC0PrintTable[32])() = -{ - LT_BC0F, LT_BC0T, LT_BC0FL, LT_BC0TL, LT_COP0_Unknown, LT_COP0_Unknown, LT_COP0_Unknown, LT_COP0_Unknown, - LT_COP0_Unknown, LT_COP0_Unknown, LT_COP0_Unknown, LT_COP0_Unknown, LT_COP0_Unknown, LT_COP0_Unknown, LT_COP0_Unknown, LT_COP0_Unknown, - LT_COP0_Unknown, LT_COP0_Unknown, LT_COP0_Unknown, LT_COP0_Unknown, LT_COP0_Unknown, LT_COP0_Unknown, LT_COP0_Unknown, LT_COP0_Unknown, - LT_COP0_Unknown, LT_COP0_Unknown, LT_COP0_Unknown, LT_COP0_Unknown, LT_COP0_Unknown, LT_COP0_Unknown, LT_COP0_Unknown, LT_COP0_Unknown, -}; - -void (*LT_COP0C0PrintTable[64])() = { - LT_COP0_Unknown, LT_TLBR, LT_TLBWI, LT_COP0_Unknown, LT_COP0_Unknown, LT_COP0_Unknown, LT_TLBWR, LT_COP0_Unknown, - LT_TLBP, LT_COP0_Unknown, LT_COP0_Unknown, LT_COP0_Unknown, LT_COP0_Unknown, LT_COP0_Unknown, LT_COP0_Unknown, LT_COP0_Unknown, - LT_COP0_Unknown, LT_COP0_Unknown, LT_COP0_Unknown, LT_COP0_Unknown, LT_COP0_Unknown, LT_COP0_Unknown, LT_COP0_Unknown, LT_COP0_Unknown, - LT_ERET, LT_COP0_Unknown, LT_COP0_Unknown, LT_COP0_Unknown, LT_COP0_Unknown, LT_COP0_Unknown, LT_COP0_Unknown, LT_COP0_Unknown, - LT_COP0_Unknown, LT_COP0_Unknown, LT_COP0_Unknown, LT_COP0_Unknown, LT_COP0_Unknown, LT_COP0_Unknown, LT_COP0_Unknown, LT_COP0_Unknown, - LT_COP0_Unknown, LT_COP0_Unknown, LT_COP0_Unknown, LT_COP0_Unknown, LT_COP0_Unknown, LT_COP0_Unknown, LT_COP0_Unknown, LT_COP0_Unknown, - LT_COP0_Unknown, LT_COP0_Unknown, LT_COP0_Unknown, LT_COP0_Unknown, LT_COP0_Unknown, LT_COP0_Unknown, LT_COP0_Unknown, LT_COP0_Unknown, - LT_EI, LT_DI, LT_COP0_Unknown, LT_COP0_Unknown, LT_COP0_Unknown, LT_COP0_Unknown, LT_COP0_Unknown, LT_COP0_Unknown -}; - - -void (*LT_COP1PrintTable[32])() = { - LT_MFC1, LT_COP1_Unknown, LT_CFC1, LT_COP1_Unknown, LT_MTC1, LT_COP1_Unknown, LT_CTC1, LT_COP1_Unknown, - LT_COP1_BC1, LT_COP1_Unknown, LT_COP1_Unknown, LT_COP1_Unknown, LT_COP1_Unknown, LT_COP1_Unknown, LT_COP1_Unknown, LT_COP1_Unknown, - LT_COP1_S, LT_COP1_Unknown, LT_COP1_Unknown, LT_COP1_Unknown, LT_COP1_W, LT_COP1_Unknown, LT_COP1_Unknown, LT_COP1_Unknown, - LT_COP1_Unknown, LT_COP1_Unknown, LT_COP1_Unknown, LT_COP1_Unknown, LT_COP1_Unknown, LT_COP1_Unknown, LT_COP1_Unknown, LT_COP1_Unknown, -}; - -void (*LT_COP1BC1PrintTable[32])() = { - LT_BC1F, LT_BC1T, LT_BC1FL, LT_BC1TL, LT_COP1_Unknown, LT_COP1_Unknown, LT_COP1_Unknown, LT_COP1_Unknown, - LT_COP1_Unknown, LT_COP1_Unknown, LT_COP1_Unknown, LT_COP1_Unknown, LT_COP1_Unknown, LT_COP1_Unknown, LT_COP1_Unknown, LT_COP1_Unknown, - LT_COP1_Unknown, LT_COP1_Unknown, LT_COP1_Unknown, LT_COP1_Unknown, LT_COP1_Unknown, LT_COP1_Unknown, LT_COP1_Unknown, LT_COP1_Unknown, - LT_COP1_Unknown, LT_COP1_Unknown, LT_COP1_Unknown, LT_COP1_Unknown, LT_COP1_Unknown, LT_COP1_Unknown, LT_COP1_Unknown, LT_COP1_Unknown, -}; - -void (*LT_COP1SPrintTable[64])() = { -LT_ADD_S, LT_SUB_S, LT_MUL_S, LT_DIV_S, LT_SQRT_S, LT_ABS_S, LT_MOV_S, LT_NEG_S, -LT_COP1_Unknown,LT_COP1_Unknown,LT_COP1_Unknown,LT_COP1_Unknown,LT_COP1_Unknown,LT_COP1_Unknown,LT_COP1_Unknown,LT_COP1_Unknown, -LT_COP1_Unknown,LT_COP1_Unknown,LT_COP1_Unknown,LT_COP1_Unknown,LT_COP1_Unknown,LT_COP1_Unknown,LT_RSQRT_S, LT_COP1_Unknown, -LT_ADDA_S, LT_SUBA_S, LT_MULA_S, LT_COP1_Unknown,LT_MADD_S, LT_MSUB_S, LT_MADDA_S, LT_MSUBA_S, -LT_COP1_Unknown,LT_COP1_Unknown,LT_COP1_Unknown,LT_COP1_Unknown,LT_CVT_W, LT_COP1_Unknown,LT_COP1_Unknown,LT_COP1_Unknown, -LT_MAX_S, LT_MIN_S, LT_COP1_Unknown,LT_COP1_Unknown,LT_COP1_Unknown,LT_COP1_Unknown,LT_COP1_Unknown,LT_COP1_Unknown, -LT_C_F, LT_COP1_Unknown,LT_C_EQ, LT_COP1_Unknown,LT_C_LT, LT_COP1_Unknown,LT_C_LE, LT_COP1_Unknown, -LT_COP1_Unknown,LT_COP1_Unknown,LT_COP1_Unknown,LT_COP1_Unknown,LT_COP1_Unknown,LT_COP1_Unknown,LT_COP1_Unknown,LT_COP1_Unknown, -}; - -void (*LT_COP1WPrintTable[64])() = { -LT_COP1_Unknown,LT_COP1_Unknown,LT_COP1_Unknown,LT_COP1_Unknown,LT_COP1_Unknown,LT_COP1_Unknown,LT_COP1_Unknown,LT_COP1_Unknown, -LT_COP1_Unknown,LT_COP1_Unknown,LT_COP1_Unknown,LT_COP1_Unknown,LT_COP1_Unknown,LT_COP1_Unknown,LT_COP1_Unknown,LT_COP1_Unknown, -LT_COP1_Unknown,LT_COP1_Unknown,LT_COP1_Unknown,LT_COP1_Unknown,LT_COP1_Unknown,LT_COP1_Unknown,LT_COP1_Unknown,LT_COP1_Unknown, -LT_COP1_Unknown,LT_COP1_Unknown,LT_COP1_Unknown,LT_COP1_Unknown,LT_COP1_Unknown,LT_COP1_Unknown,LT_COP1_Unknown,LT_COP1_Unknown, -LT_CVT_S, LT_COP1_Unknown,LT_COP1_Unknown,LT_COP1_Unknown,LT_COP1_Unknown,LT_COP1_Unknown,LT_COP1_Unknown,LT_COP1_Unknown, -LT_COP1_Unknown,LT_COP1_Unknown,LT_COP1_Unknown,LT_COP1_Unknown,LT_COP1_Unknown,LT_COP1_Unknown,LT_COP1_Unknown,LT_COP1_Unknown, -LT_COP1_Unknown,LT_COP1_Unknown,LT_COP1_Unknown,LT_COP1_Unknown,LT_COP1_Unknown,LT_COP1_Unknown,LT_COP1_Unknown,LT_COP1_Unknown, -LT_COP1_Unknown,LT_COP1_Unknown,LT_COP1_Unknown,LT_COP1_Unknown,LT_COP1_Unknown,LT_COP1_Unknown,LT_COP1_Unknown,LT_COP1_Unknown, -}; - -void (*LT_COP2PrintTable[32])() = { - LT_COP2_Unknown, LT_QMFC2, LT_CFC2, LT_COP2_Unknown, LT_COP2_Unknown, LT_QMTC2, LT_CTC2, LT_COP2_Unknown, - LT_COP2_BC2, LT_COP2_Unknown, LT_COP2_Unknown, LT_COP2_Unknown, LT_COP2_Unknown, LT_COP2_Unknown, LT_COP2_Unknown, LT_COP2_Unknown, - LT_COP2_SPECIAL, LT_COP2_SPECIAL, LT_COP2_SPECIAL, LT_COP2_SPECIAL, LT_COP2_SPECIAL, LT_COP2_SPECIAL, LT_COP2_SPECIAL, LT_COP2_SPECIAL, - LT_COP2_SPECIAL, LT_COP2_SPECIAL, LT_COP2_SPECIAL, LT_COP2_SPECIAL, LT_COP2_SPECIAL, LT_COP2_SPECIAL, LT_COP2_SPECIAL, LT_COP2_SPECIAL, -}; - -void (*LT_COP2BC2PrintTable[32])() = { - LT_BC2F, LT_BC2T, LT_BC2FL, LT_BC2TL, LT_COP2_Unknown, LT_COP2_Unknown, LT_COP2_Unknown, LT_COP2_Unknown, - LT_COP2_Unknown, LT_COP2_Unknown, LT_COP2_Unknown, LT_COP2_Unknown, LT_COP2_Unknown, LT_COP2_Unknown, LT_COP2_Unknown, LT_COP2_Unknown, - LT_COP2_Unknown, LT_COP2_Unknown, LT_COP2_Unknown, LT_COP2_Unknown, LT_COP2_Unknown, LT_COP2_Unknown, LT_COP2_Unknown, LT_COP2_Unknown, - LT_COP2_Unknown, LT_COP2_Unknown, LT_COP2_Unknown, LT_COP2_Unknown, LT_COP2_Unknown, LT_COP2_Unknown, LT_COP2_Unknown, LT_COP2_Unknown, -}; - -void (*LT_COP2SPECIAL1PrintTable[64])() = -{ - LT_VADDx, LT_VADDy, LT_VADDz, LT_VADDw, LT_VSUBx, LT_VSUBy, LT_VSUBz, LT_VSUBw, - LT_VMADDx, LT_VMADDy, LT_VMADDz, LT_VMADDw, LT_VMSUBx, LT_VMSUBy, LT_VMSUBz, LT_VMSUBw, - LT_VMAXx, LT_VMAXy, LT_VMAXz, LT_VMAXw, LT_VMINIx, LT_VMINIy, LT_VMINIz, LT_VMINIw, - LT_VMULx, LT_VMULy, LT_VMULz, LT_VMULw, LT_VMULq, LT_VMAXi, LT_VMULi, LT_VMINIi, - LT_VADDq, LT_VMADDq, LT_VADDi, LT_VMADDi, LT_VSUBq, LT_VMSUBq, LT_VSUBi, LT_VMSUBi, - LT_VADD, LT_VMADD, LT_VMUL, LT_VMAX, LT_VSUB, LT_VMSUB, LT_VOPMSUB, LT_VMINI, - LT_VIADD, LT_VISUB, LT_VIADDI, LT_COP2_Unknown,LT_VIAND, LT_VIOR, LT_COP2_Unknown, LT_COP2_Unknown, - LT_VCALLMS, LT_VCALLMSR, LT_COP2_Unknown,LT_COP2_Unknown,LT_COP2_SPECIAL2,LT_COP2_SPECIAL2,LT_COP2_SPECIAL2,LT_COP2_SPECIAL2, -}; - -void (*LT_COP2SPECIAL2PrintTable[128])() = -{ - LT_VADDAx ,LT_VADDAy ,LT_VADDAz ,LT_VADDAw ,LT_VSUBAx ,LT_VSUBAy ,LT_VSUBAz ,LT_VSUBAw, - LT_VMADDAx ,LT_VMADDAy ,LT_VMADDAz ,LT_VMADDAw ,LT_VMSUBAx ,LT_VMSUBAy ,LT_VMSUBAz ,LT_VMSUBAw, - LT_VITOF0 ,LT_VITOF4 ,LT_VITOF12 ,LT_VITOF15 ,LT_VFTOI0 ,LT_VFTOI4 ,LT_VFTOI12 ,LT_VFTOI15, - LT_VMULAx ,LT_VMULAy ,LT_VMULAz ,LT_VMULAw ,LT_VMULAq ,LT_VABS ,LT_VMULAi ,LT_VCLIPw, - LT_VADDAq ,LT_VMADDAq ,LT_VADDAi ,LT_VMADDAi ,LT_VSUBAq ,LT_VMSUBAq ,LT_VSUBAi ,LT_VMSUBAi, - LT_VADDA ,LT_VMADDA ,LT_VMULA ,LT_COP2_Unknown,LT_VSUBA ,LT_VMSUBA ,LT_VOPMULA ,LT_VNOP, - LT_VMOVE ,LT_VMR32 ,LT_COP2_Unknown,LT_COP2_Unknown,LT_VLQI ,LT_VSQI ,LT_VLQD ,LT_VSQD, - LT_VDIV ,LT_VSQRT ,LT_VRSQRT ,LT_VWAITQ ,LT_VMTIR ,LT_VMFIR ,LT_VILWR ,LT_VISWR, - LT_VRNEXT ,LT_VRGET ,LT_VRINIT ,LT_VRXOR ,LT_COP2_Unknown,LT_COP2_Unknown,LT_COP2_Unknown,LT_COP2_Unknown, - LT_COP2_Unknown,LT_COP2_Unknown,LT_COP2_Unknown,LT_COP2_Unknown,LT_COP2_Unknown,LT_COP2_Unknown,LT_COP2_Unknown,LT_COP2_Unknown, - LT_COP2_Unknown,LT_COP2_Unknown,LT_COP2_Unknown,LT_COP2_Unknown,LT_COP2_Unknown,LT_COP2_Unknown,LT_COP2_Unknown,LT_COP2_Unknown, - LT_COP2_Unknown,LT_COP2_Unknown,LT_COP2_Unknown,LT_COP2_Unknown,LT_COP2_Unknown,LT_COP2_Unknown,LT_COP2_Unknown,LT_COP2_Unknown, - LT_COP2_Unknown,LT_COP2_Unknown,LT_COP2_Unknown,LT_COP2_Unknown,LT_COP2_Unknown,LT_COP2_Unknown,LT_COP2_Unknown,LT_COP2_Unknown, - LT_COP2_Unknown,LT_COP2_Unknown,LT_COP2_Unknown,LT_COP2_Unknown,LT_COP2_Unknown,LT_COP2_Unknown,LT_COP2_Unknown,LT_COP2_Unknown, - LT_COP2_Unknown,LT_COP2_Unknown,LT_COP2_Unknown,LT_COP2_Unknown,LT_COP2_Unknown,LT_COP2_Unknown,LT_COP2_Unknown,LT_COP2_Unknown, - LT_COP2_Unknown,LT_COP2_Unknown,LT_COP2_Unknown,LT_COP2_Unknown,LT_COP2_Unknown,LT_COP2_Unknown,LT_COP2_Unknown,LT_COP2_Unknown, -}; diff --git a/pcsx2/DebugTools/cpuopsDebug.h b/pcsx2/DebugTools/cpuopsDebug.h deleted file mode 100644 index 955222b547..0000000000 --- a/pcsx2/DebugTools/cpuopsDebug.h +++ /dev/null @@ -1,456 +0,0 @@ -/* Pcsx2 - Pc Ps2 Emulator - * Copyright (C) 2002-2008 Pcsx2 Team - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA - */ - -void UpdateR5900op(); -extern void (*LT_OpcodePrintTable[64])(); -extern void (*LT_SpecialPrintTable[64])(); -extern void (*LT_REGIMMPrintTable[32])(); -extern void (*LT_MMIPrintTable[64])(); -extern void (*LT_MMI0PrintTable[32])(); -extern void (*LT_MMI1PrintTable[32])(); -extern void (*LT_MMI2PrintTable[32])(); -extern void (*LT_MMI3PrintTable[32])(); -extern void (*LT_COP0PrintTable[32])(); -extern void (*LT_COP0BC0PrintTable[32])(); -extern void (*LT_COP0C0PrintTable[64])(); -extern void (*LT_COP1PrintTable[32])(); -extern void (*LT_COP1BC1PrintTable[32])(); -extern void (*LT_COP1SPrintTable[64])(); -extern void (*LT_COP1WPrintTable[64])(); -extern void (*LT_COP2PrintTable[32])(); -extern void (*LT_COP2BC2PrintTable[32])(); -extern void (*LT_COP2SPECIAL1PrintTable[64])(); -extern void (*LT_COP2SPECIAL2PrintTable[128])(); -// **********************Standard Opcodes************************** -int L_ADD=0; -int L_ADDI=0; -int L_ADDIU=0; -int L_ADDU=0; -int L_AND=0; -int L_ANDI=0; -int L_BEQ=0; -int L_BEQL=0; -int L_BGEZ=0; -int L_BGEZAL=0; -int L_BGEZALL=0; -int L_BGEZL=0; -int L_BGTZ=0; -int L_BGTZL=0; -int L_BLEZ=0; -int L_BLEZL=0; -int L_BLTZ=0; -int L_BLTZAL=0; -int L_BLTZALL=0; -int L_BLTZL=0; -int L_BNE=0; -int L_BNEL=0; -int L_BREAK=0; -int L_CACHE=0; -int L_DADD=0; -int L_DADDI=0; -int L_DADDIU=0; -int L_DADDU=0; -int L_DIV=0; -int L_DIVU=0; -int L_DSLL=0; -int L_DSLL32=0; -int L_DSLLV=0; -int L_DSRA=0; -int L_DSRA32=0; -int L_DSRAV=0; -int L_DSRL=0; -int L_DSRL32=0; -int L_DSRLV=0; -int L_DSUB=0; -int L_DSUBU=0; -int L_J=0; -int L_JAL=0; -int L_JALR=0; -int L_JR=0; -int L_LB=0; -int L_LBU=0; -int L_LD=0; -int L_LDL=0; -int L_LDR=0; -int L_LH=0; -int L_LHU=0; -int L_LQ=0; -int L_LQC2=0; -int L_LUI=0; -int L_LW=0; -int L_LWC1=0; -int L_LWL=0; -int L_LWR=0; -int L_LWU=0; -int L_MFHI=0; -int L_MFLO=0; -int L_MFSA=0; -int L_MOVN=0; -int L_MOVZ=0; -int L_MTHI=0; -int L_MTLO=0; -int L_MTSA=0; -int L_MTSAB=0; -int L_MTSAH=0; -int L_MULT=0; -int L_MULTU=0; -int L_NOR=0; -int L_OR=0; -int L_ORI=0; -int L_PREF=0; -int L_SB=0; -int L_SD=0; -int L_SDL=0; -int L_SDR=0; -int L_SH=0; -int L_SLL=0; -int L_SLLV=0; -int L_SLT=0; -int L_SLTI=0; -int L_SLTIU=0; -int L_SLTU=0; -int L_SQ=0; -int L_SQC2=0; -int L_SRA=0; -int L_SRAV=0; -int L_SRL=0; -int L_SRLV=0; -int L_SUB=0; -int L_SUBU=0; -int L_SW=0; -int L_SWC1=0; -int L_SWL=0; -int L_SWR=0; -int L_SYNC=0; -int L_SYSCALL=0; -int L_TEQ=0; -int L_TEQI=0; -int L_TGE=0; -int L_TGEI=0; -int L_TGEIU=0; -int L_TGEU=0; -int L_TLT=0; -int L_TLTI=0; -int L_TLTIU=0; -int L_TLTU=0; -int L_TNE=0; -int L_TNEI=0; -int L_XOR=0; -int L_XORI=0; - - - - -//*****************MMI OPCODES********************************* -int L_MADD=0; -int L_MADDU=0; -int L_PLZCW=0; -int L_MADD1=0; -int L_MADDU1=0; -int L_MFHI1=0; -int L_MTHI1=0; -int L_MFLO1=0; -int L_MTLO1=0; -int L_MULT1=0; -int L_MULTU1=0; -int L_DIV1=0; -int L_DIVU1=0; -int L_PMFHL=0; -int L_PMTHL=0; -int L_PSLLH=0; -int L_PSRLH=0; -int L_PSRAH=0; -int L_PSLLW=0; -int L_PSRLW=0; -int L_PSRAW=0; -//*****************END OF MMI OPCODES************************** -//*************************MMI0 OPCODES************************ - -int L_PADDW=0; -int L_PSUBW=0; -int L_PCGTW=0; -int L_PMAXW=0; -int L_PADDH=0; -int L_PSUBH=0; -int L_PCGTH=0; -int L_PMAXH=0; -int L_PADDB=0; -int L_PSUBB=0; -int L_PCGTB=0; -int L_PADDSW=0; -int L_PSUBSW=0; -int L_PEXTLW=0; -int L_PPACW=0; -int L_PADDSH=0; -int L_PSUBSH=0; -int L_PEXTLH=0; -int L_PPACH=0; -int L_PADDSB=0; -int L_PSUBSB=0; -int L_PEXTLB=0; -int L_PPACB=0; -int L_PEXT5=0; -int L_PPAC5=0; -//***END OF MMI0 OPCODES****************************************** -//**********MMI1 OPCODES************************************** -int L_PABSW=0; -int L_PCEQW=0; -int L_PMINW=0; -int L_PADSBH=0; -int L_PABSH=0; -int L_PCEQH=0; -int L_PMINH=0; -int L_PCEQB=0; -int L_PADDUW=0; -int L_PSUBUW=0; -int L_PEXTUW=0; -int L_PADDUH=0; -int L_PSUBUH=0; -int L_PEXTUH=0; -int L_PADDUB=0; -int L_PSUBUB=0; -int L_PEXTUB=0; -int L_QFSRV=0; -//********END OF MMI1 OPCODES*********************************** -//*********MMI2 OPCODES*************************************** -int L_PMADDW=0; -int L_PSLLVW=0; -int L_PSRLVW=0; -int L_PMSUBW=0; -int L_PMFHI=0; -int L_PMFLO=0; -int L_PINTH=0; -int L_PMULTW=0; -int L_PDIVW=0; -int L_PCPYLD=0; -int L_PMADDH=0; -int L_PHMADH=0; -int L_PAND=0; -int L_PXOR=0; -int L_PMSUBH=0; -int L_PHMSBH=0; -int L_PEXEH=0; -int L_PREVH=0; -int L_PMULTH=0; -int L_PDIVBW=0; -int L_PEXEW=0; -int L_PROT3W=0; -//*****END OF MMI2 OPCODES*********************************** -//*************************MMI3 OPCODES************************ -int L_PMADDUW=0; -int L_PSRAVW=0; -int L_PMTHI=0; -int L_PMTLO=0; -int L_PINTEH=0; -int L_PMULTUW=0; -int L_PDIVUW=0; -int L_PCPYUD=0; -int L_POR=0; -int L_PNOR=0; -int L_PEXCH=0; -int L_PCPYH=0; -int L_PEXCW=0; -//**********************END OF MMI3 OPCODES******************** -//**************************************************************************** -//** COP0 ** -//**************************************************************************** -int L_MFC0=0; -int L_MTC0=0; -int L_BC0F=0; -int L_BC0T=0; -int L_BC0FL=0; -int L_BC0TL=0; -int L_TLBR=0; -int L_TLBWI=0; -int L_TLBWR=0; -int L_TLBP=0; -int L_ERET=0; -int L_DI=0; -int L_EI=0; -//**************************************************************************** -//** END OF COP0 ** -//**************************************************************************** -//**************************************************************************** -//** COP1 - Floating Point Unit (FPU) ** -//**************************************************************************** -int L_MFC1=0; -int L_CFC1=0; -int L_MTC1=0; -int L_CTC1=0; -int L_BC1F=0; -int L_BC1T=0; -int L_BC1FL=0; -int L_BC1TL=0; -int L_ADD_S=0; -int L_SUB_S=0; -int L_MUL_S=0; -int L_DIV_S=0; -int L_SQRT_S=0; -int L_ABS_S=0; -int L_MOV_S=0; -int L_NEG_S=0; -int L_RSQRT_S=0; -int L_ADDA_S=0; -int L_SUBA_S=0; -int L_MULA_S=0; -int L_MADD_S=0; -int L_MSUB_S=0; -int L_MADDA_S=0; -int L_MSUBA_S=0; -int L_CVT_W=0; -int L_MAX_S=0; -int L_MIN_S=0; -int L_C_F=0; -int L_C_EQ=0; -int L_C_LT=0; -int L_C_LE=0; - int L_CVT_S=0; -//**************************************************************************** -//** END OF COP1 ** -//**************************************************************************** -//**************************************************************************** -//** COP2 - (VU0) ** -//**************************************************************************** -int L_QMFC2=0; -int L_CFC2=0; -int L_QMTC2=0; -int L_CTC2=0; -int L_BC2F=0; -int L_BC2T=0; -int L_BC2FL=0; -int L_BC2TL=0; -int L_VADDx=0; -int L_VADDy=0; -int L_VADDz=0; -int L_VADDw=0; -int L_VSUBx=0; -int L_VSUBy=0; -int L_VSUBz=0; -int L_VSUBw=0; -int L_VMADDx=0; -int L_VMADDy=0; -int L_VMADDz=0; -int L_VMADDw=0; -int L_VMSUBx=0; -int L_VMSUBy=0; -int L_VMSUBz=0; -int L_VMSUBw=0; -int L_VMAXx=0; -int L_VMAXy=0; -int L_VMAXz=0; -int L_VMAXw=0; -int L_VMINIx=0; -int L_VMINIy=0; -int L_VMINIz=0; -int L_VMINIw=0; -int L_VMULx=0; -int L_VMULy=0; -int L_VMULz=0; -int L_VMULw=0; -int L_VMULq=0; -int L_VMAXi=0; -int L_VMULi=0; -int L_VMINIi=0; -int L_VADDq=0; -int L_VMADDq=0; -int L_VADDi=0; -int L_VMADDi=0; -int L_VSUBq=0; -int L_VMSUBq=0; -int L_VSUBi=0; -int L_VMSUBi=0; -int L_VADD=0; -int L_VMADD=0; -int L_VMUL=0; -int L_VMAX=0; -int L_VSUB=0; -int L_VMSUB=0; -int L_VOPMSUB=0; -int L_VMINI=0; -int L_VIADD=0; -int L_VISUB=0; -int L_VIADDI=0; -int L_VIAND=0; -int L_VIOR=0; -int L_VCALLMS=0; -int L_VCALLMSR=0; -int L_VADDAx=0; -int L_VADDAy=0; -int L_VADDAz=0; -int L_VADDAw=0; -int L_VSUBAx=0; -int L_VSUBAy=0; -int L_VSUBAz=0; -int L_VSUBAw=0; -int L_VMADDAx=0; -int L_VMADDAy=0; -int L_VMADDAz=0; -int L_VMADDAw=0; -int L_VMSUBAx=0; -int L_VMSUBAy=0; -int L_VMSUBAz=0; -int L_VMSUBAw=0; -int L_VITOF0=0; -int L_VITOF4=0; -int L_VITOF12=0; -int L_VITOF15=0; -int L_VFTOI0=0; -int L_VFTOI4=0; -int L_VFTOI12=0; -int L_VFTOI15=0; -int L_VMULAx=0; -int L_VMULAy=0; -int L_VMULAz=0; -int L_VMULAw=0; -int L_VMULAq=0; -int L_VABS=0; -int L_VMULAi=0; -int L_VCLIPw=0; -int L_VADDAq=0; -int L_VMADDAq=0; -int L_VADDAi=0; -int L_VMADDAi=0; -int L_VSUBAq=0; -int L_VMSUBAq=0; -int L_VSUBAi=0; -int L_VMSUBAi=0; -int L_VADDA=0; -int L_VMADDA=0; -int L_VMULA=0; -int L_VSUBA=0; -int L_VMSUBA=0; -int L_VOPMULA=0; -int L_VNOP=0; -int L_VMOVE=0; -int L_VMR32=0; -int L_VLQI=0; -int L_VSQI=0; -int L_VLQD=0; -int L_VSQD=0; -int L_VDIV=0; -int L_VSQRT=0; -int L_VRSQRT=0; -int L_VWAITQ=0; -int L_VMTIR=0; -int L_VMFIR=0; -int L_VILWR=0; -int L_VISWR=0; -int L_VRNEXT=0; -int L_VRGET=0; -int L_VRINIT=0; -int L_VRXOR=0; diff --git a/pcsx2/Elfheader.cpp b/pcsx2/Elfheader.cpp index 98ddfd8860..e2a9fa7eb0 100644 --- a/pcsx2/Elfheader.cpp +++ b/pcsx2/Elfheader.cpp @@ -22,6 +22,7 @@ #include "CDVDisodrv.h" using namespace std; +using namespace R5900; #ifdef _MSC_VER #pragma warning(disable:4996) //ignore the stricmp deprecated warning @@ -506,7 +507,7 @@ void ElfApplyPatches() ssprintf( filename, "%8.8x", params ElfCRC ); // if patches found the following status msg will be overwritten - Console::SetTitle( fmt_string( "Game running without patches. [CRC=%S]", params &filename ) ); + Console::SetTitle( fmt_string( "Game running without patches. [CRC=%hs]", params &filename ) ); if(LoadPatch( filename ) != 0) { diff --git a/pcsx2/FPU.cpp b/pcsx2/FPU.cpp index 85f75e96d1..507d51aa50 100644 --- a/pcsx2/FPU.cpp +++ b/pcsx2/FPU.cpp @@ -148,6 +148,10 @@ using namespace std; // for min / max intDoBranch( _BranchTarget_ ); \ } else cpuRegs.pc += 4; +namespace R5900 { +namespace Interpreter { +namespace OpcodeImpl +{ //**************************************************************** // FPU Opcodes @@ -359,19 +363,24 @@ void SUBA_S() { checkUnderflow( _FAValUl_, FPUflagU | FPUflagSU, 1 ); } -namespace EE { namespace Interpreter{ namespace OpcodeImpl -{ - void LWC1() { - u32 addr; - addr = cpuRegs.GPR.r[_Rs_].UL[0] + (s32)(s16)(cpuRegs.code & 0xffff); - if (addr & 0x00000003) { SysPrintf( "FPU (LWC1 Opcode): Invalid Memory Address\n" ); return; } // Should signal an exception? - memRead32(addr, &fpuRegs.fpr[_Rt_].UL); - } +///////////////////////////////////////////////////////////////////// +// COP1 (FPU) Load/Store Instructions + +// These are actually EE opcodes but since they're related to FPU registers and such they +// seem more appropriately located here. + +void LWC1() { + u32 addr; + addr = cpuRegs.GPR.r[_Rs_].UL[0] + (s32)(s16)(cpuRegs.code & 0xffff); + if (addr & 0x00000003) { Console::Error( "FPU (LWC1 Opcode): Invalid Memory Address" ); return; } // Should signal an exception? + memRead32(addr, &fpuRegs.fpr[_Rt_].UL); +} + +void SWC1() { + u32 addr; + addr = cpuRegs.GPR.r[_Rs_].UL[0] + (s32)(s16)(cpuRegs.code & 0xffff); + if (addr & 0x00000003) { Console::Error( "FPU (SWC1 Opcode): Invalid Memory Address" ); return; } // Should signal an exception? + memWrite32(addr, fpuRegs.fpr[_Rt_].UL); +} - void SWC1() { - u32 addr; - addr = cpuRegs.GPR.r[_Rs_].UL[0] + (s32)(s16)(cpuRegs.code & 0xffff); - if (addr & 0x00000003) { SysPrintf( "FPU (SWC1 Opcode): Invalid Memory Address\n" ); return; } // Should signal an exception? - memWrite32(addr, fpuRegs.fpr[_Rt_].UL); - } }}} \ No newline at end of file diff --git a/pcsx2/GS.cpp b/pcsx2/GS.cpp index 69ce546eb5..d52da89384 100644 --- a/pcsx2/GS.cpp +++ b/pcsx2/GS.cpp @@ -28,6 +28,8 @@ using namespace Threading; using namespace std; +using namespace R5900; + #ifdef DEBUG #define MTGS_LOG SysPrintf #else @@ -1228,7 +1230,6 @@ void gsResetFrameSkip() _gs_ResetFrameskip(); } -void frameLimitReset(); // defined in Counters.c void gsDynamicSkipEnable() { if( !m_StrictSkipping ) return; diff --git a/pcsx2/GS.h b/pcsx2/GS.h index 849d2b5233..cae8927bcf 100644 --- a/pcsx2/GS.h +++ b/pcsx2/GS.h @@ -265,22 +265,25 @@ void gsWrite16(u32 mem, u16 value); void gsWrite32(u32 mem, u32 value); void gsWrite64(u32 mem, u64 value); -void gsConstWrite8(u32 mem, int mmreg); -void gsConstWrite16(u32 mem, int mmreg); -void gsConstWrite32(u32 mem, int mmreg); -void gsConstWrite64(u32 mem, int mmreg); -void gsConstWrite128(u32 mem, int mmreg); - u8 gsRead8(u32 mem); u16 gsRead16(u32 mem); u32 gsRead32(u32 mem); u64 gsRead64(u32 mem); -int gsConstRead8(u32 x86reg, u32 mem, u32 sign); -int gsConstRead16(u32 x86reg, u32 mem, u32 sign); -int gsConstRead32(u32 x86reg, u32 mem); -void gsConstRead64(u32 mem, int mmreg); -void gsConstRead128(u32 mem, int xmmreg); +namespace Dynarec +{ + void gsConstWrite8(u32 mem, int mmreg); + void gsConstWrite16(u32 mem, int mmreg); + void gsConstWrite32(u32 mem, int mmreg); + void gsConstWrite64(u32 mem, int mmreg); + void gsConstWrite128(u32 mem, int mmreg); + + int gsConstRead8(u32 x86reg, u32 mem, u32 sign); + int gsConstRead16(u32 x86reg, u32 mem, u32 sign); + int gsConstRead32(u32 x86reg, u32 mem); + void gsConstRead64(u32 mem, int mmreg); + void gsConstRead128(u32 mem, int xmmreg); +} void gsIrq(); extern void gsInterrupt(); diff --git a/pcsx2/Hw.cpp b/pcsx2/Hw.cpp index f77678391a..b84ea88696 100644 --- a/pcsx2/Hw.cpp +++ b/pcsx2/Hw.cpp @@ -28,6 +28,9 @@ #include +using namespace Dynarec; +using namespace Dynarec::R5900; + #ifndef PCSX2_VIRTUAL_MEM u8 *psH; // hw mem u16 *psHW; diff --git a/pcsx2/Hw.h b/pcsx2/Hw.h index 48cbebd0f8..8ea0c35dcb 100644 --- a/pcsx2/Hw.h +++ b/pcsx2/Hw.h @@ -38,13 +38,11 @@ extern u64 *psHD; #define psHu32(mem) (*(u32*)&PS2MEM_HW[(mem) & 0xffff]) #define psHu64(mem) (*(u64*)&PS2MEM_HW[(mem) & 0xffff]) -extern u32 g_nextBranchCycle; -extern int cpuSetNextBranch( u32 startCycle, s32 delta ); -extern int cpuSetNextBranchDelta( s32 delta ); -extern int cpuTestCycle( u32 startCycle, s32 delta ); -extern void cpuSetBranch(); - +namespace R5900{ extern void CPU_INT( u32 n, s32 ecycle ); +} + +using R5900::CPU_INT; // VIF0 -- 0x10004000 -- psH[0x4000] // VIF1 -- 0x10005000 -- psH[0x5000] diff --git a/pcsx2/IPU/IPU.cpp b/pcsx2/IPU/IPU.cpp index 576fe81afa..c713d5c0dd 100644 --- a/pcsx2/IPU/IPU.cpp +++ b/pcsx2/IPU/IPU.cpp @@ -30,6 +30,9 @@ using namespace std; // for min / max +using namespace Dynarec; +using namespace Dynarec::R5900; + // Zero cycle IRQ schedules aren't really good, but the IPU uses them. // Better to throw the IRQ inline: diff --git a/pcsx2/InterTables.cpp b/pcsx2/InterTables.cpp index a77204cc95..fa5fe1ade9 100644 --- a/pcsx2/InterTables.cpp +++ b/pcsx2/InterTables.cpp @@ -19,39 +19,79 @@ //all tables for R5900 are define here.. #include "InterTables.h" +#include "R5900.h" -namespace EE +#include "x86/iR5900AritImm.h" +#include "x86/iR5900Arit.h" +#include "x86/iR5900MultDiv.h" +#include "x86/iR5900Shift.h" +#include "x86/iR5900Branch.h" +#include "x86/iR5900Jump.h" +#include "x86/iR5900LoadStore.h" +#include "x86/iR5900Move.h" +#include "x86/iMMI.h" +#include "x86/iCP0.h" +#include "x86/iFPU.h" + +namespace R5900 { namespace Opcodes { + // Generates an entry for the given opcode name. + // Assumes the default function naming schemes for interpreter and recompiler functions. + # define MakeOpcode( name, cycles ) \ + static const OPCODE name = { \ + #name, \ + cycles, \ + NULL, \ + R5900::Interpreter::OpcodeImpl::name, \ + Dynarec::R5900::OpcodeImpl::rec##name, \ + R5900::OpcodeDisasm::name \ + } + + # define MakeOpcodeClass( name ) \ + static const OPCODE name = { \ + #name, \ + 0, \ + R5900::Opcodes::Class_##name, \ + NULL, \ + NULL, \ + NULL \ + } + // We're working on new hopefully better cycle ratios, but they're still a WIP. // And yes this whole thing is an ugly hack. I'll clean it up once we have // a better idea how exactly the cycle ratios will work best. - static const int Cycles_Default = 9; - static const int Cycles_Branch = 12; + namespace Cycles + { + static const int Default = 9; + static const int Branch = 11; + static const int CopDefault = 7; - static const int Cycles_Mult = 2*8; - static const int Cycles_Div = 13*8; - static const int Cycles_FPU_Sqrt = 4*8; - static const int Cycles_MMI_Mult = 3*8; - static const int Cycles_MMI_Div = 22*8; + static const int Mult = 2*8; + static const int Div = 14*8; + static const int MMI_Mult = 3*8; + static const int MMI_Div = 22*8; - static const int Cycles_Store = 20; // 21 for snes emu - static const int Cycles_Load = 11; // 13 for snes emu + static const int FPU_Mult = 12; - static const int Cycles_Misc = 7; + static const int Store = 21; + static const int Load = 11; + } + + using namespace Cycles; MakeOpcode( Unknown, Default ); MakeOpcode( MMI_Unknown, Default ); + MakeOpcode( COP0_Unknown, Default ); + MakeOpcode( COP1_Unknown, Default ); // Class Subset Opcodes // (not really opcodes, but rather entire subsets of other opcode classes) MakeOpcodeClass( SPECIAL ); MakeOpcodeClass( REGIMM ); - //MakeOpcodeClass( COP0 ); - //MakeOpcodeClass( COP1 ); //MakeOpcodeClass( COP2 ); MakeOpcodeClass( MMI ); MakeOpcodeClass( MMI0 ); @@ -59,11 +99,12 @@ namespace EE MakeOpcodeClass( MMI1 ); MakeOpcodeClass( MMI3 ); + MakeOpcodeClass( COP0 ); + MakeOpcodeClass( COP1 ); + // Misc Junk - MakeOpcode( COP0, Misc ); - MakeOpcode( COP1, Misc ); - MakeOpcode( COP2, Misc ); + MakeOpcode( COP2, Default ); MakeOpcode( CACHE, Default ); MakeOpcode( PREF, Default ); @@ -308,25 +349,92 @@ namespace EE MakeOpcode( PCPYH, Default ); MakeOpcode( PEXCW, Default ); + ////////////////////////////////////////////////////////// + // COP0 Instructions + + MakeOpcodeClass( COP0_C0 ); + MakeOpcodeClass( COP0_BC0 ); + + MakeOpcode( MFC0, CopDefault ); + MakeOpcode( MTC0, CopDefault ); + + MakeOpcode( BC0F, Branch ); + MakeOpcode( BC0T, Branch ); + MakeOpcode( BC0FL, Branch ); + MakeOpcode( BC0TL, Branch ); + + MakeOpcode( TLBR, CopDefault ); + MakeOpcode( TLBWI, CopDefault ); + MakeOpcode( TLBWR, CopDefault ); + MakeOpcode( TLBP, CopDefault ); + MakeOpcode( ERET, CopDefault ); + MakeOpcode( EI, CopDefault ); + MakeOpcode( DI, CopDefault ); + + ////////////////////////////////////////////////////////// + // COP1 Instructions! + + MakeOpcodeClass( COP1_BC1 ); + MakeOpcodeClass( COP1_S ); + MakeOpcodeClass( COP1_W ); // contains CVT_S instruction *only* + + MakeOpcode( MFC1, CopDefault ); + MakeOpcode( CFC1, CopDefault ); + MakeOpcode( MTC1, CopDefault ); + MakeOpcode( CTC1, CopDefault ); + + MakeOpcode( BC1F, Branch ); + MakeOpcode( BC1T, Branch ); + MakeOpcode( BC1FL, Branch ); + MakeOpcode( BC1TL, Branch ); + + MakeOpcode( ADD_S, CopDefault ); + MakeOpcode( ADDA_S, CopDefault ); + MakeOpcode( SUB_S, CopDefault ); + MakeOpcode( SUBA_S, CopDefault ); + + MakeOpcode( ABS_S, CopDefault ); + MakeOpcode( MOV_S, CopDefault ); + MakeOpcode( NEG_S, CopDefault ); + MakeOpcode( MAX_S, CopDefault ); + MakeOpcode( MIN_S, CopDefault ); + + MakeOpcode( MUL_S, FPU_Mult ); + MakeOpcode( DIV_S, 3*8 ); + MakeOpcode( SQRT_S, 3*8 ); + MakeOpcode( RSQRT_S, 4*8 ); + MakeOpcode( MULA_S, FPU_Mult ); + MakeOpcode( MADD_S, FPU_Mult ); + MakeOpcode( MSUB_S, FPU_Mult ); + MakeOpcode( MADDA_S, FPU_Mult ); + MakeOpcode( MSUBA_S, FPU_Mult ); + + MakeOpcode( C_F, CopDefault ); + MakeOpcode( C_EQ, CopDefault ); + MakeOpcode( C_LT, CopDefault ); + MakeOpcode( C_LE, CopDefault ); + + MakeOpcode( CVT_S, CopDefault ); + MakeOpcode( CVT_W, CopDefault ); } namespace OpcodeTables { using namespace Opcodes; - const OPCODE Standard[64] = + const OPCODE tbl_Standard[64] = { SPECIAL, REGIMM, J, JAL, BEQ, BNE, BLEZ, BGTZ, ADDI, ADDIU, SLTI, SLTIU, ANDI, ORI, XORI, LUI, COP0, COP1, COP2, Unknown, BEQL, BNEL, BLEZL, BGTZL, - DADDI, DADDIU, LDL, LDR, Opcodes::MMI, Unknown, LQ, SQ, + DADDI, DADDIU, LDL, LDR, MMI, Unknown, LQ, SQ, LB, LH, LWL, LW, LBU, LHU, LWR, LWU, SB, SH, SWL, SW, SDL, SDR, SWR, CACHE, Unknown, LWC1, Unknown, PREF, Unknown, Unknown, LQC2, LD, Unknown, SWC1, Unknown, Unknown, Unknown, Unknown, SQC2, SD }; - const OPCODE Special[64] = + static const OPCODE tbl_Special[64] = { SLL, Unknown, SRL, SRA, SLLV, Unknown, SRLV, SRAV, JR, JALR, MOVZ, MOVN, SYSCALL, BREAK, Unknown, SYNC, @@ -338,26 +446,26 @@ namespace EE DSLL, Unknown, DSRL, DSRA, DSLL32, Unknown, DSRL32, DSRA32 }; - const OPCODE RegImm[32] = { + static const OPCODE tbl_RegImm[32] = { BLTZ, BGEZ, BLTZL, BGEZL, Unknown, Unknown, Unknown, Unknown, TGEI, TGEIU, TLTI, TLTIU, TEQI, Unknown, TNEI, Unknown, BLTZAL, BGEZAL, BLTZALL, BGEZALL, Unknown, Unknown, Unknown, Unknown, MTSAB, MTSAH , Unknown, Unknown, Unknown, Unknown, Unknown, Unknown, }; - const OPCODE MMI[64] = + static const OPCODE tbl_MMI[64] = { MADD, MADDU, MMI_Unknown, MMI_Unknown, PLZCW, MMI_Unknown, MMI_Unknown, MMI_Unknown, - Opcodes::MMI0, Opcodes::MMI2, MMI_Unknown, MMI_Unknown, MMI_Unknown, MMI_Unknown, MMI_Unknown, MMI_Unknown, + MMI0, MMI2, MMI_Unknown, MMI_Unknown, MMI_Unknown, MMI_Unknown, MMI_Unknown, MMI_Unknown, MFHI1, MTHI1, MFLO1, MTLO1, MMI_Unknown, MMI_Unknown, MMI_Unknown, MMI_Unknown, MULT1, MULTU1, DIV1, DIVU1, MMI_Unknown, MMI_Unknown, MMI_Unknown, MMI_Unknown, MADD1, MADDU1, MMI_Unknown, MMI_Unknown, MMI_Unknown, MMI_Unknown, MMI_Unknown, MMI_Unknown, - Opcodes::MMI1, Opcodes::MMI3, MMI_Unknown, MMI_Unknown, MMI_Unknown, MMI_Unknown, MMI_Unknown, MMI_Unknown, + MMI1, MMI3, MMI_Unknown, MMI_Unknown, MMI_Unknown, MMI_Unknown, MMI_Unknown, MMI_Unknown, PMFHL, PMTHL, MMI_Unknown, MMI_Unknown, PSLLH, MMI_Unknown, PSRLH, PSRAH, MMI_Unknown, MMI_Unknown, MMI_Unknown, MMI_Unknown, PSLLW, MMI_Unknown, PSRLW, PSRAW, }; - const OPCODE MMI0[32] = + static const OPCODE tbl_MMI0[32] = { PADDW, PSUBW, PCGTW, PMAXW, PADDH, PSUBH, PCGTH, PMAXH, @@ -369,7 +477,7 @@ namespace EE MMI_Unknown, MMI_Unknown, PEXT5, PPAC5, }; - const OPCODE MMI1[32] = + static const OPCODE tbl_MMI1[32] = { MMI_Unknown, PABSW, PCEQW, PMINW, PADSBH, PABSH, PCEQH, PMINH, @@ -382,7 +490,7 @@ namespace EE }; - const OPCODE MMI2[32] = + static const OPCODE tbl_MMI2[32] = { PMADDW, MMI_Unknown, PSLLVW, PSRLVW, PMSUBW, MMI_Unknown, MMI_Unknown, MMI_Unknown, @@ -394,7 +502,7 @@ namespace EE PMULTH, PDIVBW, PEXEW, PROT3W, }; - const OPCODE MMI3[32] = + static const OPCODE tbl_MMI3[32] = { PMADDUW, MMI_Unknown, MMI_Unknown, PSRAVW, MMI_Unknown, MMI_Unknown, MMI_Unknown, MMI_Unknown, @@ -406,72 +514,105 @@ namespace EE MMI_Unknown, MMI_Unknown, PEXCW, MMI_Unknown, }; - } // end namespace EE::OpcodeTables -} // end namespace EE + static const OPCODE tbl_COP0[32] = + { + MFC0, COP0_Unknown, COP0_Unknown, COP0_Unknown, MTC0, COP0_Unknown, COP0_Unknown, COP0_Unknown, + COP0_BC0, COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown, + COP0_C0, COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown, + COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown, + }; -void (*Int_COP0PrintTable[32])() = -{ - MFC0, COP0_Unknown, COP0_Unknown, COP0_Unknown, MTC0, COP0_Unknown, COP0_Unknown, COP0_Unknown, - COP0_BC0, COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown, - COP0_Func, COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown, - COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown, -}; + static const OPCODE tbl_COP0_BC0[32] = + { + BC0F, BC0T, BC0FL, BC0TL, COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown, + COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown, + COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown, + COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown, + }; -void (*Int_COP0BC0PrintTable[32])() = -{ - BC0F, BC0T, BC0FL, BC0TL, COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown, - COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown, - COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown, - COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown, -}; + static const OPCODE tbl_COP0_C0[64] = + { + COP0_Unknown, TLBR, TLBWI, COP0_Unknown, COP0_Unknown, COP0_Unknown, TLBWR, COP0_Unknown, + TLBP, COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown, + COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown, + ERET, COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown, + COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown, + COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown, + COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown, + EI, DI, COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown + }; -void (*Int_COP0C0PrintTable[64])() = { - COP0_Unknown, TLBR, TLBWI, COP0_Unknown, COP0_Unknown, COP0_Unknown, TLBWR, COP0_Unknown, - TLBP, COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown, - COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown, - ERET, COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown, - COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown, - COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown, - COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown, - EI, DI, COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown, COP0_Unknown -}; + static const OPCODE tbl_COP1[32] = + { + MFC1, COP1_Unknown, CFC1, COP1_Unknown, MTC1, COP1_Unknown, CTC1, COP1_Unknown, + COP1_BC1, COP1_Unknown, COP1_Unknown, COP1_Unknown, COP1_Unknown, COP1_Unknown, COP1_Unknown, COP1_Unknown, + COP1_S, COP1_Unknown, COP1_Unknown, COP1_Unknown, COP1_W, COP1_Unknown, COP1_Unknown, COP1_Unknown, + COP1_Unknown, COP1_Unknown, COP1_Unknown, COP1_Unknown, COP1_Unknown, COP1_Unknown, COP1_Unknown, COP1_Unknown, + }; -void (*Int_COP1PrintTable[32])() = { - MFC1, COP1_Unknown, CFC1, COP1_Unknown, MTC1, COP1_Unknown, CTC1, COP1_Unknown, - COP1_BC1, COP1_Unknown, COP1_Unknown, COP1_Unknown, COP1_Unknown, COP1_Unknown, COP1_Unknown, COP1_Unknown, - COP1_S, COP1_Unknown, COP1_Unknown, COP1_Unknown, COP1_W, COP1_Unknown, COP1_Unknown, COP1_Unknown, - COP1_Unknown, COP1_Unknown, COP1_Unknown, COP1_Unknown, COP1_Unknown, COP1_Unknown, COP1_Unknown, COP1_Unknown, -}; + static const OPCODE tbl_COP1_BC1[32] = + { + BC1F, BC1T, BC1FL, BC1TL, COP1_Unknown, COP1_Unknown, COP1_Unknown, COP1_Unknown, + COP1_Unknown, COP1_Unknown, COP1_Unknown, COP1_Unknown, COP1_Unknown, COP1_Unknown, COP1_Unknown, COP1_Unknown, + COP1_Unknown, COP1_Unknown, COP1_Unknown, COP1_Unknown, COP1_Unknown, COP1_Unknown, COP1_Unknown, COP1_Unknown, + COP1_Unknown, COP1_Unknown, COP1_Unknown, COP1_Unknown, COP1_Unknown, COP1_Unknown, COP1_Unknown, COP1_Unknown, + }; -void (*Int_COP1BC1PrintTable[32])() = { - BC1F, BC1T, BC1FL, BC1TL, COP1_Unknown, COP1_Unknown, COP1_Unknown, COP1_Unknown, - COP1_Unknown, COP1_Unknown, COP1_Unknown, COP1_Unknown, COP1_Unknown, COP1_Unknown, COP1_Unknown, COP1_Unknown, - COP1_Unknown, COP1_Unknown, COP1_Unknown, COP1_Unknown, COP1_Unknown, COP1_Unknown, COP1_Unknown, COP1_Unknown, - COP1_Unknown, COP1_Unknown, COP1_Unknown, COP1_Unknown, COP1_Unknown, COP1_Unknown, COP1_Unknown, COP1_Unknown, -}; + static const OPCODE tbl_COP1_S[64] = + { + ADD_S, SUB_S, MUL_S, DIV_S, SQRT_S, ABS_S, MOV_S, NEG_S, + COP1_Unknown,COP1_Unknown,COP1_Unknown,COP1_Unknown,COP1_Unknown,COP1_Unknown,COP1_Unknown,COP1_Unknown, + COP1_Unknown,COP1_Unknown,COP1_Unknown,COP1_Unknown,COP1_Unknown,COP1_Unknown,RSQRT_S, COP1_Unknown, + ADDA_S, SUBA_S, MULA_S, COP1_Unknown,MADD_S, MSUB_S, MADDA_S, MSUBA_S, + COP1_Unknown,COP1_Unknown,COP1_Unknown,COP1_Unknown,CVT_W, COP1_Unknown,COP1_Unknown,COP1_Unknown, + MAX_S, MIN_S, COP1_Unknown,COP1_Unknown,COP1_Unknown,COP1_Unknown,COP1_Unknown,COP1_Unknown, + C_F, COP1_Unknown,C_EQ, COP1_Unknown,C_LT, COP1_Unknown,C_LE, COP1_Unknown, + COP1_Unknown,COP1_Unknown,COP1_Unknown,COP1_Unknown,COP1_Unknown,COP1_Unknown,COP1_Unknown,COP1_Unknown, + }; -void (*Int_COP1SPrintTable[64])() = { -ADD_S, SUB_S, MUL_S, DIV_S, SQRT_S, ABS_S, MOV_S, NEG_S, -COP1_Unknown,COP1_Unknown,COP1_Unknown,COP1_Unknown,COP1_Unknown,COP1_Unknown,COP1_Unknown,COP1_Unknown, -COP1_Unknown,COP1_Unknown,COP1_Unknown,COP1_Unknown,COP1_Unknown,COP1_Unknown,RSQRT_S, COP1_Unknown, -ADDA_S, SUBA_S, MULA_S, COP1_Unknown,MADD_S, MSUB_S, MADDA_S, MSUBA_S, -COP1_Unknown,COP1_Unknown,COP1_Unknown,COP1_Unknown,CVT_W, COP1_Unknown,COP1_Unknown,COP1_Unknown, -MAX_S, MIN_S, COP1_Unknown,COP1_Unknown,COP1_Unknown,COP1_Unknown,COP1_Unknown,COP1_Unknown, -C_F, COP1_Unknown,C_EQ, COP1_Unknown,C_LT, COP1_Unknown,C_LE, COP1_Unknown, -COP1_Unknown,COP1_Unknown,COP1_Unknown,COP1_Unknown,COP1_Unknown,COP1_Unknown,COP1_Unknown,COP1_Unknown, -}; - -void (*Int_COP1WPrintTable[64])() = { -COP1_Unknown,COP1_Unknown,COP1_Unknown,COP1_Unknown,COP1_Unknown,COP1_Unknown,COP1_Unknown,COP1_Unknown, -COP1_Unknown,COP1_Unknown,COP1_Unknown,COP1_Unknown,COP1_Unknown,COP1_Unknown,COP1_Unknown,COP1_Unknown, -COP1_Unknown,COP1_Unknown,COP1_Unknown,COP1_Unknown,COP1_Unknown,COP1_Unknown,COP1_Unknown,COP1_Unknown, -COP1_Unknown,COP1_Unknown,COP1_Unknown,COP1_Unknown,COP1_Unknown,COP1_Unknown,COP1_Unknown,COP1_Unknown, -CVT_S, COP1_Unknown,COP1_Unknown,COP1_Unknown,COP1_Unknown,COP1_Unknown,COP1_Unknown,COP1_Unknown, -COP1_Unknown,COP1_Unknown,COP1_Unknown,COP1_Unknown,COP1_Unknown,COP1_Unknown,COP1_Unknown,COP1_Unknown, -COP1_Unknown,COP1_Unknown,COP1_Unknown,COP1_Unknown,COP1_Unknown,COP1_Unknown,COP1_Unknown,COP1_Unknown, -COP1_Unknown,COP1_Unknown,COP1_Unknown,COP1_Unknown,COP1_Unknown,COP1_Unknown,COP1_Unknown,COP1_Unknown, -}; + static const OPCODE tbl_COP1_W[64] = + { + COP1_Unknown,COP1_Unknown,COP1_Unknown,COP1_Unknown,COP1_Unknown,COP1_Unknown,COP1_Unknown,COP1_Unknown, + COP1_Unknown,COP1_Unknown,COP1_Unknown,COP1_Unknown,COP1_Unknown,COP1_Unknown,COP1_Unknown,COP1_Unknown, + COP1_Unknown,COP1_Unknown,COP1_Unknown,COP1_Unknown,COP1_Unknown,COP1_Unknown,COP1_Unknown,COP1_Unknown, + COP1_Unknown,COP1_Unknown,COP1_Unknown,COP1_Unknown,COP1_Unknown,COP1_Unknown,COP1_Unknown,COP1_Unknown, + CVT_S, COP1_Unknown,COP1_Unknown,COP1_Unknown,COP1_Unknown,COP1_Unknown,COP1_Unknown,COP1_Unknown, + COP1_Unknown,COP1_Unknown,COP1_Unknown,COP1_Unknown,COP1_Unknown,COP1_Unknown,COP1_Unknown,COP1_Unknown, + COP1_Unknown,COP1_Unknown,COP1_Unknown,COP1_Unknown,COP1_Unknown,COP1_Unknown,COP1_Unknown,COP1_Unknown, + COP1_Unknown,COP1_Unknown,COP1_Unknown,COP1_Unknown,COP1_Unknown,COP1_Unknown,COP1_Unknown,COP1_Unknown, + }; + } // end namespace R5900::OpcodeTables + + namespace Opcodes + { + using namespace OpcodeTables; + + const OPCODE& Class_SPECIAL() { return tbl_Special[_Funct_]; } + const OPCODE& Class_REGIMM() { return tbl_RegImm[_Rt_]; } + + const OPCODE& Class_MMI() { return tbl_MMI[_Funct_]; } + const OPCODE& Class_MMI0() { return tbl_MMI0[_Sa_]; } + const OPCODE& Class_MMI1() { return tbl_MMI1[_Sa_]; } + const OPCODE& Class_MMI2() { return tbl_MMI2[_Sa_]; } + const OPCODE& Class_MMI3() { return tbl_MMI3[_Sa_]; } + + const OPCODE& Class_COP0() { return tbl_COP0[_Rs_]; } + const OPCODE& Class_COP0_BC0() { return tbl_COP0_BC0[(cpuRegs.code >> 16) & 0x03]; } + const OPCODE& Class_COP0_C0() { return tbl_COP0_C0[_Funct_]; } + + const OPCODE& Class_COP1() { return tbl_COP1[_Rs_]; } + const OPCODE& Class_COP1_BC1() { return tbl_COP1_BC1[_Rt_]; } + const OPCODE& Class_COP1_S() { return tbl_COP1_S[_Funct_]; } + const OPCODE& Class_COP1_W() { return tbl_COP1_W[_Funct_]; } + + // These are for future use when the COP2 tables are completed. + //const OPCODE& Class_COP2() { return tbl_COP2[_Rs_]; } + //const OPCODE& Class_COP2_BC2() { return tbl_COP2_BC2[_Rt_]; } + //const OPCODE& Class_COP2_SPECIAL() { return tbl_COP2_SPECIAL[_Funct_]; } + //const OPCODE& Class_COP2_SPECIAL2() { return tbl_COP2_SPECIAL2[(cpuRegs.code & 0x3) | ((cpuRegs.code >> 4) & 0x7c)]; } + } +} // end namespace R5900 void (*Int_COP2PrintTable[32])() = { COP2_Unknown, QMFC2, CFC2, COP2_Unknown, COP2_Unknown, QMTC2, CTC2, COP2_Unknown, diff --git a/pcsx2/InterTables.h b/pcsx2/InterTables.h index 1a5061863a..be9e01f542 100644 --- a/pcsx2/InterTables.h +++ b/pcsx2/InterTables.h @@ -22,91 +22,63 @@ #include "PS2Etypes.h" -#include "x86/iR5900AritImm.h" -#include "x86/iR5900Arit.h" -#include "x86/iR5900MultDiv.h" -#include "x86/iR5900Shift.h" -#include "x86/iR5900Branch.h" -#include "x86/iR5900Jump.h" -#include "x86/iR5900LoadStore.h" -#include "x86/iR5900Move.h" -#include "x86/iMMI.h" - -namespace EE { namespace Dynarec { namespace OpcodeImpl -{ - void recUnknown(); - void recMMI_Unknown(); - void recREGIMM() ; - void recSPECIAL(); - void recCOP0(); - void recCOP1(); - void recCOP2(); - void recMMI(); - void recMMI0(); - void recMMI1(); - void recMMI2(); - void recMMI3(); - - void recCACHE(); - void recPREF(); - void recSYSCALL(); - void recBREAK(); - void recSYNC(); - - void recMFSA(); - void recMTSA(); - void recMTSAB(); - void recMTSAH(); - - void recTGE(); - void recTGEU(); - void recTLT(); - void recTLTU(); - void recTEQ(); - void recTNE(); - void recTGEI(); - void recTGEIU(); - void recTLTI(); - void recTLTIU(); - void recTEQI(); - void recTNEI(); - -} } } - -// TODO : Move these into the EE::OpcodesTable namespace -extern void (*Int_COP0PrintTable[32])(); -extern void (*Int_COP0BC0PrintTable[32])(); -extern void (*Int_COP0C0PrintTable[64])(); -extern void (*Int_COP1PrintTable[32])(); -extern void (*Int_COP1BC1PrintTable[32])(); -extern void (*Int_COP1SPrintTable[64])(); -extern void (*Int_COP1WPrintTable[64])(); +// TODO : Move these into the OpcodeTables namespace extern void (*Int_COP2PrintTable[32])(); extern void (*Int_COP2BC2PrintTable[32])(); extern void (*Int_COP2SPECIAL1PrintTable[64])(); extern void (*Int_COP2SPECIAL2PrintTable[128])(); -void COP0_Unknown(); -void COP0_BC0(); -void COP0_Func(); -void COP1_BC1(); -void COP1_S(); -void COP1_W(); -void COP1_Unknown(); void COP2_BC2(); void COP2_SPECIAL(); -void COP2_Unknown(); void COP2_SPECIAL2(); +void COP2_Unknown(); -namespace EE + +namespace Dynarec { + namespace R5900 { + namespace OpcodeImpl + { + void recUnknown(); + void recCOP2(); + + void recCACHE(); + void recPREF(); + void recSYSCALL(); + void recBREAK(); + void recSYNC(); + + void recMFSA(); + void recMTSA(); + void recMTSAB(); + void recMTSAH(); + + void recTGE(); + void recTGEU(); + void recTLT(); + void recTLTU(); + void recTEQ(); + void recTNE(); + void recTGEI(); + void recTGEIU(); + void recTLTI(); + void recTLTIU(); + void recTEQI(); + void recTNEI(); + + } +} } // end namespace Dynarec::OpcodeImpl::EE + +namespace R5900 +{ + /////////////////////////////////////////////////////////////////////////// // Encapsulates information about every opcode on the Emotion Engine and // it's many co-processors. struct OPCODE { // Textual name of the instruction. - const char Name[12]; + const char Name[16]; // Number of cycles this instruction normally uses. u8 cycles; @@ -123,37 +95,19 @@ namespace EE // Generates a string representation of the instruction and it's parameters, // and pastes it into the given output parameter. - void (*decode)( std::string& output ); + void (*disasm)( std::string& output ); }; // Returns the current real instruction, as per the current cpuRegs settings. const OPCODE& GetCurrentInstruction(); - // Generates an entry for the given opcode name. - // Assumes the default function naming schemes for interpreter and recompiler functions. -# define MakeOpcode( name, cycles ) \ - static const OPCODE name = { \ - #name, \ - Cycles_##cycles, \ - NULL, \ - EE::Interpreter::OpcodeImpl::name, \ - EE::Dynarec::OpcodeImpl::rec##name, \ - EE::Debug::OpcodePrint::name \ - } - -# define MakeOpcodeClass( name ) \ - static const OPCODE name = { \ - #name, \ - 0, \ - EE::Opcodes::Class_##name, \ - NULL, \ - NULL, \ - NULL \ - } - namespace OpcodeTables { - extern const OPCODE Standard[64]; + using ::R5900::OPCODE; + + extern const OPCODE tbl_Standard[64]; + + /*extern const OPCODE Standard[64]; extern const OPCODE Special[64]; extern const OPCODE RegImm[32]; extern const OPCODE MMI[64]; @@ -161,10 +115,21 @@ namespace EE extern const OPCODE MMI1[32]; extern const OPCODE MMI2[32]; extern const OPCODE MMI3[32]; + + extern const OPCODE COP0[32]; + extern const OPCODE COP0_BC0[32]; + extern const OPCODE COP0_C0[64]; + + extern const OPCODE COP1[32]; + extern const OPCODE COP1_BC1[32]; + extern const OPCODE COP1_S[64]; + extern const OPCODE COP1_W[64];*/ } namespace Opcodes { + using ::R5900::OPCODE; + const OPCODE& Class_SPECIAL(); const OPCODE& Class_REGIMM(); const OPCODE& Class_MMI(); @@ -172,563 +137,607 @@ namespace EE const OPCODE& Class_MMI1(); const OPCODE& Class_MMI2(); const OPCODE& Class_MMI3(); - } - namespace Debug + const OPCODE& Class_COP0(); + const OPCODE& Class_COP0_BC0(); + const OPCODE& Class_COP0_C0(); + + const OPCODE& Class_COP1(); + const OPCODE& Class_COP1_BC1(); + const OPCODE& Class_COP1_S(); + const OPCODE& Class_COP1_W(); + } +} + +namespace R5900 +{ + namespace OpcodeDisasm { - namespace OpcodePrint - { //**************************************************************** - void Unknown( std::string& output ); - void COP0( std::string& output ); - void COP1( std::string& output ); - void COP2( std::string& output ); - void MMI_Unknown( std::string& output ); + void Unknown( std::string& output ); + void COP0_Unknown( std::string& output ); + void COP1_Unknown( std::string& output ); + void MMI_Unknown( std::string& output ); + + void COP2( std::string& output ); // **********************Standard Opcodes************************** - void J( std::string& output ); - void JAL( std::string& output ); - void BEQ( std::string& output ); - void BNE( std::string& output ); - void BLEZ( std::string& output ); - void BGTZ( std::string& output ); - void ADDI( std::string& output ); - void ADDIU( std::string& output ); - void SLTI( std::string& output ); - void SLTIU( std::string& output ); - void ANDI( std::string& output ); - void ORI( std::string& output ); - void XORI( std::string& output ); - void LUI( std::string& output ); - void BEQL( std::string& output ); - void BNEL( std::string& output ); - void BLEZL( std::string& output ); - void BGTZL( std::string& output ); - void DADDI( std::string& output ); - void DADDIU( std::string& output ); - void LDL( std::string& output ); - void LDR( std::string& output ); - void LB( std::string& output ); - void LH( std::string& output ); - void LWL( std::string& output ); - void LW( std::string& output ); - void LBU( std::string& output ); - void LHU( std::string& output ); - void LWR( std::string& output ); - void LWU( std::string& output ); - void SB( std::string& output ); - void SH( std::string& output ); - void SWL( std::string& output ); - void SW( std::string& output ); - void SDL( std::string& output ); - void SDR( std::string& output ); - void SWR( std::string& output ); - void CACHE( std::string& output ); - void LWC1( std::string& output ); - void PREF( std::string& output ); - void LQC2( std::string& output ); - void LD( std::string& output ); - void SQC2( std::string& output ); - void SD( std::string& output ); - void LQ( std::string& output ); - void SQ( std::string& output ); - void SWC1( std::string& output ); -//***************end of standard opcodes************************* -//***************SPECIAL OPCODES********************************** - void SLL( std::string& output ); - void SRL( std::string& output ); - void SRA( std::string& output ); - void SLLV( std::string& output ); - void SRLV( std::string& output ); - void SRAV( std::string& output ); - void JR( std::string& output ); - void JALR( std::string& output ); - void SYSCALL( std::string& output ); - void BREAK( std::string& output ); - void SYNC( std::string& output ); - void MFHI( std::string& output ); - void MTHI( std::string& output ); - void MFLO( std::string& output ); - void MTLO( std::string& output ); - void DSLLV( std::string& output ); - void DSRLV( std::string& output ); - void DSRAV( std::string& output ); - void MULT( std::string& output ); - void MULTU( std::string& output ); - void DIV( std::string& output ); - void DIVU( std::string& output ); - void ADD( std::string& output ); - void ADDU( std::string& output ); - void SUB( std::string& output ); - void SUBU( std::string& output ); - void AND( std::string& output ); - void OR( std::string& output ); - void XOR( std::string& output ); - void NOR( std::string& output ); - void SLT( std::string& output ); - void SLTU( std::string& output ); - void DADD( std::string& output ); - void DADDU( std::string& output ); - void DSUB( std::string& output ); - void DSUBU( std::string& output ); - void TGE( std::string& output ); - void TGEU( std::string& output ); - void TLT( std::string& output ); - void TLTU( std::string& output ); - void TEQ( std::string& output ); - void TNE( std::string& output ); - void DSLL( std::string& output ); - void DSRL( std::string& output ); - void DSRA( std::string& output ); - void DSLL32( std::string& output ); - void DSRL32( std::string& output ); - void DSRA32( std::string& output ); - void MOVZ( std::string& output ); - void MOVN( std::string& output ); - void MFSA( std::string& output ); - void MTSA( std::string& output ); -//******************END OF SPECIAL OPCODES************************** - -//******************REGIMM OPCODES********************************** - void BLTZ( std::string& output ); - void BGEZ( std::string& output ); - void BLTZL( std::string& output ); - void BGEZL( std::string& output ); - void TGEI( std::string& output ); - void TGEIU( std::string& output ); - void TLTI( std::string& output ); - void TLTIU( std::string& output ); - void TEQI( std::string& output ); - void TNEI( std::string& output ); - void BLTZAL( std::string& output ); - void BGEZAL( std::string& output ); - void BLTZALL( std::string& output ); - void BGEZALL( std::string& output ); - void MTSAB( std::string& output ); - void MTSAH( std::string& output ); -//*****************END OF REGIMM OPCODES***************************** -//*****************MMI OPCODES********************************* - void MADD( std::string& output ); - void MADDU( std::string& output ); - void PLZCW( std::string& output ); - void MADD1( std::string& output ); - void MADDU1( std::string& output ); - void MFHI1( std::string& output ); - void MTHI1( std::string& output ); - void MFLO1( std::string& output ); - void MTLO1( std::string& output ); - void MULT1( std::string& output ); - void MULTU1( std::string& output ); - void DIV1( std::string& output ); - void DIVU1( std::string& output ); - void PMFHL( std::string& output ); - void PMTHL( std::string& output ); - void PSLLH( std::string& output ); - void PSRLH( std::string& output ); - void PSRAH( std::string& output ); - void PSLLW( std::string& output ); - void PSRLW( std::string& output ); - void PSRAW( std::string& output ); -//*****************END OF MMI OPCODES************************** -//*************************MMI0 OPCODES************************ - void PADDW( std::string& output ); - void PSUBW( std::string& output ); - void PCGTW( std::string& output ); - void PMAXW( std::string& output ); - void PADDH( std::string& output ); - void PSUBH( std::string& output ); - void PCGTH( std::string& output ); - void PMAXH( std::string& output ); - void PADDB( std::string& output ); - void PSUBB( std::string& output ); - void PCGTB( std::string& output ); - void PADDSW( std::string& output ); - void PSUBSW( std::string& output ); - void PEXTLW( std::string& output ); - void PPACW( std::string& output ); - void PADDSH( std::string& output ); - void PSUBSH( std::string& output ); - void PEXTLH( std::string& output ); - void PPACH( std::string& output ); - void PADDSB( std::string& output ); - void PSUBSB( std::string& output ); - void PEXTLB( std::string& output ); - void PPACB( std::string& output ); - void PEXT5( std::string& output ); - void PPAC5( std::string& output ); -//***END OF MMI0 OPCODES****************************************** -//**********MMI1 OPCODES************************************** - void PABSW( std::string& output ); - void PCEQW( std::string& output ); - void PMINW( std::string& output ); - void PADSBH( std::string& output ); - void PABSH( std::string& output ); - void PCEQH( std::string& output ); - void PMINH( std::string& output ); - void PCEQB( std::string& output ); - void PADDUW( std::string& output ); - void PSUBUW( std::string& output ); - void PEXTUW( std::string& output ); - void PADDUH( std::string& output ); - void PSUBUH( std::string& output ); - void PEXTUH( std::string& output ); - void PADDUB( std::string& output ); - void PSUBUB( std::string& output ); - void PEXTUB( std::string& output ); - void QFSRV( std::string& output ); -//********END OF MMI1 OPCODES*********************************** -//*********MMI2 OPCODES*************************************** - void PMADDW( std::string& output ); - void PSLLVW( std::string& output ); - void PSRLVW( std::string& output ); - void PMSUBW( std::string& output ); - void PMFHI( std::string& output ); - void PMFLO( std::string& output ); - void PINTH( std::string& output ); - void PMULTW( std::string& output ); - void PDIVW( std::string& output ); - void PCPYLD( std::string& output ); - void PMADDH( std::string& output ); - void PHMADH( std::string& output ); - void PAND( std::string& output ); - void PXOR( std::string& output ); - void PMSUBH( std::string& output ); - void PHMSBH( std::string& output ); - void PEXEH( std::string& output ); - void PREVH( std::string& output ); - void PMULTH( std::string& output ); - void PDIVBW( std::string& output ); - void PEXEW( std::string& output ); - void PROT3W( std::string& output ); -//*****END OF MMI2 OPCODES*********************************** -//*************************MMI3 OPCODES************************ - void PMADDUW( std::string& output ); - void PSRAVW( std::string& output ); - void PMTHI( std::string& output ); - void PMTLO( std::string& output ); - void PINTEH( std::string& output ); - void PMULTUW( std::string& output ); - void PDIVUW( std::string& output ); - void PCPYUD( std::string& output ); - void POR( std::string& output ); - void PNOR( std::string& output ); - void PEXCH( std::string& output ); - void PCPYH( std::string& output ); - void PEXCW( std::string& output ); -//**********************END OF MMI3 OPCODES******************** - } + void J( std::string& output ); + void JAL( std::string& output ); + void BEQ( std::string& output ); + void BNE( std::string& output ); + void BLEZ( std::string& output ); + void BGTZ( std::string& output ); + void ADDI( std::string& output ); + void ADDIU( std::string& output ); + void SLTI( std::string& output ); + void SLTIU( std::string& output ); + void ANDI( std::string& output ); + void ORI( std::string& output ); + void XORI( std::string& output ); + void LUI( std::string& output ); + void BEQL( std::string& output ); + void BNEL( std::string& output ); + void BLEZL( std::string& output ); + void BGTZL( std::string& output ); + void DADDI( std::string& output ); + void DADDIU( std::string& output ); + void LDL( std::string& output ); + void LDR( std::string& output ); + void LB( std::string& output ); + void LH( std::string& output ); + void LWL( std::string& output ); + void LW( std::string& output ); + void LBU( std::string& output ); + void LHU( std::string& output ); + void LWR( std::string& output ); + void LWU( std::string& output ); + void SB( std::string& output ); + void SH( std::string& output ); + void SWL( std::string& output ); + void SW( std::string& output ); + void SDL( std::string& output ); + void SDR( std::string& output ); + void SWR( std::string& output ); + void CACHE( std::string& output ); + void LWC1( std::string& output ); + void PREF( std::string& output ); + void LQC2( std::string& output ); + void LD( std::string& output ); + void SQC2( std::string& output ); + void SD( std::string& output ); + void LQ( std::string& output ); + void SQ( std::string& output ); + void SWC1( std::string& output ); +//*****************end of standard opcodes********************** +//********************SPECIAL OPCODES*************************** + void SLL( std::string& output ); + void SRL( std::string& output ); + void SRA( std::string& output ); + void SLLV( std::string& output ); + void SRLV( std::string& output ); + void SRAV( std::string& output ); + void JR( std::string& output ); + void JALR( std::string& output ); + void SYSCALL( std::string& output ); + void BREAK( std::string& output ); + void SYNC( std::string& output ); + void MFHI( std::string& output ); + void MTHI( std::string& output ); + void MFLO( std::string& output ); + void MTLO( std::string& output ); + void DSLLV( std::string& output ); + void DSRLV( std::string& output ); + void DSRAV( std::string& output ); + void MULT( std::string& output ); + void MULTU( std::string& output ); + void DIV( std::string& output ); + void DIVU( std::string& output ); + void ADD( std::string& output ); + void ADDU( std::string& output ); + void SUB( std::string& output ); + void SUBU( std::string& output ); + void AND( std::string& output ); + void OR( std::string& output ); + void XOR( std::string& output ); + void NOR( std::string& output ); + void SLT( std::string& output ); + void SLTU( std::string& output ); + void DADD( std::string& output ); + void DADDU( std::string& output ); + void DSUB( std::string& output ); + void DSUBU( std::string& output ); + void TGE( std::string& output ); + void TGEU( std::string& output ); + void TLT( std::string& output ); + void TLTU( std::string& output ); + void TEQ( std::string& output ); + void TNE( std::string& output ); + void DSLL( std::string& output ); + void DSRL( std::string& output ); + void DSRA( std::string& output ); + void DSLL32( std::string& output ); + void DSRL32( std::string& output ); + void DSRA32( std::string& output ); + void MOVZ( std::string& output ); + void MOVN( std::string& output ); + void MFSA( std::string& output ); + void MTSA( std::string& output ); +//*******************END OF SPECIAL OPCODES************************ +//***********************REGIMM OPCODES**************************** + void BLTZ( std::string& output ); + void BGEZ( std::string& output ); + void BLTZL( std::string& output ); + void BGEZL( std::string& output ); + void TGEI( std::string& output ); + void TGEIU( std::string& output ); + void TLTI( std::string& output ); + void TLTIU( std::string& output ); + void TEQI( std::string& output ); + void TNEI( std::string& output ); + void BLTZAL( std::string& output ); + void BGEZAL( std::string& output ); + void BLTZALL( std::string& output ); + void BGEZALL( std::string& output ); + void MTSAB( std::string& output ); + void MTSAH( std::string& output ); +//*******************END OF REGIMM OPCODES*********************** +//***********************MMI OPCODES***************************** + void MADD( std::string& output ); + void MADDU( std::string& output ); + void PLZCW( std::string& output ); + void MADD1( std::string& output ); + void MADDU1( std::string& output ); + void MFHI1( std::string& output ); + void MTHI1( std::string& output ); + void MFLO1( std::string& output ); + void MTLO1( std::string& output ); + void MULT1( std::string& output ); + void MULTU1( std::string& output ); + void DIV1( std::string& output ); + void DIVU1( std::string& output ); + void PMFHL( std::string& output ); + void PMTHL( std::string& output ); + void PSLLH( std::string& output ); + void PSRLH( std::string& output ); + void PSRAH( std::string& output ); + void PSLLW( std::string& output ); + void PSRLW( std::string& output ); + void PSRAW( std::string& output ); +//********************END OF MMI OPCODES*********************** +//***********************MMI0 OPCODES************************** + void PADDW( std::string& output ); + void PSUBW( std::string& output ); + void PCGTW( std::string& output ); + void PMAXW( std::string& output ); + void PADDH( std::string& output ); + void PSUBH( std::string& output ); + void PCGTH( std::string& output ); + void PMAXH( std::string& output ); + void PADDB( std::string& output ); + void PSUBB( std::string& output ); + void PCGTB( std::string& output ); + void PADDSW( std::string& output ); + void PSUBSW( std::string& output ); + void PEXTLW( std::string& output ); + void PPACW( std::string& output ); + void PADDSH( std::string& output ); + void PSUBSH( std::string& output ); + void PEXTLH( std::string& output ); + void PPACH( std::string& output ); + void PADDSB( std::string& output ); + void PSUBSB( std::string& output ); + void PEXTLB( std::string& output ); + void PPACB( std::string& output ); + void PEXT5( std::string& output ); + void PPAC5( std::string& output ); +//******************END OF MMI0 OPCODES*********************** +//*********************MMI1 OPCODES*************************** + void PABSW( std::string& output ); + void PCEQW( std::string& output ); + void PMINW( std::string& output ); + void PADSBH( std::string& output ); + void PABSH( std::string& output ); + void PCEQH( std::string& output ); + void PMINH( std::string& output ); + void PCEQB( std::string& output ); + void PADDUW( std::string& output ); + void PSUBUW( std::string& output ); + void PEXTUW( std::string& output ); + void PADDUH( std::string& output ); + void PSUBUH( std::string& output ); + void PEXTUH( std::string& output ); + void PADDUB( std::string& output ); + void PSUBUB( std::string& output ); + void PEXTUB( std::string& output ); + void QFSRV( std::string& output ); +//*****************END OF MMI1 OPCODES*********************** +//*********************MMI2 OPCODES************************** + void PMADDW( std::string& output ); + void PSLLVW( std::string& output ); + void PSRLVW( std::string& output ); + void PMSUBW( std::string& output ); + void PMFHI( std::string& output ); + void PMFLO( std::string& output ); + void PINTH( std::string& output ); + void PMULTW( std::string& output ); + void PDIVW( std::string& output ); + void PCPYLD( std::string& output ); + void PMADDH( std::string& output ); + void PHMADH( std::string& output ); + void PAND( std::string& output ); + void PXOR( std::string& output ); + void PMSUBH( std::string& output ); + void PHMSBH( std::string& output ); + void PEXEH( std::string& output ); + void PREVH( std::string& output ); + void PMULTH( std::string& output ); + void PDIVBW( std::string& output ); + void PEXEW( std::string& output ); + void PROT3W( std::string& output ); +//********************END OF MMI2 OPCODES******************** +//***********************MMI3 OPCODES************************ + void PMADDUW( std::string& output ); + void PSRAVW( std::string& output ); + void PMTHI( std::string& output ); + void PMTLO( std::string& output ); + void PINTEH( std::string& output ); + void PMULTUW( std::string& output ); + void PDIVUW( std::string& output ); + void PCPYUD( std::string& output ); + void POR( std::string& output ); + void PNOR( std::string& output ); + void PEXCH( std::string& output ); + void PCPYH( std::string& output ); + void PEXCW( std::string& output ); +//*********************END OF MMI3 OPCODES******************* +//************************COP0 OPCODES*********************** + void MFC0( std::string& output ); + void MTC0( std::string& output ); + void BC0F( std::string& output ); + void BC0T( std::string& output ); + void BC0FL( std::string& output ); + void BC0TL( std::string& output ); + void TLBR( std::string& output ); + void TLBWI( std::string& output ); + void TLBWR( std::string& output ); + void TLBP( std::string& output ); + void ERET( std::string& output ); + void DI( std::string& output ); + void EI( std::string& output ); +//***********************END OF COP0************************* +//**************COP1 - Floating Point Unit (FPU)************* + void MFC1( std::string& output ); + void CFC1( std::string& output ); + void MTC1( std::string& output ); + void CTC1( std::string& output ); + void BC1F( std::string& output ); + void BC1T( std::string& output ); + void BC1FL( std::string& output ); + void BC1TL( std::string& output ); + void ADD_S( std::string& output ); + void SUB_S( std::string& output ); + void MUL_S( std::string& output ); + void DIV_S( std::string& output ); + void SQRT_S( std::string& output ); + void ABS_S( std::string& output ); + void MOV_S( std::string& output ); + void NEG_S( std::string& output ); + void RSQRT_S( std::string& output ); + void ADDA_S( std::string& output ); + void SUBA_S( std::string& output ); + void MULA_S( std::string& output ); + void MADD_S( std::string& output ); + void MSUB_S( std::string& output ); + void MADDA_S( std::string& output ); + void MSUBA_S( std::string& output ); + void CVT_W( std::string& output ); + void MAX_S( std::string& output ); + void MIN_S( std::string& output ); + void C_F( std::string& output ); + void C_EQ( std::string& output ); + void C_LT( std::string& output ); + void C_LE( std::string& output ); + void CVT_S( std::string& output ); +//**********************END OF COP1*********************** } +} - namespace Interpreter +namespace R5900 +{ + namespace Interpreter { + namespace OpcodeImpl { - namespace OpcodeImpl - { - void COP0(); - void COP1(); - void COP2(); + using namespace ::R5900; - void Unknown(); - void MMI_Unknown(); + void COP2(); + + void Unknown(); + void MMI_Unknown(); + void COP0_Unknown(); + void COP1_Unknown(); // **********************Standard Opcodes************************** - void J(); - void JAL(); - void BEQ(); - void BNE(); - void BLEZ(); - void BGTZ(); - void ADDI(); - void ADDIU(); - void SLTI(); - void SLTIU(); - void ANDI(); - void ORI(); - void XORI(); - void LUI(); - void BEQL(); - void BNEL(); - void BLEZL(); - void BGTZL(); - void DADDI(); - void DADDIU(); - void LDL(); - void LDR(); - void LB(); - void LH(); - void LWL(); - void LW(); - void LBU(); - void LHU(); - void LWR(); - void LWU(); - void SB(); - void SH(); - void SWL(); - void SW(); - void SDL(); - void SDR(); - void SWR(); - void CACHE(); - void LWC1(); - void PREF(); - void LQC2(); - void LD(); - void SQC2(); - void SD(); - void LQ(); - void SQ(); - void SWC1(); -//***************end of standard opcodes************************* - - -//***************SPECIAL OPCODES********************************** - void SLL(); - void SRL(); - void SRA(); - void SLLV(); - void SRLV(); - void SRAV(); - void JR(); - void JALR(); - void SYSCALL(); - void BREAK(); - void SYNC(); - void MFHI(); - void MTHI(); - void MFLO(); - void MTLO(); - void DSLLV(); - void DSRLV(); - void DSRAV(); - void MULT(); - void MULTU(); - void DIV(); - void DIVU(); - void ADD(); - void ADDU(); - void SUB(); - void SUBU(); - void AND(); - void OR(); - void XOR(); - void NOR(); - void SLT(); - void SLTU(); - void DADD(); - void DADDU(); - void DSUB(); - void DSUBU(); - void TGE(); - void TGEU(); - void TLT(); - void TLTU(); - void TEQ(); - void TNE(); - void DSLL(); - void DSRL(); - void DSRA(); - void DSLL32(); - void DSRL32(); - void DSRA32(); - void MOVZ(); - void MOVN(); - void MFSA(); - void MTSA(); -//******************END OF SPECIAL OPCODES************************** - -//******************REGIMM OPCODES********************************** - void BLTZ(); - void BGEZ(); - void BLTZL(); - void BGEZL(); - void TGEI(); - void TGEIU(); - void TLTI(); - void TLTIU(); - void TEQI(); - void TNEI(); - void BLTZAL(); - void BGEZAL(); - void BLTZALL(); - void BGEZALL(); - void MTSAB(); - void MTSAH(); -//*****************END OF REGIMM OPCODES***************************** - -//*****************MMI OPCODES********************************* - void MADD(); - void MADDU(); - void PLZCW(); - void MADD1(); - void MADDU1(); - void MFHI1(); - void MTHI1(); - void MFLO1(); - void MTLO1(); - void MULT1(); - void MULTU1(); - void DIV1(); - void DIVU1(); - void PMFHL(); - void PMTHL(); - void PSLLH(); - void PSRLH(); - void PSRAH(); - void PSLLW(); - void PSRLW(); - void PSRAW(); -//*****************END OF MMI OPCODES************************** - -//*************************MMI0 OPCODES************************ - void PADDW(); - void PSUBW(); - void PCGTW(); - void PMAXW(); - void PADDH(); - void PSUBH(); - void PCGTH(); - void PMAXH(); - void PADDB(); - void PSUBB(); - void PCGTB(); - void PADDSW(); - void PSUBSW(); - void PEXTLW(); - void PPACW(); - void PADDSH(); - void PSUBSH(); - void PEXTLH(); - void PPACH(); - void PADDSB(); - void PSUBSB(); - void PEXTLB(); - void PPACB(); - void PEXT5(); - void PPAC5(); -//***END OF MMI0 OPCODES****************************************** - -//**********MMI1 OPCODES************************************** - void PABSW(); - void PCEQW(); - void PMINW(); - void PADSBH(); - void PABSH(); - void PCEQH(); - void PMINH(); - void PCEQB(); - void PADDUW(); - void PSUBUW(); - void PEXTUW(); - void PADDUH(); - void PSUBUH(); - void PEXTUH(); - void PADDUB(); - void PSUBUB(); - void PEXTUB(); - void QFSRV(); -//********END OF MMI1 OPCODES*********************************** - -//*********MMI2 OPCODES*************************************** - void PMADDW(); - void PSLLVW(); - void PSRLVW(); - void PMSUBW(); - void PMFHI(); - void PMFLO(); - void PINTH(); - void PMULTW(); - void PDIVW(); - void PCPYLD(); - void PMADDH(); - void PHMADH(); - void PAND(); - void PXOR(); - void PMSUBH(); - void PHMSBH(); - void PEXEH(); - void PREVH(); - void PMULTH(); - void PDIVBW(); - void PEXEW(); - void PROT3W(); -//*****END OF MMI2 OPCODES*********************************** - -//*************************MMI3 OPCODES************************ - void PMADDUW(); - void PSRAVW(); - void PMTHI(); - void PMTLO(); - void PINTEH(); - void PMULTUW(); - void PDIVUW(); - void PCPYUD(); - void POR(); - void PNOR(); - void PEXCH(); - void PCPYH(); - void PEXCW(); + void J(); + void JAL(); + void BEQ(); + void BNE(); + void BLEZ(); + void BGTZ(); + void ADDI(); + void ADDIU(); + void SLTI(); + void SLTIU(); + void ANDI(); + void ORI(); + void XORI(); + void LUI(); + void BEQL(); + void BNEL(); + void BLEZL(); + void BGTZL(); + void DADDI(); + void DADDIU(); + void LDL(); + void LDR(); + void LB(); + void LH(); + void LWL(); + void LW(); + void LBU(); + void LHU(); + void LWR(); + void LWU(); + void SB(); + void SH(); + void SWL(); + void SW(); + void SDL(); + void SDR(); + void SWR(); + void CACHE(); + void LWC1(); + void PREF(); + void LQC2(); + void LD(); + void SQC2(); + void SD(); + void LQ(); + void SQ(); + void SWC1(); +//*****************end of standard opcodes********************** +//********************SPECIAL OPCODES*************************** + void SLL(); + void SRL(); + void SRA(); + void SLLV(); + void SRLV(); + void SRAV(); + void JR(); + void JALR(); + void SYSCALL(); + void BREAK(); + void SYNC(); + void MFHI(); + void MTHI(); + void MFLO(); + void MTLO(); + void DSLLV(); + void DSRLV(); + void DSRAV(); + void MULT(); + void MULTU(); + void DIV(); + void DIVU(); + void ADD(); + void ADDU(); + void SUB(); + void SUBU(); + void AND(); + void OR(); + void XOR(); + void NOR(); + void SLT(); + void SLTU(); + void DADD(); + void DADDU(); + void DSUB(); + void DSUBU(); + void TGE(); + void TGEU(); + void TLT(); + void TLTU(); + void TEQ(); + void TNE(); + void DSLL(); + void DSRL(); + void DSRA(); + void DSLL32(); + void DSRL32(); + void DSRA32(); + void MOVZ(); + void MOVN(); + void MFSA(); + void MTSA(); +//*******************END OF SPECIAL OPCODES************************ +//***********************REGIMM OPCODES**************************** + void BLTZ(); + void BGEZ(); + void BLTZL(); + void BGEZL(); + void TGEI(); + void TGEIU(); + void TLTI(); + void TLTIU(); + void TEQI(); + void TNEI(); + void BLTZAL(); + void BGEZAL(); + void BLTZALL(); + void BGEZALL(); + void MTSAB(); + void MTSAH(); +//*******************END OF REGIMM OPCODES*********************** +//***********************MMI OPCODES***************************** + void MADD(); + void MADDU(); + void PLZCW(); + void MADD1(); + void MADDU1(); + void MFHI1(); + void MTHI1(); + void MFLO1(); + void MTLO1(); + void MULT1(); + void MULTU1(); + void DIV1(); + void DIVU1(); + void PMFHL(); + void PMTHL(); + void PSLLH(); + void PSRLH(); + void PSRAH(); + void PSLLW(); + void PSRLW(); + void PSRAW(); +//********************END OF MMI OPCODES*********************** +//***********************MMI0 OPCODES************************** + void PADDW(); + void PSUBW(); + void PCGTW(); + void PMAXW(); + void PADDH(); + void PSUBH(); + void PCGTH(); + void PMAXH(); + void PADDB(); + void PSUBB(); + void PCGTB(); + void PADDSW(); + void PSUBSW(); + void PEXTLW(); + void PPACW(); + void PADDSH(); + void PSUBSH(); + void PEXTLH(); + void PPACH(); + void PADDSB(); + void PSUBSB(); + void PEXTLB(); + void PPACB(); + void PEXT5(); + void PPAC5(); +//******************END OF MMI0 OPCODES*********************** +//*********************MMI1 OPCODES*************************** + void PABSW(); + void PCEQW(); + void PMINW(); + void PADSBH(); + void PABSH(); + void PCEQH(); + void PMINH(); + void PCEQB(); + void PADDUW(); + void PSUBUW(); + void PEXTUW(); + void PADDUH(); + void PSUBUH(); + void PEXTUH(); + void PADDUB(); + void PSUBUB(); + void PEXTUB(); + void QFSRV(); +//*****************END OF MMI1 OPCODES*********************** +//*********************MMI2 OPCODES************************** + void PMADDW(); + void PSLLVW(); + void PSRLVW(); + void PMSUBW(); + void PMFHI(); + void PMFLO(); + void PINTH(); + void PMULTW(); + void PDIVW(); + void PCPYLD(); + void PMADDH(); + void PHMADH(); + void PAND(); + void PXOR(); + void PMSUBH(); + void PHMSBH(); + void PEXEH(); + void PREVH(); + void PMULTH(); + void PDIVBW(); + void PEXEW(); + void PROT3W(); +//********************END OF MMI2 OPCODES******************** +//***********************MMI3 OPCODES************************ + void PMADDUW(); + void PSRAVW(); + void PMTHI(); + void PMTLO(); + void PINTEH(); + void PMULTUW(); + void PDIVUW(); + void PCPYUD(); + void POR(); + void PNOR(); + void PEXCH(); + void PCPYH(); + void PEXCW(); //**********************END OF MMI3 OPCODES******************** - } - } // end namespace Interpreter -} // End namespace EE +//*************************COP0 OPCODES************************ + void MFC0(); + void MTC0(); + void BC0F(); + void BC0T(); + void BC0FL(); + void BC0TL(); + void TLBR(); + void TLBWI(); + void TLBWR(); + void TLBP(); + void ERET(); + void DI(); + void EI(); +//********************END OF COP0 OPCODES************************ +//************COP1 OPCODES - Floating Point Unit***************** + void MFC1(); + void CFC1(); + void MTC1(); + void CTC1(); + void BC1F(); + void BC1T(); + void BC1FL(); + void BC1TL(); + void ADD_S(); + void SUB_S(); + void MUL_S(); + void DIV_S(); + void SQRT_S(); + void ABS_S(); + void MOV_S(); + void NEG_S(); + void RSQRT_S(); + void ADDA_S(); + void SUBA_S(); + void MULA_S(); + void MADD_S(); + void MSUB_S(); + void MADDA_S(); + void MSUBA_S(); + void CVT_W(); + void MAX_S(); + void MIN_S(); + void C_F(); + void C_EQ(); + void C_LT(); + void C_LE(); + void CVT_S(); + } } // end namespace R5900::Interpreter::OpcodeImpl::R5900 +} // End namespace Interpreter -//**************************************************************************** -//** COP0 ** -//**************************************************************************** -void MFC0(); -void MTC0(); -void BC0F(); -void BC0T(); -void BC0FL(); -void BC0TL(); -void TLBR(); -void TLBWI(); -void TLBWR(); -void TLBP(); -void ERET(); -void DI(); -void EI(); -//**************************************************************************** -//** END OF COP0 ** -//**************************************************************************** -//**************************************************************************** -//** COP1 - Floating Point Unit (FPU) ** -//**************************************************************************** -void MFC1(); -void CFC1(); -void MTC1(); -void CTC1(); -void BC1F(); -void BC1T(); -void BC1FL(); -void BC1TL(); -void ADD_S(); -void SUB_S(); -void MUL_S(); -void DIV_S(); -void SQRT_S(); -void ABS_S(); -void MOV_S(); -void NEG_S(); -void RSQRT_S(); -void ADDA_S(); -void SUBA_S(); -void MULA_S(); -void MADD_S(); -void MSUB_S(); -void MADDA_S(); -void MSUBA_S(); -void CVT_W(); -void MAX_S(); -void MIN_S(); -void C_F(); -void C_EQ(); -void C_LT(); -void C_LE(); - void CVT_S(); -//**************************************************************************** -//** END OF COP1 ** -//**************************************************************************** //**************************************************************************** //** COP2 - (VU0) ** //**************************************************************************** @@ -863,5 +872,5 @@ void VRNEXT(); void VRGET(); void VRINIT(); void VRXOR(); -//************************************END OF SPECIAL2 ************ +//*******************END OF SPECIAL2 ********************* #endif diff --git a/pcsx2/Interpreter.cpp b/pcsx2/Interpreter.cpp index 717f380cda..35eaaef994 100644 --- a/pcsx2/Interpreter.cpp +++ b/pcsx2/Interpreter.cpp @@ -26,55 +26,75 @@ #include -const char *bios[256]={ -//0x00 - "RFU000_FullReset", "ResetEE", "SetGsCrt", "RFU003", - "Exit", "RFU005", "LoadExecPS2", "ExecPS2", - "RFU008", "RFU009", "AddSbusIntcHandler", "RemoveSbusIntcHandler", - "Interrupt2Iop", "SetVTLBRefillHandler", "SetVCommonHandler", "SetVInterruptHandler", -//0x10 - "AddIntcHandler", "RemoveIntcHandler", "AddDmacHandler", "RemoveDmacHandler", - "_EnableIntc", "_DisableIntc", "_EnableDmac", "_DisableDmac", - "_SetAlarm", "_ReleaseAlarm", "_iEnableIntc", "_iDisableIntc", - "_iEnableDmac", "_iDisableDmac", "_iSetAlarm", "_iReleaseAlarm", -//0x20 - "CreateThread", "DeleteThread", "StartThread", "ExitThread", - "ExitDeleteThread", "TerminateThread", "iTerminateThread", "DisableDispatchThread", - "EnableDispatchThread", "ChangeThreadPriority", "iChangeThreadPriority", "RotateThreadReadyQueue", - "iRotateThreadReadyQueue", "ReleaseWaitThread", "iReleaseWaitThread", "GetThreadId", -//0x30 - "ReferThreadStatus","iReferThreadStatus", "SleepThread", "WakeupThread", - "_iWakeupThread", "CancelWakeupThread", "iCancelWakeupThread", "SuspendThread", - "iSuspendThread", "ResumeThread", "iResumeThread", "JoinThread", - "RFU060", "RFU061", "EndOfHeap", "RFU063", -//0x40 - "CreateSema", "DeleteSema", "SignalSema", "iSignalSema", - "WaitSema", "PollSema", "iPollSema", "ReferSemaStatus", - "iReferSemaStatus", "RFU073", "SetOsdConfigParam", "GetOsdConfigParam", - "GetGsHParam", "GetGsVParam", "SetGsHParam", "SetGsVParam", -//0x50 - "RFU080_CreateEventFlag", "RFU081_DeleteEventFlag", - "RFU082_SetEventFlag", "RFU083_iSetEventFlag", - "RFU084_ClearEventFlag", "RFU085_iClearEventFlag", - "RFU086_WaitEventFlag", "RFU087_PollEventFlag", - "RFU088_iPollEventFlag", "RFU089_ReferEventFlagStatus", - "RFU090_iReferEventFlagStatus", "RFU091_GetEntryAddress", - "EnableIntcHandler_iEnableIntcHandler", - "DisableIntcHandler_iDisableIntcHandler", - "EnableDmacHandler_iEnableDmacHandler", - "DisableDmacHandler_iDisableDmacHandler", -//0x60 - "KSeg0", "EnableCache", "DisableCache", "GetCop0", - "FlushCache", "RFU101", "CpuConfig", "iGetCop0", - "iFlushCache", "RFU105", "iCpuConfig", "sceSifStopDma", - "SetCPUTimerHandler", "SetCPUTimer", "SetOsdConfigParam2", "SetOsdConfigParam2", -//0x70 - "GsGetIMR_iGsGetIMR", "GsGetIMR_iGsPutIMR", "SetPgifHandler", "SetVSyncFlag", - "RFU116", "print", "sceSifDmaStat_isceSifDmaStat", "sceSifSetDma_isceSifSetDma", - "sceSifSetDChain_isceSifSetDChain", "sceSifSetReg", "sceSifGetReg", "ExecOSD", - "Deci2Call", "PSMode", "MachineType", "GetMemorySize", -}; +extern void iDumpVU0Registers(); +extern void iDumpVU1Registers(); +extern u32 vudump; +extern int vu0branch, vu1branch; +namespace R5900 +{ + const char * const bios[256]= + { + //0x00 + "RFU000_FullReset", "ResetEE", "SetGsCrt", "RFU003", + "Exit", "RFU005", "LoadExecPS2", "ExecPS2", + "RFU008", "RFU009", "AddSbusIntcHandler", "RemoveSbusIntcHandler", + "Interrupt2Iop", "SetVTLBRefillHandler", "SetVCommonHandler", "SetVInterruptHandler", + //0x10 + "AddIntcHandler", "RemoveIntcHandler", "AddDmacHandler", "RemoveDmacHandler", + "_EnableIntc", "_DisableIntc", "_EnableDmac", "_DisableDmac", + "_SetAlarm", "_ReleaseAlarm", "_iEnableIntc", "_iDisableIntc", + "_iEnableDmac", "_iDisableDmac", "_iSetAlarm", "_iReleaseAlarm", + //0x20 + "CreateThread", "DeleteThread", "StartThread", "ExitThread", + "ExitDeleteThread", "TerminateThread", "iTerminateThread", "DisableDispatchThread", + "EnableDispatchThread", "ChangeThreadPriority", "iChangeThreadPriority", "RotateThreadReadyQueue", + "iRotateThreadReadyQueue", "ReleaseWaitThread", "iReleaseWaitThread", "GetThreadId", + //0x30 + "ReferThreadStatus","iReferThreadStatus", "SleepThread", "WakeupThread", + "_iWakeupThread", "CancelWakeupThread", "iCancelWakeupThread", "SuspendThread", + "iSuspendThread", "ResumeThread", "iResumeThread", "JoinThread", + "RFU060", "RFU061", "EndOfHeap", "RFU063", + //0x40 + "CreateSema", "DeleteSema", "SignalSema", "iSignalSema", + "WaitSema", "PollSema", "iPollSema", "ReferSemaStatus", + "iReferSemaStatus", "RFU073", "SetOsdConfigParam", "GetOsdConfigParam", + "GetGsHParam", "GetGsVParam", "SetGsHParam", "SetGsVParam", + //0x50 + "RFU080_CreateEventFlag", "RFU081_DeleteEventFlag", + "RFU082_SetEventFlag", "RFU083_iSetEventFlag", + "RFU084_ClearEventFlag", "RFU085_iClearEventFlag", + "RFU086_WaitEventFlag", "RFU087_PollEventFlag", + "RFU088_iPollEventFlag", "RFU089_ReferEventFlagStatus", + "RFU090_iReferEventFlagStatus", "RFU091_GetEntryAddress", + "EnableIntcHandler_iEnableIntcHandler", + "DisableIntcHandler_iDisableIntcHandler", + "EnableDmacHandler_iEnableDmacHandler", + "DisableDmacHandler_iDisableDmacHandler", + //0x60 + "KSeg0", "EnableCache", "DisableCache", "GetCop0", + "FlushCache", "RFU101", "CpuConfig", "iGetCop0", + "iFlushCache", "RFU105", "iCpuConfig", "sceSifStopDma", + "SetCPUTimerHandler", "SetCPUTimer", "SetOsdConfigParam2", "SetOsdConfigParam2", + //0x70 + "GsGetIMR_iGsGetIMR", "GsGetIMR_iGsPutIMR", "SetPgifHandler", "SetVSyncFlag", + "RFU116", "print", "sceSifDmaStat_isceSifDmaStat", "sceSifSetDma_isceSifSetDma", + "sceSifSetDChain_isceSifSetDChain", "sceSifSetReg", "sceSifGetReg", "ExecOSD", + "Deci2Call", "PSMode", "MachineType", "GetMemorySize", + }; + + const OPCODE& GetCurrentInstruction() + { + const OPCODE* opcode = &R5900::OpcodeTables::tbl_Standard[_Opcode_]; + + while( opcode->getsubclass != NULL ) + opcode = &opcode->getsubclass(); + + return *opcode; + } + +namespace Interpreter +{ int branch2 = 0; static u32 branchPC; @@ -83,8 +103,8 @@ static u32 branchPC; #ifdef PCSX2_DEVBUILD static void debugI() { - //CPU_LOG("%s\n", disR5900Current.getString()); - if (cpuRegs.GPR.n.r0.UD[0] || cpuRegs.GPR.n.r0.UD[1]) SysPrintf("R0 is not zero!!!!\n"); + //CPU_LOG("%s\n", disR5900Current.getCString()); + if (cpuRegs.GPR.n.r0.UD[0] || cpuRegs.GPR.n.r0.UD[1]) Console::Error("R0 is not zero!!!!"); } #else static void debugI() {} @@ -92,19 +112,6 @@ static void debugI() {} static u32 cpuBlockCycles = 0; // 3 bit fixed point version of cycle count -namespace EE -{ - const OPCODE& GetCurrentInstruction() - { - const EE::OPCODE* opcode = &EE::OpcodeTables::Standard[_Opcode_]; - - while( opcode->getsubclass != NULL ) - opcode = &opcode->getsubclass(); - - return *opcode; - } -} - static std::string disOut; static __forceinline void execI() @@ -116,14 +123,9 @@ static __forceinline void execI() cpuRegs.code = *(u32 *)PSM(cpuRegs.pc); #endif - const EE::OPCODE& opcode = EE::GetCurrentInstruction(); - - /*disOut.assign( "\n" ); - opcode.decode( disOut ); - SysPrintf( disOut.c_str() );*/ + const OPCODE& opcode = GetCurrentInstruction(); cpuBlockCycles += opcode.cycles; - //cpuRegs.cycle++; cpuRegs.pc += 4; opcode.interpret(); @@ -150,58 +152,16 @@ void intSetBranch() { branch2 = 1; } -//**************************************************************** -// Used to manage FPU Opcodes -//**************************************************************** - -void COP1_BC1() { - Int_COP1BC1PrintTable[_Rt_](); -} - -void COP1_S() { - Int_COP1SPrintTable[_Funct_](); -} - -void COP1_W() { - Int_COP1WPrintTable[_Funct_](); -} - void COP1_Unknown() { FPU_LOG("Unknown FPU opcode called\n"); } - -namespace EE { namespace Opcodes -{ - -const OPCODE& Class_SPECIAL() { return EE::OpcodeTables::Special[_Funct_]; } -const OPCODE& Class_REGIMM() { return EE::OpcodeTables::RegImm[_Rt_]; } - -const OPCODE& Class_MMI() { return EE::OpcodeTables::MMI[_Funct_]; } -const OPCODE& Class_MMI0() { return EE::OpcodeTables::MMI0[_Sa_]; } -const OPCODE& Class_MMI1() { return EE::OpcodeTables::MMI1[_Sa_]; } -const OPCODE& Class_MMI2() { return EE::OpcodeTables::MMI2[_Sa_]; } -const OPCODE& Class_MMI3() { return EE::OpcodeTables::MMI3[_Sa_]; } - -//const OPCODE& Class_COP0() { return EE::OpcodeTables::COP1[_Rs_]; } -//const OPCODE& Class_COP1() { return EE::OpcodeTables::COP1[_Rs_]; } -//const OPCODE& Class_COP2() { return EE::OpcodeTables::COP2[_Rs_]; } - -} } - -namespace EE { namespace Interpreter { namespace OpcodeImpl -{ -void COP0() -{ - Int_COP0PrintTable[_Rs_](); +void COP0_Unknown(){ + CPU_LOG("COP0 Unknown opcode called\n"); } -void COP1() +namespace OpcodeImpl { - FPU_LOG("%s\n", disR5900Current.getString() ); - Int_COP1PrintTable[_Rs_](); -} - void COP2() { std::string disOut; @@ -215,6 +175,11 @@ void Unknown() { CPU_LOG("%8.8lx: Unknown opcode called\n", cpuRegs.pc); } +void MMI_Unknown() { Console::Notice("Unknown MMI opcode called"); } +void COP0_Unknown() { Console::Notice("Unknown COP0 opcode called"); } +void COP1_Unknown() { Console::Notice("Unknown FPU/COP1 opcode called"); } + + /********************************************************* * Arithmetic with immediate operand * * Format: OP rt, rs, immediate * @@ -1014,9 +979,9 @@ void MTSAH() { cpuRegs.sa = ((cpuRegs.GPR.r[_Rs_].UL[0] & 0x7) ^ (_Imm_ & 0x7)) << 4; } -} } } // end EE::Interpreter::OpcodeImpl namespace +} // end namespace R5900::Interpreter::OpcodeImpl -/////////////////////////////////////////// +//////////////////////////////////////////////////////// void intInit() { //detect cpu for use the optimaze asm code @@ -1036,12 +1001,6 @@ static void intExecuteBlock() { while (!branch2) execI(); } - -extern void iDumpVU0Registers(); -extern void iDumpVU1Registers(); -extern u32 vudump; -extern int vu0branch, vu1branch; - void intExecuteVU0Block() { int i; @@ -1124,6 +1083,10 @@ void intVU1Clear(u32 Addr, u32 Size) { void intShutdown() { } +} + +using namespace Interpreter; + R5900cpu intCpu = { intInit, intReset, @@ -1140,3 +1103,4 @@ R5900cpu intCpu = { intShutdown }; +} \ No newline at end of file diff --git a/pcsx2/MMI.cpp b/pcsx2/MMI.cpp index 44fdfec7a3..5342f01850 100644 --- a/pcsx2/MMI.cpp +++ b/pcsx2/MMI.cpp @@ -23,11 +23,11 @@ #include "R5900.h" #include "InterTables.h" -namespace EE { namespace Interpreter{ namespace OpcodeImpl +namespace R5900 { +namespace Interpreter { +namespace OpcodeImpl { -void MMI_Unknown() { Console::Notice("Unknown MMI opcode called"); } - //*****************MMI OPCODES********************************* void MADD() { @@ -1544,4 +1544,4 @@ void PEXCW() { // obs: // QFSRV not verified -}}} // end namespace EE::Interpreter::OpcodeImpl \ No newline at end of file +}}} // end namespace R5900::Interpreter::OpcodeImpl \ No newline at end of file diff --git a/pcsx2/MTGS.cpp b/pcsx2/MTGS.cpp index f55af22b7f..1923ecad39 100644 --- a/pcsx2/MTGS.cpp +++ b/pcsx2/MTGS.cpp @@ -51,7 +51,6 @@ using namespace std; #define volatize(x) (*(u8* volatile*)&(x)) // for writepos #define volatize_c(x) (*(u8 * volatile*)&(x)) // for readpos - ///////////////////////////////////////////////////////////////////////////// // BEGIN -- MTGS GIFtag Parse Implementation // @@ -209,9 +208,6 @@ mtgsThreadObject::mtgsThreadObject() : , m_lock_Stack() #endif { - memcpy_raz_( m_gsMem, PS2MEM_GS, sizeof(m_gsMem) ); - GSsetBaseMem( m_gsMem ); - // Wait for the thread to finish initialization (it runs GSinit, which can take // some time since it's creating a new window and all), and then check for errors. @@ -432,6 +428,10 @@ __forceinline u32 mtgsThreadObject::_gifTransferDummy( GIF_PATH pathidx, const u int mtgsThreadObject::Callback() { Console::WriteLn("MTGS > Thread Started, Opening GS Plugin..."); + + memcpy_raz_( m_gsMem, PS2MEM_GS, sizeof(m_gsMem) ); + GSsetBaseMem( m_gsMem ); + m_returncode = GSopen((void *)&pDsp, "PCSX2", 1); GSCSRr = 0x551B400F; // 0x55190000 m_wait_InitDone.Set(); diff --git a/pcsx2/Memory.cpp b/pcsx2/Memory.cpp index 2111db859a..8d08e71562 100644 --- a/pcsx2/Memory.cpp +++ b/pcsx2/Memory.cpp @@ -59,6 +59,9 @@ BIOS #include "GS.h" #include "vtlb.h" +using namespace Dynarec; +using namespace Dynarec::R5900; + #ifdef ENABLECACHE #include "Cache.h" #endif @@ -2721,13 +2724,13 @@ void loadBiosRom( const char *ext, u8 *dest, long maxSize ) Path::Combine( Bios, Config.BiosDir, Config.Bios ); - ssprintf(Bios1, "%S.%s", params &Bios, ext); + ssprintf(Bios1, "%hs.%s", params &Bios, ext); if( (filesize=Path::isFile( Bios1 ) ) <= 0 ) { Path::ReplaceExtension( Bios1, Bios, ext ); if( (filesize=Path::isFile( Bios1 ) ) <= 0 ) { - // And this check is... well I'm not sure whf this check is trying to accomplish! (air) + // And this check is... well I'm not sure wtf this check is trying to accomplish! (air) ssprintf( Bios1, "%s%s.bin", params Config.BiosDir, ext ); if( (filesize=Path::isFile( Bios1 ) ) <= 0 ) { diff --git a/pcsx2/Misc.cpp b/pcsx2/Misc.cpp index 508be96c84..03ec77c0c5 100644 --- a/pcsx2/Misc.cpp +++ b/pcsx2/Misc.cpp @@ -42,6 +42,8 @@ #include "Paths.h" using namespace std; +using namespace Dynarec; +using namespace R5900; PcsxConfig Config; u32 BiosVersion; @@ -376,8 +378,6 @@ int GetPS2ElfName(char *name){ return 2; } -extern u32 dumplog; - #ifdef PCSX2_DEVBUILD void SaveGSState(const string& file) @@ -494,7 +494,7 @@ char *ParseLang(char *id) { #define NUM_STATES 10 int StatesC = 0; -extern void iDumpRegisters(u32 startpc, u32 temp); + extern char strgametitle[256]; char* mystrlwr( char* string ) @@ -553,7 +553,7 @@ void ProcessFKeys(int fkey, int shift) { SaveState::GetFilename( Text, StatesC ); gzLoadingState joe( Text ); // throws exception on version mismatch - cpuReset(); + R5900::cpuReset(); joe.FreezeAll(); } catch( Exception::StateLoadError_Recoverable& ) @@ -576,7 +576,7 @@ void ProcessFKeys(int fkey, int shift) "Pcsx2 encountered an error while trying to load the savestate\n" "and emulation had to be aborted." ); - cpuShutdown(); + R5900::cpuShutdown(); ClosePlugins(); throw Exception::CpuStateShutdown( @@ -632,7 +632,8 @@ void ProcessFKeys(int fkey, int shift) // [Air]: Do we really want to save runtime changes to frameskipping? //SaveConfig(); } - break; + break; + // note: VK_F5-VK_F7 are reserved for GS case 8: GSmakeSnapshot("snap/"); @@ -699,8 +700,8 @@ void ProcessFKeys(int fkey, int shift) } else { if( GSsetupRecording != NULL ) GSsetupRecording(g_Pcsx2Recording, NULL); - if( SPU2setupRecording != NULL ) SPU2setupRecording(g_Pcsx2Recording, NULL); } + if( SPU2setupRecording != NULL ) SPU2setupRecording(g_Pcsx2Recording, NULL); } break; } diff --git a/pcsx2/Misc.h b/pcsx2/Misc.h index 400e84e16a..53ff4bfc8b 100644 --- a/pcsx2/Misc.h +++ b/pcsx2/Misc.h @@ -193,12 +193,20 @@ struct romdir{ u32 GetBiosVersion(); int IsBIOS(char *filename, char *description); -// check to see if needs freezing +extern u32 g_sseVUMXCSR, g_sseMXCSR; + +void SetCPUState(u32 sseMXCSR, u32 sseVUMXCSR); + +// when using mmx/xmm regs, use; 0 is load +// freezes no matter the state extern void FreezeXMMRegs_(int save); extern void FreezeMMXRegs_(int save); extern bool g_EEFreezeRegs; -#define FreezeXMMRegs(save) if( g_EEFreezeRegs ) { FreezeXMMRegs_(save); } +extern u8 g_globalMMXSaved; +extern u8 g_globalXMMSaved; +// these macros check to see if needs freezing +#define FreezeXMMRegs(save) if( g_EEFreezeRegs ) { FreezeXMMRegs_(save); } #define FreezeMMXRegs(save) if( g_EEFreezeRegs ) { FreezeMMXRegs_(save); } diff --git a/pcsx2/Patch.cpp b/pcsx2/Patch.cpp index 4023ff6003..7cf5a71062 100644 --- a/pcsx2/Patch.cpp +++ b/pcsx2/Patch.cpp @@ -567,14 +567,14 @@ void patchFunc_xkickdelay( char * cmd, char * param ) void patchFunc_fastmemory( char * cmd, char * param ) { // only valid for recompilers - EE::Dynarec::SetFastMemory(1); + Dynarec::SetFastMemory(1); } void patchFunc_vunanmode( char * cmd, char * param ) { // only valid for recompilers - SetVUNanMode(param != NULL ? atoi(param) : 1); + Dynarec::SetVUNanMode(param != NULL ? atoi(param) : 1); } void patchFunc_path3hack( char * cmd, char * param ) diff --git a/pcsx2/Patch.h b/pcsx2/Patch.h index ecdfb8edf8..b02a6f5911 100644 --- a/pcsx2/Patch.h +++ b/pcsx2/Patch.h @@ -117,13 +117,11 @@ void resetpatch( void ); int AddPatch(int Mode, int Place, int Address, int Size, u64 data); -namespace EE { namespace Dynarec { - void SetFastMemory(int); // iR5900LoadStore.c -} } - -void SetVUNanMemory(int); // iVUmicro.c - -extern void SetVUNanMode(int mode); +namespace Dynarec { + extern void SetFastMemory(int); // iR5900LoadStore.c + extern void SetVUNanMemory(int); // iVUmicro.c + extern void SetVUNanMode(int mode); +} extern int path3hack; extern int g_FFXHack; @@ -132,7 +130,6 @@ extern int g_ZeroGSOptions; extern u32 g_sseMXCSR; extern u32 g_sseVUMXCSR; -void SetCPUState(u32 sseMXCSR, u32 sseVUMXCSR); void SetRoundMode(u32 ee, u32 vu); int LoadPatch(const std::string& patchfile); diff --git a/pcsx2/Plugins.cpp b/pcsx2/Plugins.cpp index 021ca01db9..d6a2b09fa8 100644 --- a/pcsx2/Plugins.cpp +++ b/pcsx2/Plugins.cpp @@ -223,7 +223,7 @@ USBhandler usbHandler; #define MapSymbolVar_Error(var,name) if((MapSymbolVar(var,name))==NULL) \ { \ const char* errString = SysLibError(); \ - Msgbox::Alert("%s: Error loading %S: %s", params &filename, #name, errString); \ + Msgbox::Alert("%s: Error loading %hs: %s", params &filename, #name, errString); \ return -1; \ } @@ -251,7 +251,7 @@ int _TestPS2Esyms(void* drv, int type, int expected_version, const string& filen int actual_version = ((PS2EgetLibVersion2(type) >> 16)&0xff); if( actual_version != expected_version) { - Msgbox::Alert("Can't load '%S', wrong PS2E version (%x != %x)", params &filename, actual_version, expected_version); + Msgbox::Alert("Can't load '%hs', wrong PS2E version (%x != %x)", params &filename, actual_version, expected_version); return -1; } @@ -287,7 +287,7 @@ int LoadGSplugin(const string& filename) void *drv; GSplugin = SysLoadLibrary(filename.c_str()); - if (GSplugin == NULL) { Msgbox::Alert ("Could Not Load GS Plugin '%S': %s", params &filename, SysLibError()); return -1; } + if (GSplugin == NULL) { Msgbox::Alert ("Could Not Load GS Plugin '%hs': %s", params &filename, SysLibError()); return -1; } drv = GSplugin; TestPS2Esyms(GS); MapSymbol_Error(GSinit); @@ -339,7 +339,7 @@ int LoadPAD1plugin(const string& filename) { void *drv; PAD1plugin = SysLoadLibrary(filename.c_str()); - if (PAD1plugin == NULL) { Msgbox::Alert("Could Not Load PAD1 Plugin '%S': %s", params &filename, SysLibError()); return -1; } + if (PAD1plugin == NULL) { Msgbox::Alert("Could Not Load PAD1 Plugin '%hs': %s", params &filename, SysLibError()); return -1; } drv = PAD1plugin; TestPS2Esyms(PAD); MapSymbolPAD_Error(PAD1,PAD,init); @@ -370,7 +370,7 @@ int LoadPAD2plugin(const string& filename) { void *drv; PAD2plugin = SysLoadLibrary(filename.c_str()); - if (PAD2plugin == NULL) { Msgbox::Alert("Could Not Load PAD2 Plugin '%S': %s", params &filename, SysLibError()); return -1; } + if (PAD2plugin == NULL) { Msgbox::Alert("Could Not Load PAD2 Plugin '%hs': %s", params &filename, SysLibError()); return -1; } drv = PAD2plugin; TestPS2Esyms(PAD); MapSymbolPAD_Error(PAD2,PAD,init); @@ -402,7 +402,7 @@ int LoadSPU2plugin(const string& filename) { void *drv; SPU2plugin = SysLoadLibrary(filename.c_str()); - if (SPU2plugin == NULL) { Msgbox::Alert("Could Not Load SPU2 Plugin '%S': %s", params &filename, SysLibError()); return -1; } + if (SPU2plugin == NULL) { Msgbox::Alert("Could Not Load SPU2 Plugin '%hs': %s", params &filename, SysLibError()); return -1; } drv = SPU2plugin; TestPS2Esyms(SPU2); MapSymbol_Error(SPU2init); @@ -445,7 +445,7 @@ int LoadCDVDplugin(const string& filename) { void *drv; CDVDplugin = SysLoadLibrary(filename.c_str()); - if (CDVDplugin == NULL) { Msgbox::Alert("Could Not Load CDVD Plugin '%S': %s", params &filename, SysLibError()); return -1; } + if (CDVDplugin == NULL) { Msgbox::Alert("Could Not Load CDVD Plugin '%hs': %s", params &filename, SysLibError()); return -1; } drv = CDVDplugin; TestPS2Esyms(CDVD); MapSymbol_Error(CDVDinit); @@ -482,7 +482,7 @@ int LoadDEV9plugin(const string& filename) { void *drv; DEV9plugin = SysLoadLibrary(filename.c_str()); - if (DEV9plugin == NULL) { Msgbox::Alert("Could Not Load DEV9 Plugin '%S': %s", params &filename, SysLibError()); return -1; } + if (DEV9plugin == NULL) { Msgbox::Alert("Could Not Load DEV9 Plugin '%hs': %s", params &filename, SysLibError()); return -1; } drv = DEV9plugin; TestPS2Esyms(DEV9); MapSymbol_Error(DEV9init); @@ -519,7 +519,7 @@ int LoadUSBplugin(const string& filename) { void *drv; USBplugin = SysLoadLibrary(filename.c_str()); - if (USBplugin == NULL) { Msgbox::Alert("Could Not Load USB Plugin '%S': %s", params &filename, SysLibError()); return -1; } + if (USBplugin == NULL) { Msgbox::Alert("Could Not Load USB Plugin '%hs': %s", params &filename, SysLibError()); return -1; } drv = USBplugin; TestPS2Esyms(USB); MapSymbol_Error(USBinit); @@ -556,7 +556,7 @@ int LoadFWplugin(const string& filename) { void *drv; FWplugin = SysLoadLibrary(filename.c_str()); - if (FWplugin == NULL) { Msgbox::Alert("Could Not Load FW Plugin '%S': %s", params &filename, SysLibError()); return -1; } + if (FWplugin == NULL) { Msgbox::Alert("Could Not Load FW Plugin '%hs': %s", params &filename, SysLibError()); return -1; } drv = FWplugin; TestPS2Esyms(FW); MapSymbol_Error(FWinit); diff --git a/pcsx2/PsxHw.h b/pcsx2/PsxHw.h index 3f44e5a1c0..3f76ac0543 100644 --- a/pcsx2/PsxHw.h +++ b/pcsx2/PsxHw.h @@ -100,31 +100,31 @@ extern void psxSetNextBranchDelta( s32 delta ); void psxHwReset(); u8 psxHwRead8 (u32 add); -int psxHwConstRead8(u32 x86reg, u32 add, u32 sign); - u16 psxHwRead16(u32 add); -int psxHwConstRead16(u32 x86reg, u32 add, u32 sign); - u32 psxHwRead32(u32 add); -int psxHwConstRead32(u32 x86reg, u32 add); void psxHwWrite8 (u32 add, u8 value); -void psxHwConstWrite8(u32 add, int mmreg); - void psxHwWrite16(u32 add, u16 value); -void psxHwConstWrite16(u32 add, int mmreg); - void psxHwWrite32(u32 add, u32 value); -void psxHwConstWrite32(u32 add, int mmreg); u8 psxHw4Read8 (u32 add); -int psxHw4ConstRead8 (u32 x86reg, u32 add, u32 sign); - void psxHw4Write8(u32 add, u8 value); -void psxHw4ConstWrite8(u32 add, int mmreg); -int psxHwFreeze(gzFile f, int Mode); void psxDmaInterrupt(int n); void psxDmaInterrupt2(int n); +int psxHwFreeze(gzFile f, int Mode); + +namespace Dynarec +{ + int psxHwConstRead8(u32 x86reg, u32 add, u32 sign); + int psxHwConstRead16(u32 x86reg, u32 add, u32 sign); + int psxHwConstRead32(u32 x86reg, u32 add); + void psxHwConstWrite8(u32 add, int mmreg); + void psxHwConstWrite16(u32 add, int mmreg); + void psxHwConstWrite32(u32 add, int mmreg); + int psxHw4ConstRead8 (u32 x86reg, u32 add, u32 sign); + void psxHw4ConstWrite8(u32 add, int mmreg); +} + #endif /* __PSXHW_H__ */ diff --git a/pcsx2/PsxMem.cpp b/pcsx2/PsxMem.cpp index 2fa5aa135d..2fe2281dfa 100644 --- a/pcsx2/PsxMem.cpp +++ b/pcsx2/PsxMem.cpp @@ -24,7 +24,6 @@ #include "Hw.h" #include "iR3000A.h" -extern u32 g_psxMaxRecMem; int g_psxWriteOk=1; static u32 writectrl; diff --git a/pcsx2/PsxMem.h b/pcsx2/PsxMem.h index 84368f6b33..969b5e24b6 100644 --- a/pcsx2/PsxMem.h +++ b/pcsx2/PsxMem.h @@ -96,24 +96,26 @@ void psxMemWrite8 (u32 mem, u8 value); void psxMemWrite16(u32 mem, u16 value); void psxMemWrite32(u32 mem, u32 value); -// x86reg and mmreg are always x86 regs -void psxRecMemRead8(); -int psxRecMemConstRead8(u32 x86reg, u32 mem, u32 sign); +namespace Dynarec +{ + // x86reg and mmreg are always x86 regs + void psxRecMemRead8(); + int psxRecMemConstRead8(u32 x86reg, u32 mem, u32 sign); -void psxRecMemRead16(); -int psxRecMemConstRead16(u32 x86reg, u32 mem, u32 sign); + void psxRecMemRead16(); + int psxRecMemConstRead16(u32 x86reg, u32 mem, u32 sign); -void psxRecMemRead32(); -int psxRecMemConstRead32(u32 x86reg, u32 mem); + void psxRecMemRead32(); + int psxRecMemConstRead32(u32 x86reg, u32 mem); -void psxRecMemWrite8(); -int psxRecMemConstWrite8(u32 mem, int mmreg); + void psxRecMemWrite8(); + int psxRecMemConstWrite8(u32 mem, int mmreg); -void psxRecMemWrite16(); -int psxRecMemConstWrite16(u32 mem, int mmreg); - -void psxRecMemWrite32(); -int psxRecMemConstWrite32(u32 mem, int mmreg); + void psxRecMemWrite16(); + int psxRecMemConstWrite16(u32 mem, int mmreg); + void psxRecMemWrite32(); + int psxRecMemConstWrite32(u32 mem, int mmreg); +} #endif /* __PSXMEMORY_H__ */ diff --git a/pcsx2/R3000A.cpp b/pcsx2/R3000A.cpp index a4fdf7cc80..ecd728bec1 100644 --- a/pcsx2/R3000A.cpp +++ b/pcsx2/R3000A.cpp @@ -201,7 +201,7 @@ __forceinline void PSX_INT( IopEventId n, s32 ecycle ) // fixme - this doesn't take into account EE/IOP sync (the IOP may be running // ahead or behind the EE as per the EEsCycles value) s32 iopDelta = (g_psxNextBranchCycle-psxRegs.cycle)*8; - cpuSetNextBranchDelta( iopDelta ); + R5900::cpuSetNextBranchDelta( iopDelta ); } } @@ -276,12 +276,12 @@ void iopTestIntc() if( psxHu32(0x1078) == 0 ) return; if( (psxHu32(0x1070) & psxHu32(0x1074)) == 0 ) return; - if( !eeEventTestIsActive ) + if( !R5900::EventTestIsActive ) { // An iop exception has occured while the EE is running code. // Inform the EE to branch so the IOP can handle it promptly: - cpuSetNextBranchDelta( 16 ); + R5900::cpuSetNextBranchDelta( 16 ); iopBranchAction = true; //Console::Error( "** IOP Needs an EE EventText, kthx ** %d", params psxCycleEE ); diff --git a/pcsx2/R5900.cpp b/pcsx2/R5900.cpp index 11ced7e831..ea1239aa51 100644 --- a/pcsx2/R5900.cpp +++ b/pcsx2/R5900.cpp @@ -28,6 +28,16 @@ #include "Paths.h" +#ifdef _DEBUG +extern u32 s_vucount; +#endif + +namespace R5900 +{ + +s32 EEsCycle; // used to sync the IOP to the EE +u32 EEoCycle; + static int inter; PCSX2_ALIGNED16(cpuRegisters cpuRegs); @@ -38,18 +48,12 @@ PCSX2_ALIGNED16(GPR_reg64 g_cpuConstRegs[32]) = {0}; u32 g_cpuHasConstReg = 0, g_cpuFlushedConstReg = 0; R5900cpu *Cpu; -s32 EEsCycle; // used to sync the IOP to the EE -u32 EEoCycle; u32 bExecBIOS = 0; // set if the BIOS has already been executed static bool cpuIsInitialized = false; static uint eeWaitCycles = 1024; -bool eeEventTestIsActive = false; - -#ifdef _DEBUG -extern u32 s_vucount; -#endif +bool EventTestIsActive = false; bool cpuInit() { @@ -100,7 +104,7 @@ bool cpuInit() if( !CreateProcess(strexe.c_str(), "", NULL, NULL, FALSE, DETACHED_PROCESS|CREATE_NEW_PROCESS_GROUP, NULL, strdir.GetPtr(), &si, &pi)) { - MessageBox(NULL, fmt_string( "Failed to launch %S\n", params &strexe ).c_str(), "Failure", MB_OK); + MessageBox(NULL, fmt_string( "Failed to launch %hs\n", params &strexe ).c_str(), "Failure", MB_OK); } else { @@ -400,12 +404,21 @@ __forceinline void cpuSetBranch() g_nextBranchCycle = cpuRegs.cycle; } +void cpuClearInt( uint i ) +{ + jASSUME( i < 32 ); + cpuRegs.interrupt &= ~(1 << i); +} + static __forceinline void TESTINT( u8 n, void (*callback)() ) { if( !(cpuRegs.interrupt & (1 << n)) ) return; if( cpuTestCycle( cpuRegs.sCycle[n], cpuRegs.eCycle[n] ) ) + { + cpuClearInt( n ); callback(); + } else cpuSetNextBranch( cpuRegs.sCycle[n], cpuRegs.eCycle[n] ); } @@ -439,9 +452,6 @@ static __forceinline void _cpuTestInterrupts() } } -u32 s_iLastCOP0Cycle = 0; -u32 s_iLastPERFCycle[2] = {0,0}; - static __forceinline void _cpuTestTIMR() { cpuRegs.CP0.n.Count += cpuRegs.cycle-s_iLastCOP0Cycle; @@ -495,7 +505,7 @@ u32 g_nextBranchCycle = 0; // and the recompiler. (moved here to help alleviate redundant code) static __forceinline void _cpuBranchTest_Shared() { - eeEventTestIsActive = true; + EventTestIsActive = true; g_nextBranchCycle = cpuRegs.cycle + eeWaitCycles; EEsCycle += cpuRegs.cycle - EEoCycle; @@ -609,7 +619,7 @@ static __forceinline void _cpuBranchTest_Shared() // Apply vsync and other counter nextCycles cpuSetNextBranch( nextsCounter, nextCounter ); - eeEventTestIsActive = false; + EventTestIsActive = false; // ---- INTC / DMAC Exceptions ----------------- // Raise the INTC and DMAC interrupts here, which usually throw exceptions. @@ -624,11 +634,6 @@ static __forceinline void _cpuBranchTest_Shared() } } -#ifdef PCSX2_DEVBUILD -extern u8 g_globalXMMSaved; -extern u8 g_globalMMXSaved; -#endif - void cpuBranchTest() { // cpuBranchTest should be called from the recompiler only. @@ -654,26 +659,6 @@ void cpuBranchTest() g_EEFreezeRegs = true; } -__forceinline void CPU_INT( u32 n, s32 ecycle) -{ - cpuRegs.interrupt|= 1 << n; - cpuRegs.sCycle[n] = cpuRegs.cycle; - cpuRegs.eCycle[n] = ecycle; - - // Interrupt is happening soon: make sure both EE and IOP are aware. - - if( ecycle <= 28 && psxCycleEE > 0 ) - { - // If running in the IOP, force it to break immediately into the EE. - // the EE's branch test is due to run. - - psxBreak += psxCycleEE; // record the number of cycles the IOP didn't run. - psxCycleEE = 0; - } - - cpuSetNextBranchDelta( cpuRegs.eCycle[n] ); -} - void cpuTestINTCInts() { if( cpuRegs.interrupt & (1 << 30) ) return; @@ -687,7 +672,7 @@ void cpuTestINTCInts() // only set the next branch delta if the exception won't be handled for // the current branch... - if( !eeEventTestIsActive ) + if( !EventTestIsActive ) cpuSetNextBranchDelta( 4 ); else if(psxCycleEE > 0) { @@ -710,7 +695,7 @@ __forceinline void cpuTestDMACInts() // only set the next branch delta if the exception won't be handled for // the current branch... - if( !eeEventTestIsActive ) + if( !EventTestIsActive ) cpuSetNextBranchDelta( 4 ); else if(psxCycleEE > 0) { @@ -780,15 +765,27 @@ void IntcpuBranchTest() // Perform counters, ints, and IOP updates: _cpuBranchTest_Shared(); - if (VU0.VI[REG_VPU_STAT].UL & 0x1) { - Cpu->ExecuteVU0Block(); - - // This might be needed to keep the EE and VU0 in sync. - // A better fix will require hefty changes to the VU recs. -_- - if(VU0.VI[REG_VPU_STAT].UL & 0x1) - cpuSetNextBranchDelta( 768 ); - - } - g_EEFreezeRegs = true; } + +__forceinline void CPU_INT( u32 n, s32 ecycle) +{ + cpuRegs.interrupt|= 1 << n; + cpuRegs.sCycle[n] = cpuRegs.cycle; + cpuRegs.eCycle[n] = ecycle; + + // Interrupt is happening soon: make sure both EE and IOP are aware. + + if( ecycle <= 28 && psxCycleEE > 0 ) + { + // If running in the IOP, force it to break immediately into the EE. + // the EE's branch test is due to run. + + psxBreak += psxCycleEE; // record the number of cycles the IOP didn't run. + psxCycleEE = 0; + } + + cpuSetNextBranchDelta( cpuRegs.eCycle[n] ); +} + +} // end namespace R5900 \ No newline at end of file diff --git a/pcsx2/R5900.h b/pcsx2/R5900.h index 2b1961e03a..f9a4358188 100644 --- a/pcsx2/R5900.h +++ b/pcsx2/R5900.h @@ -19,16 +19,21 @@ #ifndef __R5900_H__ #define __R5900_H__ -#include +extern bool g_EEFreezeRegs; + +namespace R5900 +{ + // EE Bios function name tables. + extern const char* const bios[256]; struct R5900cpu { void (*Init)(); // throws exceptions on failure. void (*Reset)(); void (*Step)(); void (*Execute)(); /* executes up to a break */ - void (*ExecuteBlock)(); /* executes up to a jump */ - void (*ExecuteVU0Block)(); /* executes up to a jump */ - void (*ExecuteVU1Block)(); /* executes up to a jump */ + void (*ExecuteBlock)(); + void (*ExecuteVU0Block)(); + void (*ExecuteVU1Block)(); void (*EnableVU0micro)(int enable); void (*EnableVU1micro)(int enable); void (*Clear)(u32 Addr, u32 Size); @@ -37,6 +42,9 @@ struct R5900cpu { void (*Shutdown)(); }; +extern s32 EEsCycle; +extern u32 EEoCycle; + extern R5900cpu *Cpu; extern R5900cpu intCpu; extern R5900cpu recCpu; @@ -77,22 +85,22 @@ union CP0regs { BadVAddr, Count, EntryHi, Compare; union { struct { - int IE:1; - int EXL:1; - int ERL:1; - int KSU:2; - int unused0:3; - int IM:8; - int EIE:1; - int _EDI:1; - int CH:1; - int unused1:3; - int BEV:1; - int DEV:1; - int unused2:2; - int FR:1; - int unused3:1; - int CU:4; + u32 IE:1; + u32 EXL:1; + u32 ERL:1; + u32 KSU:2; + u32 unused0:3; + u32 IM:8; + u32 EIE:1; + u32 _EDI:1; + u32 CH:1; + u32 unused1:3; + u32 BEV:1; + u32 DEV:1; + u32 unused2:2; + u32 FR:1; + u32 unused3:1; + u32 CU:4; } b; u32 val; } Status; @@ -125,13 +133,8 @@ struct cpuRegisters { u32 tempcycles; }; -extern s32 EEsCycle; -extern u32 EEoCycle; -extern bool eeEventTestIsActive; -extern PCSX2_ALIGNED16_DECL(cpuRegisters cpuRegs); - // used for optimization -typedef union { +union GPR_reg64 { u64 UD[1]; //64 bits s64 SD[1]; u32 UL[2]; @@ -140,7 +143,7 @@ typedef union { s16 SS[4]; u8 UC[8]; s8 SC[8]; -} GPR_reg64; +}; #define GPR_IS_CONST1(reg) ((reg)<32 && (g_cpuHasConstReg&(1<<(reg)))) #define GPR_IS_CONST2(reg1, reg2) ((g_cpuHasConstReg&(1<<(reg1)))&&(g_cpuHasConstReg&(1<<(reg2)))) @@ -155,9 +158,6 @@ typedef union { if( (reg) < 32 ) g_cpuHasConstReg &= ~(1<<(reg)); \ } -extern PCSX2_ALIGNED16_DECL(GPR_reg64 g_cpuConstRegs[32]); -extern u32 g_cpuHasConstReg, g_cpuFlushedConstReg; - union FPRreg { float f; u32 UL; @@ -169,8 +169,6 @@ struct fpuRegisters { FPRreg ACC; // 32 bit accumulator }; -extern PCSX2_ALIGNED16_DECL(fpuRegisters fpuRegs); - struct tlbs { u32 PageMask,EntryHi; @@ -186,8 +184,6 @@ struct tlbs #endif }; -extern PCSX2_ALIGNED16_DECL(tlbs tlb[48]); - #ifndef _PC_ #define _i64(x) (s64)x @@ -229,29 +225,47 @@ extern PCSX2_ALIGNED16_DECL(tlbs tlb[48]); bool cpuInit(); void cpuReset(); // can throw Exception::FileNotFound. void cpuShutdown(); +void cpuExecuteBios(); void cpuException(u32 code, u32 bd); void cpuTlbMissR(u32 addr, u32 bd); void cpuTlbMissW(u32 addr, u32 bd); void IntcpuBranchTest(); void cpuBranchTest(); void cpuTestHwInts(); + extern void cpuTestINTCInts(); extern void cpuTestDMACInts(); extern void cpuTestTIMRInts(); -void cpuExecuteBios(); -u32 VirtualToPhysicalR(u32 addr); -u32 VirtualToPhysicalW(u32 addr); +//u32 VirtualToPhysicalR(u32 addr); +//u32 VirtualToPhysicalW(u32 addr); -void intDoBranch(u32 target); -void intSetBranch(); -void intExecuteVU0Block(); -void intExecuteVU1Block(); +namespace Interpreter +{ + void intDoBranch(u32 target); + void intSetBranch(); + void intExecuteVU0Block(); + void intExecuteVU1Block(); +} void JumpCheckSym(u32 addr, u32 pc); void JumpCheckSymRet(u32 addr); -extern bool g_EEFreezeRegs; +extern int cpuSetNextBranch( u32 startCycle, s32 delta ); +extern int cpuSetNextBranchDelta( s32 delta ); +extern int cpuTestCycle( u32 startCycle, s32 delta ); +extern void cpuSetBranch(); + +extern PCSX2_ALIGNED16_DECL(fpuRegisters fpuRegs); +extern PCSX2_ALIGNED16_DECL(tlbs tlb[48]); +extern PCSX2_ALIGNED16_DECL(cpuRegisters cpuRegs); +extern PCSX2_ALIGNED16_DECL(GPR_reg64 g_cpuConstRegs[32]); + +extern u32 g_nextBranchCycle; +extern u32 g_cpuHasConstReg, g_cpuFlushedConstReg; +extern bool EventTestIsActive; +extern u32 s_iLastCOP0Cycle; +extern u32 s_iLastPERFCycle[2]; //exception code #define EXC_CODE(x) ((x)<<2) @@ -278,28 +292,6 @@ extern bool g_EEFreezeRegs; #define EXC_TLB_STORE 1 #define EXC_TLB_LOAD 0 -//#define EE_PROFILING //EE Profiling enable - -#ifdef EE_PROFILING //EE Profiling code - -extern u64 profile_starttick; -extern u64 profile_totalticks; - -#define START_EE_PROFILE() \ - profile_starttick = GetCPUTick(); - -#define END_EE_PROFILE() \ - profile_totalticks += GetCPUTick()-profile_starttick; - -#define CLEAR_EE_PROFILE() \ - profile_totalticks = 0; - -#else -#define START_EE_PROFILE() - -#define END_EE_PROFILE() - -#define CLEAR_EE_PROFILE() -#endif +} // End Namespace R5900 #endif /* __R5900_H__ */ diff --git a/pcsx2/RDebug/deci2_dbgp.cpp b/pcsx2/RDebug/deci2_dbgp.cpp index e578122391..5168b414fe 100644 --- a/pcsx2/RDebug/deci2_dbgp.cpp +++ b/pcsx2/RDebug/deci2_dbgp.cpp @@ -26,6 +26,8 @@ #include "Threading.h" using namespace Threading; +using namespace R5900; + struct DECI2_DBGP_HEADER{ DECI2_HEADER h; //+00 u16 id; //+08 diff --git a/pcsx2/SPR.cpp b/pcsx2/SPR.cpp index 8e63fd26b2..47243945ad 100644 --- a/pcsx2/SPR.cpp +++ b/pcsx2/SPR.cpp @@ -22,6 +22,8 @@ #include "SPR.h" #include "iR5900.h" +using R5900::Cpu; + #define spr0 ((DMACh*)&PS2MEM_HW[0xD000]) #define spr1 ((DMACh*)&PS2MEM_HW[0xD400]) @@ -223,7 +225,6 @@ void SPRFROMinterrupt() { spr0->chcr&= ~0x100; hwDmacIrq(8); - cpuRegs.interrupt &= ~(1 << 8); } extern void mfifoGIFtransfer(int); @@ -394,6 +395,5 @@ void SPRTOinterrupt() { spr1->chcr &= ~0x100; hwDmacIrq(9); - cpuRegs.interrupt &= ~(1 << 9); } diff --git a/pcsx2/SaveState.cpp b/pcsx2/SaveState.cpp index 7c2778f119..8eb95f7818 100644 --- a/pcsx2/SaveState.cpp +++ b/pcsx2/SaveState.cpp @@ -33,8 +33,8 @@ #include "Paths.h" -extern u32 s_iLastCOP0Cycle; -extern u32 s_iLastPERFCycle[2]; +using namespace R5900; + extern int g_psxWriteOk; // STATES @@ -83,7 +83,7 @@ string SaveState::GetFilename( int slot ) SaveState::SaveState( const char* msg, const string& destination ) : m_version( g_SaveVersion ) { - Console::WriteLn( "%s %S", params msg, &destination ); + Console::WriteLn( "%s %hs", params msg, &destination ); } s32 CALLBACK gsSafeFreeze( int mode, freezeData *data ) diff --git a/pcsx2/Sif.cpp b/pcsx2/Sif.cpp index 108306a74b..05c5ad56fd 100644 --- a/pcsx2/Sif.cpp +++ b/pcsx2/Sif.cpp @@ -271,7 +271,7 @@ __forceinline void SIF0Dma() // } // } - Cpu->Clear(sif0dma->madr, readSize*4); + R5900::Cpu->Clear(sif0dma->madr, readSize*4); cycles += readSize * BIAS; // fixme : BIAS is factored in below //cycles += readSize; @@ -524,14 +524,11 @@ __forceinline void sif1Interrupt() { __forceinline void EEsif0Interrupt() { sif0dma->chcr &= ~0x100; hwDmacIrq(DMAC_SIF0); - cpuRegs.interrupt &= ~(1 << 5); } __forceinline void EEsif1Interrupt() { hwDmacIrq(DMAC_SIF1); sif1dma->chcr &= ~0x100; - cpuRegs.interrupt &= ~(1 << 6); - } __forceinline void dmaSIF0() { diff --git a/pcsx2/SourceLog.cpp b/pcsx2/SourceLog.cpp index 8166f09c12..77092ab4d1 100644 --- a/pcsx2/SourceLog.cpp +++ b/pcsx2/SourceLog.cpp @@ -30,6 +30,8 @@ #include "Common.h" #include "PsxCommon.h" +using namespace R5900; + FILE *emuLog; #ifdef PCSX2_DEVBUILD diff --git a/pcsx2/Stats.cpp b/pcsx2/Stats.cpp index e3a8046175..0e725e5602 100644 --- a/pcsx2/Stats.cpp +++ b/pcsx2/Stats.cpp @@ -58,6 +58,8 @@ void statsClose() { fclose(f); } +using R5900::cpuRegs; + void statsVSync() { static u64 accum = 0, accumvu1 = 0; static u32 frame = 0; diff --git a/pcsx2/StringUtils.h b/pcsx2/StringUtils.h index 616b47e136..7e276592af 100644 --- a/pcsx2/StringUtils.h +++ b/pcsx2/StringUtils.h @@ -47,11 +47,17 @@ std::string to_string(const T& value) // allow us to use the va_list feature on references. struct VARG_PARAM { + // just some value to make the struct length 32bits instead of 8 bits, so that the + // compiler generates somewhat more efficient code. + uint someval; }; -extern VARG_PARAM va_arg_dummy; +extern const VARG_PARAM va_arg_dummy; extern void ssprintf(std::string& dest, const std::string& fmt, VARG_PARAM dummy, ...); +extern void ssappendf( std::string& dest, const std::string& format, VARG_PARAM dummy, ...); extern void vssprintf(std::string& dest, const std::string& format, va_list args); +extern void vssappendf(std::string& dest, const std::string& format, va_list args); + extern std::string fmt_string( const std::string& fmt, VARG_PARAM dummy, ... ); #endif diff --git a/pcsx2/System.cpp b/pcsx2/System.cpp index eb17bc9040..10e55f2b78 100644 --- a/pcsx2/System.cpp +++ b/pcsx2/System.cpp @@ -82,6 +82,7 @@ static void trim( string& line ) line.erase( 0, beginning_of_string ); } +using R5900::cpuRegs; // This function should be called once during program execution. void SysDetect() @@ -147,4 +148,4 @@ void SysDetect() } Console::ClearColor(); -} \ No newline at end of file +} diff --git a/pcsx2/VU0.cpp b/pcsx2/VU0.cpp index 89a2116d59..432f367ddc 100644 --- a/pcsx2/VU0.cpp +++ b/pcsx2/VU0.cpp @@ -49,6 +49,8 @@ #include "VUflags.h" +using namespace R5900; + PCSX2_ALIGNED16(VURegs VU0); void COP2_BC2() { Int_COP2BC2PrintTable[_Rt_]();} @@ -63,7 +65,9 @@ void COP2_Unknown() CPU_LOG("Unknown COP2 opcode called\n"); } -namespace EE{ namespace Interpreter{ namespace OpcodeImpl +namespace R5900 { +namespace Interpreter{ +namespace OpcodeImpl { void LQC2() { u32 addr = cpuRegs.GPR.r[_Rs_].UL[0] + (s16)cpuRegs.code; @@ -339,50 +343,6 @@ void VFCSET() { VU0.code = cpuRegs.code; _vuFCSET(&VU0); } void VFCGET() { VU0.code = cpuRegs.code; _vuFCGET(&VU0); } void VXITOP() { VU0.code = cpuRegs.code; _vuXITOP(&VU0); } -#define CP2COND (((VU0.VI[REG_VPU_STAT].US[0] >> 8) & 1)) - -void BC2F() -{ - if (CP2COND == 0) - { - SysPrintf("VU0 Macro Branch \n"); - intDoBranch(_BranchTarget_); - } -} -void BC2T() -{ - if (CP2COND == 1) - { - SysPrintf("VU0 Macro Branch \n"); - intDoBranch(_BranchTarget_); - } -} - -void BC2FL() -{ - if (CP2COND == 0) - { - SysPrintf("VU0 Macro Branch \n"); - intDoBranch(_BranchTarget_); - } - else - { - cpuRegs.pc+= 4; - } -} -void BC2TL() -{ - if (CP2COND == 1) - { - SysPrintf("VU0 Macro Branch \n"); - intDoBranch(_BranchTarget_); - } - else - { - cpuRegs.pc+= 4; - } -} - void vu0Finish() { if( (VU0.VI[REG_VPU_STAT].UL & 0x1) ) { @@ -403,13 +363,3 @@ void vu0Finish() } } } - -void VCALLMS() { - vu0Finish(); - vu0ExecMicro(((cpuRegs.code >> 6) & 0x7FFF) * 8); -} - -void VCALLMSR() { - vu0Finish(); - vu0ExecMicro(VU0.VI[REG_CMSAR0].US[0] * 8); -} diff --git a/pcsx2/VU0.h b/pcsx2/VU0.h deleted file mode 100644 index 8b0614d804..0000000000 --- a/pcsx2/VU0.h +++ /dev/null @@ -1,46 +0,0 @@ -/* Pcsx2 - Pc Ps2 Emulator - * Copyright (C) 2002-2008 Pcsx2 Team - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA - */ - -#ifndef __VU0_H__ -#define __VU0_H__ - -#include "VU.h" -#define Lcode cpuRegs.code - -int vu0Init(); -void vu0Reset(); -void vu0ResetRegs(); -void vu0Shutdown(); - -void recResetVU0( void ); - -void vu0Finish(); - -extern char *recMemVU0; /* VU0 blocks */ -extern char *recVU0; /* VU1 mem */ -extern char *recVU0mac; -extern char *recVU0status; -extern char *recVU0clip; -extern char *recVU0Q; -extern char *recVU0cycles; -extern char* recVU0XMMRegs; -extern char *recPtrVU0; - -extern u32 vu0recpcold; - -#endif /* __VU0_H__ */ diff --git a/pcsx2/VU0micro.cpp b/pcsx2/VU0micro.cpp index c7ca93246f..3098843876 100644 --- a/pcsx2/VU0micro.cpp +++ b/pcsx2/VU0micro.cpp @@ -61,6 +61,8 @@ void iDumpVU0Registers() #endif } +using namespace R5900; + int vu0Init() { #ifdef PCSX2_VIRTUAL_MEM @@ -117,7 +119,7 @@ int vu0Init() VU0.vuExec = vu0Exec; VU0.vifRegs = vif0Regs; - if( CHECK_VU0REC ) SuperVUInit(0); + if( CHECK_VU0REC ) Dynarec::SuperVUInit(0); vu0Reset(); @@ -126,7 +128,7 @@ int vu0Init() void vu0Shutdown() { - if( CHECK_VU0REC ) SuperVUDestroy(0); + if( CHECK_VU0REC ) Dynarec::SuperVUDestroy(0); #ifdef PCSX2_VIRTUAL_MEM if( !SysMapUserPhysicalPages(VU0.Mem, 16, NULL, 0) ) @@ -163,12 +165,7 @@ void vu0Reset() memset(VU0.Mem, 0, 4*1024); memset(VU0.Micro, 0, 4*1024); - recResetVU0(); -} - -void recResetVU0( void ) -{ - if( CHECK_VU0REC ) SuperVUReset(0); + if( CHECK_VU0REC ) Dynarec::recResetVU0(); } void SaveState::vu0Freeze() { diff --git a/pcsx2/VU1micro.cpp b/pcsx2/VU1micro.cpp index 561e360076..129835bfc0 100644 --- a/pcsx2/VU1micro.cpp +++ b/pcsx2/VU1micro.cpp @@ -90,7 +90,7 @@ int vu1Init() VU1.vuExec = vu1Exec; VU1.vifRegs = vif1Regs; - if( CHECK_VU1REC ) recVU1Init(); + if( CHECK_VU1REC ) Dynarec::recVU1Init(); vu1Reset(); @@ -98,7 +98,7 @@ int vu1Init() } void vu1Shutdown() { - if( CHECK_VU1REC ) recVU1Shutdown(); + if( CHECK_VU1REC ) Dynarec::recVU1Shutdown(); } void vu1ResetRegs() @@ -120,7 +120,7 @@ void vu1Reset() { memset(VU1.Mem, 0, 16*1024); memset(VU1.Micro, 0, 16*1024); - recResetVU1(); + Dynarec::recResetVU1(); } void SaveState::vu1Freeze() { @@ -140,7 +140,7 @@ void vu1ExecMicro(u32 addr) SysPrintf("Previous Microprogram still running on VU1\n"); do { - Cpu->ExecuteVU1Block(); + R5900::Cpu->ExecuteVU1Block(); } while(VU0.VI[REG_VPU_STAT].UL & 0x100); } VUM_LOG("vu1ExecMicro %x\n", addr); @@ -154,7 +154,7 @@ void vu1ExecMicro(u32 addr) //do { FreezeXMMRegs(1); - Cpu->ExecuteVU1Block(); + R5900::Cpu->ExecuteVU1Block(); FreezeXMMRegs(0); //} while(VU0.VI[REG_VPU_STAT].UL & 0x100); // rec can call vu1ExecMicro diff --git a/pcsx2/VUmicro.h b/pcsx2/VUmicro.h index 7cd64dc1ae..d30464ea0a 100644 --- a/pcsx2/VUmicro.h +++ b/pcsx2/VUmicro.h @@ -72,7 +72,6 @@ void recResetVU0( void ); int vu1Init(); void vu1Reset(); void vu1ResetRegs(); -void recResetVU1( void ); void vu1Shutdown(); void vu1ExecMicro(u32 addr); void vu1Exec(VURegs* VU); diff --git a/pcsx2/Vif.cpp b/pcsx2/Vif.cpp index a289f85a49..fa3d8ff491 100644 --- a/pcsx2/Vif.cpp +++ b/pcsx2/Vif.cpp @@ -572,7 +572,6 @@ void mfifoVIF1transfer(int qwc) { void vifMFIFOInterrupt() { - if(vif1.irq && vif1.tag.size == 0) { vif1Regs->stat|= VIF1_STAT_INT; hwIntcIrq(5); @@ -581,7 +580,6 @@ void vifMFIFOInterrupt() { vif1Regs->stat&= ~0x1F000000; // FQC=0 vif1ch->chcr &= ~0x100; - cpuRegs.interrupt &= ~(1 << 10); return; } } @@ -590,7 +588,6 @@ void vifMFIFOInterrupt() if(vifqwc <= 0){ //SysPrintf("Empty\n"); hwDmacIrq(14); - cpuRegs.interrupt &= ~(1 << 10); return; } mfifoVIF1transfer(0); @@ -606,5 +603,4 @@ void vifMFIFOInterrupt() vif1Regs->stat&= ~0x1F000000; // FQC=0 // } - cpuRegs.interrupt &= ~(1 << 10); } diff --git a/pcsx2/VifDma.cpp b/pcsx2/VifDma.cpp index b6afaae166..8ff290fe30 100644 --- a/pcsx2/VifDma.cpp +++ b/pcsx2/VifDma.cpp @@ -31,6 +31,8 @@ #endif using namespace std; // for min / max +using R5900::Cpu; // for detecting VU1 dummy / frameskip. +using R5900::cpuRegs; //#define VIFUNPACKDEBUG //enable unpack debugging output @@ -205,9 +207,7 @@ __forceinline void vif0FLUSH() { int _cycles; _cycles = VU0.cycle; - //FreezeXMMRegs(1); vu0Finish(); - //FreezeXMMRegs(0); g_vifCycles+= (VU0.cycle - _cycles)*BIAS; } @@ -2108,7 +2108,6 @@ __forceinline void vif1Interrupt() { vif1Regs->stat&= ~0x1F000000; // FQC=0 // One game doesnt like vif stalling at end, cant remember what. Spiderman isnt keen on it tho vif1ch->chcr &= ~0x100; - cpuRegs.interrupt &= ~(1 << 1); return; } //return 0; diff --git a/pcsx2/vssprintf.cpp b/pcsx2/vssprintf.cpp index 6e73fe87f4..274bb5ba85 100644 --- a/pcsx2/vssprintf.cpp +++ b/pcsx2/vssprintf.cpp @@ -503,12 +503,12 @@ static void flt( std::string& dest, double num, int size, int precision, char fm #endif +/////////////////////////////////////////////////////////////////////////// // This is a "mostly" direct replacement for vsprintf, that is more secure and easier // to use than vsnprintf or vsprintf_s. See the docs for ssprintf for usage notes. -void vssprintf(std::string& dest, const std::string& format, va_list args) +void vssappendf(std::string& dest, const std::string& format, va_list args) { - int len; - int i, base; + int base; int flags; // Flags to number() @@ -516,7 +516,9 @@ void vssprintf(std::string& dest, const std::string& format, va_list args) int precision; // Min. # of digits for integers; max number of chars for from string int qualifier; // 'h', 'l', or 'L' for integer fields - dest.clear(); + // Optimization: Memory is cheap. Allocating it on the fly is not. Allocate more room + // than we'll likely need right upfront! + dest.reserve( format.length() * 2 ); for( const char* fmt = format.c_str(); *fmt; fmt++ ) { @@ -571,7 +573,7 @@ repeat: // Get the conversion qualifier qualifier = -1; - if (*fmt == 'h' || *fmt == 'l' || *fmt == 'L') + if (*fmt == 'h' || *fmt == 'l' || *fmt == 'L' ) { qualifier = *fmt; fmt++; @@ -590,24 +592,47 @@ repeat: case 's': { - const char* s = va_arg(args, char *); - if (!s) s = ""; - len = strnlen(s, precision); - if (!(flags & LEFT)) while (len < field_width--) dest += ' '; - for (i = 0; i < len; ++i) dest += *s++; - while (len < field_width--) dest += ' '; - } - continue; + // let's add support for std::string as a formatted parameter! (air) + if( qualifier == 'h' ) + { + static const string nullstring( "" ); - // let's add support for std::string as a formatted parameter! (air) - case 'S': - { - std::string* ss = va_arg(args, std::string*); - const char* s = ( ss!=NULL ) ? ss->c_str() : ""; - len = strnlen(s, precision); - if (!(flags & LEFT)) while (len < field_width--) dest += ' '; - for (i = 0; i < len; ++i) dest += *s++; - while (len < field_width--) dest += ' '; + const std::string* ss = va_arg(args, std::string*); + if( ss == NULL ) ss = &nullstring; + int len = ss->length(); + if( precision < 0 ) + { + // no precision override so just copy the whole string. + if (!(flags & LEFT)) while (len < field_width--) dest += ' '; + dest += *ss; + } + else + { + if( len > precision ) len = precision; + if (!(flags & LEFT)) while (len < field_width--) dest += ' '; + dest.append( ss->begin(), ss->begin()+len ); + } + while (len < field_width--) dest += ' '; + } + else + { + const char* s = va_arg(args, char *); + if (!s) s = ""; + + int len = strlen(s); + if( precision < 0 ) + { + if (!(flags & LEFT)) while (len < field_width--) dest += ' '; + dest += s; + } + else + { + if( len > precision ) len = precision; + if (!(flags & LEFT)) while (len < field_width--) dest += ' '; + dest.append( s, s+len ); + } + while (len < field_width--) dest += ' '; + } } continue; @@ -689,6 +714,7 @@ repeat: if (qualifier == 'L') { + // 64-bit integer support! (air) number(dest, va_arg(args, s64), base, field_width, precision, flags); } else @@ -704,6 +730,22 @@ repeat: } } +void vssprintf( std::string& dest, const std::string& format, va_list args ) +{ + dest.clear(); + vssappendf( dest, format, args ); +} + +void ssappendf( std::string& dest, const std::string& format, VARG_PARAM dummy, ...) +{ + dummy_assert(); + + va_list args; + va_start(args, dummy); + vssappendf( dest, format, args ); + va_end(args); +} + // This is a "mostly" direct replacement for sprintf, based on std::string. // The most notable difference in use is the requirement of a "params" keyword delimiting // the format string from the parameters used to fill the string's tokens. It looks @@ -712,10 +754,12 @@ repeat: // ssprintf( dest, "Yo Joe, %d. In the Hizzou %s.", params intval, strval ); // // In addition to all standard printf formatting tokens, ssprintf also supports a new token -// for std::string parameters as %S (passed by reference/pointer). Note that these are -// passed by pointer so you *must* use the & sign most of the time. Example: +// for std::string parameters as %hs (passed by reference/pointer). I opted for %hs (using 'h' +// as a qualifier) over %S because under MSVC %S acts as a char/widechar conversion. Note +// that these are passed by pointer so you *must* use the & operator most of the time. +// Example: // -// ssprintf( dest, "Yo Joe, %S.", params &strval ); +// ssprintf( dest, "Yo Joe, %hs.", params &strval ); // // This can be a cavet of sorts since forgetting to use the & will always compile but // will cause undefined behavior and odd crashes (much like how the same thing happens @@ -753,4 +797,5 @@ std::string fmt_string( const std::string& fmt, VARG_PARAM dummy, ... ) va_end( args ); return retval; -} \ No newline at end of file +} + diff --git a/pcsx2/vtlb.cpp b/pcsx2/vtlb.cpp index fd61853c67..6718013b89 100644 --- a/pcsx2/vtlb.cpp +++ b/pcsx2/vtlb.cpp @@ -21,6 +21,8 @@ #include "vtlb.h" #include "x86/ix86/ix86.h" +using namespace R5900; + #ifdef PCSX2_DEVBUILD #define verify(x) {if (!(x)) { (*(u8*)0)=3; }} #else @@ -480,7 +482,7 @@ void vtlb_Term() } -namespace EE { namespace Dynarec +namespace Dynarec { //ecx = addr @@ -695,6 +697,6 @@ void vtlb_DynGenWrite(u32 sz,int freereg) x86SetJ8(cont); } -} } +} #endif // PCSX2_VIRTUAL_MEM diff --git a/pcsx2/vtlb.h b/pcsx2/vtlb.h index 2792702ef3..e5d8c6dc87 100644 --- a/pcsx2/vtlb.h +++ b/pcsx2/vtlb.h @@ -59,12 +59,12 @@ void __fastcall vtlb_memWrite32(u32 mem, u32 value); void __fastcall vtlb_memWrite64(u32 mem, const u64* value); void __fastcall vtlb_memWrite128(u32 mem, const u64* value); -namespace EE { namespace Dynarec { +namespace Dynarec { void vtlb_DynGenWrite(u32 sz,int freereg); void vtlb_DynGenRead(u32 sz,int freereg); -} } +} #endif diff --git a/pcsx2/windows/ConfigDlg.cpp b/pcsx2/windows/ConfigDlg.cpp index b158b327cc..c4938b762d 100644 --- a/pcsx2/windows/ConfigDlg.cpp +++ b/pcsx2/windows/ConfigDlg.cpp @@ -69,7 +69,7 @@ struct ComboInitializer string tmpStr; Path::Combine( tmpStr, Config.PluginsDir, FindData.cFileName ); Lib = LoadLibrary(tmpStr.c_str()); - if (Lib == NULL) { Console::Error( "%S: %s", params &tmpStr, SysLibError()); return false; } + if (Lib == NULL) { Console::Error( "%hs: %s", params &tmpStr, SysLibError()); return false; } PS2E_GetLibType = (_PS2EgetLibType) GetProcAddress((HMODULE)Lib,"PS2EgetLibType"); PS2E_GetLibName = (_PS2EgetLibName) GetProcAddress((HMODULE)Lib,"PS2EgetLibName"); diff --git a/pcsx2/windows/CpuDlg.cpp b/pcsx2/windows/CpuDlg.cpp index 64dbc6f3f2..ada410745f 100644 --- a/pcsx2/windows/CpuDlg.cpp +++ b/pcsx2/windows/CpuDlg.cpp @@ -159,7 +159,7 @@ BOOL CALLBACK CpuDlgProc(HWND hW, UINT uMsg, WPARAM wParam, LPARAM lParam) Config.Options = newopts; } else - UpdateVSyncRate(); + R5900::UpdateVSyncRate(); SaveConfig(); diff --git a/pcsx2/windows/DebugMemory.cpp b/pcsx2/windows/DebugMemory.cpp index 5c85820814..1c8736a31b 100644 --- a/pcsx2/windows/DebugMemory.cpp +++ b/pcsx2/windows/DebugMemory.cpp @@ -22,6 +22,7 @@ #include "Common.h" #include "resource.h" +using namespace R5900; unsigned long memory_addr; BOOL mem_inupdate = FALSE; diff --git a/pcsx2/windows/Debugger.cpp b/pcsx2/windows/Debugger.cpp index 4a1868543d..b13dbc4da6 100644 --- a/pcsx2/windows/Debugger.cpp +++ b/pcsx2/windows/Debugger.cpp @@ -27,12 +27,13 @@ #include "PsxMem.h" #include "R3000A.h" +using namespace R5900; + #ifdef _MSC_VER #pragma warning(disable:4996) //ignore the stricmp deprecated warning #endif extern void (*IOP_DEBUG_BSC[64])(char *buf); -extern void UpdateR5900op(); void RefreshIOPDebugger(void); extern int ISR3000A;//for disasm HWND hWnd_debugdisasm, hWnd_debugscroll,hWnd_IOP_debugdisasm, hWnd_IOP_debugscroll; @@ -173,7 +174,7 @@ BOOL APIENTRY DumpProc(HWND hDlg, UINT message, WPARAM wParam, LPARAM lParam) sprintf(buf, "%08X %08X: %s", temp, cpuRegs.code, tmp); output.append( buf ); - EE::OpcodeTables::Standard[_Opcode_].decode( output ); + R5900::OpcodeTables::tbl_Standard[_Opcode_].disasm( output ); fprintf(fp, "%s\n", buf); @@ -580,7 +581,8 @@ BOOL APIENTRY DebuggerProc(HWND hDlg, UINT message, WPARAM wParam, LPARAM lParam return TRUE; case IDC_CPUOP: - UpdateR5900op(); + // This updated a global opcode counter. + //UpdateR5900op(); return TRUE; case IDC_DEBUG_BP_EXEC: @@ -626,9 +628,6 @@ BOOL APIENTRY DebuggerProc(HWND hDlg, UINT message, WPARAM wParam, LPARAM lParam return FALSE; } -/* this lives in interpreter.c */ -extern const char* bios[]; - void RefreshDebugger(void) { unsigned long t; @@ -651,7 +650,7 @@ void RefreshDebugger(void) if (0x0c == *mem && 0x24030000 == (*(mem-1) & 0xFFFFFF00)){ /* it's a syscall preceeded by a li v1,$data instruction. */ u8 bios_call = *(mem-1) & 0xFF; - sprintf(syscall_str, "%08X:\tsyscall\t%s", t, bios[bios_call]); + sprintf(syscall_str, "%08X:\tsyscall\t%s", t, R5900::bios[bios_call]); } else { std::string str; disR5900Fasm(str, *mem, t); diff --git a/pcsx2/windows/Debugreg.cpp b/pcsx2/windows/Debugreg.cpp index 9f0ec9fe94..ddfefde6d9 100644 --- a/pcsx2/windows/Debugreg.cpp +++ b/pcsx2/windows/Debugreg.cpp @@ -28,10 +28,14 @@ #include "R3000a.h" #include "VUmicro.h" +using namespace R5900; + HINSTANCE m_hInst; HWND m_hWnd; char text1[256]; +// Wow! This module is a lot of copy-paste! +// Between this and DisAsm modules, *someone* needs a new Ctrl-V combo on their keyboard. (air) /*R3000a registers handle */ static HWND IOPGPR0Handle=NULL; diff --git a/pcsx2/windows/RDebugger.cpp b/pcsx2/windows/RDebugger.cpp index 18683d9c21..70e9bd25c7 100644 --- a/pcsx2/windows/RDebugger.cpp +++ b/pcsx2/windows/RDebugger.cpp @@ -26,6 +26,8 @@ #include "PsxCommon.h" #include "../rdebug/deci2.h" +using namespace R5900; + u32 port=8510; SOCKET serversocket, remote; char message[1024]; //message to add to listbox diff --git a/pcsx2/windows/VCprojects/pcsx2_2008.vcproj b/pcsx2/windows/VCprojects/pcsx2_2008.vcproj index bd365025e9..49a6e7e397 100644 --- a/pcsx2/windows/VCprojects/pcsx2_2008.vcproj +++ b/pcsx2/windows/VCprojects/pcsx2_2008.vcproj @@ -1448,6 +1448,10 @@ /> + + + + @@ -2317,7 +2325,6 @@ - - - - - - - - - - - - - - @@ -2710,14 +2689,6 @@ RelativePath="..\..\PsxDma.h" > - - - - @@ -2757,10 +2728,6 @@ - - @@ -3078,10 +3045,6 @@ RelativePath="..\..\VU0.cpp" > - - @@ -3178,14 +3141,6 @@ - - - - @@ -3227,6 +3182,50 @@ > + + + + + + + + + + + + + + + + + + + + + + = m_workspace.GetLength() - 2 ) - Console::Notice( "Loadini Warning > Possible truncated value on key '%S'", params &var ); + Console::Notice( "Loadini Warning > Possible truncated value on key '%hs'", params &var ); value = m_workspace.GetPtr(); } @@ -167,7 +167,7 @@ public: ); if( retval >= sizeof(value) - 2 ) - Console::Notice( "Loadini Warning > Possible truncated value on key '%S'", params &var ); + Console::Notice( "Loadini Warning > Possible truncated value on key '%hs'", params &var ); } void Entry( const string& var, int& value, const int defvalue=0 ) @@ -201,7 +201,7 @@ public: if( enumArray[i] == NULL ) { - Console::Notice( "Loadini Warning > Unrecognized value '%S' on key '%S'\n\tUsing the default setting of '%s'.", + Console::Notice( "Loadini Warning > Unrecognized value '%hs' on key '%hs'\n\tUsing the default setting of '%s'.", params &retval, &var, enumArray[defvalue] ); value = defvalue; } diff --git a/pcsx2/x86/fast_routines.cpp b/pcsx2/x86/fast_routines.cpp index aa8f457bc4..82d3c375b1 100644 --- a/pcsx2/x86/fast_routines.cpp +++ b/pcsx2/x86/fast_routines.cpp @@ -86,6 +86,8 @@ void checkregs() if( g_EEFreezeRegs ) assert( g_globalMMXSaved ); } #endif + + __declspec(align(16)) u8 _xmm_backup[16*2]; //this one checks for alligments too ... __declspec(naked) void __fastcall memcpy_raz_u(void *dest, const void *src, size_t bytes) diff --git a/pcsx2/x86/iCOP2.cpp b/pcsx2/x86/iCOP2.cpp index 3d60062d04..9a0b7c030f 100644 --- a/pcsx2/x86/iCOP2.cpp +++ b/pcsx2/x86/iCOP2.cpp @@ -30,12 +30,19 @@ #include "VUmicro.h" #include "iVUmicro.h" - #ifdef _WIN32 #pragma warning(disable:4244) #pragma warning(disable:4761) #endif +extern void _vu0WaitMicro(); + +// Temporary until I can get the VUs namespaced properly. +using namespace Dynarec::R5900; + +namespace Dynarec +{ + #define _Ft_ _Rt_ #define _Fs_ _Rd_ #define _Fd_ _Sa_ @@ -47,12 +54,11 @@ void recCop2BranchCall( void (*func)() ) { SetFPUstate(); - EE::Dynarec::recBranchCall( func ); + R5900::recBranchCall( func ); _freeX86regs(); } #define REC_COP2_FUNC( f ) \ - void f(); \ void rec##f(s32 info) \ { \ Console::Notice("Warning > cop2 "#f" called"); \ @@ -73,7 +79,6 @@ void recV##f( s32 info ) { \ recVUMI_##f( &VU0, info ); \ } -extern u32 dumplog; #define REC_COP2_VU0_Q(f) \ void recV##f( s32 info ) { \ recVUMI_##f( &VU0, info ); \ @@ -93,8 +98,6 @@ void recCOP2(s32 info); void recCOP2_SPECIAL(s32 info); void recCOP2_BC2(s32 info); void recCOP2_SPECIAL2(s32 info); - -extern void _vu0WaitMicro(); static void recCFC2(s32 info) { @@ -680,3 +683,5 @@ void recCOP2_SPECIAL2(s32 info) int opc=(cpuRegs.code & 0x3) | ((cpuRegs.code >> 4) & 0x7c); recCOP2SPECIAL2t[opc](info); } + +} \ No newline at end of file diff --git a/pcsx2/x86/iCP0.cpp b/pcsx2/x86/iCP0.cpp index f296d7fd6a..f2c5fd6325 100644 --- a/pcsx2/x86/iCP0.cpp +++ b/pcsx2/x86/iCP0.cpp @@ -30,6 +30,12 @@ #include "iR5900.h" #include "iCP0.h" + +namespace Dynarec { +namespace R5900 { +namespace OpcodeImpl +{ + /********************************************************* * COP0 opcodes * * * @@ -71,8 +77,6 @@ REC_SYS(TLBWR); REC_SYS(TLBP); //////////////////////////////////////////////////// -extern u32 s_iLastCOP0Cycle; -extern u32 s_iLastPERFCycle[2]; void recMFC0( void ) { @@ -326,14 +330,14 @@ void recMTC0() void recERET() { - EE::Dynarec::recBranchCall( ERET ); + recBranchCall( R5900::Interpreter::OpcodeImpl::ERET ); } void recEI() { // must branch after enabling interrupts, so that anything // pending gets triggered properly. - EE::Dynarec::recBranchCall( EI ); + recBranchCall( R5900::Interpreter::OpcodeImpl::EI ); } void recDI() @@ -347,10 +351,9 @@ void recDI() MOV32RtoM( (uptr)&g_nextBranchCycle, ECX ); iFlushCall(0); - CALLFunc( (uptr)DI ); + CALLFunc( (uptr)R5900::Interpreter::OpcodeImpl::DI ); } - /*void rec(COP0) { } @@ -378,4 +381,6 @@ void rec(TLBWR) { void rec(TLBP) { }*/ +}}} + #endif diff --git a/pcsx2/x86/iCP0.h b/pcsx2/x86/iCP0.h index cf754b5a4d..886118d6cb 100644 --- a/pcsx2/x86/iCP0.h +++ b/pcsx2/x86/iCP0.h @@ -24,18 +24,25 @@ * * *********************************************************/ -void recMFC0( void ); -void recMTC0( void ); -void recBC0F( void ); -void recBC0T( void ); -void recBC0FL( void ); -void recBC0TL( void ); -void recTLBR( void ); -void recTLBWI( void ); -void recTLBWR( void ); -void recTLBP( void ); -void recERET( void ); -void recDI( void ); -void recEI( void ); +namespace Dynarec { +namespace R5900 { +namespace OpcodeImpl +{ + void recCOP0_Unknown(); + void recMFC0( void ); + void recMTC0( void ); + void recBC0F( void ); + void recBC0T( void ); + void recBC0FL( void ); + void recBC0TL( void ); + void recTLBR( void ); + void recTLBWI( void ); + void recTLBWR( void ); + void recTLBP( void ); + void recERET( void ); + void recDI( void ); + void recEI( void ); + +}}} #endif diff --git a/pcsx2/x86/iCore.cpp b/pcsx2/x86/iCore.cpp index ebd552feb1..fa670c06c4 100644 --- a/pcsx2/x86/iCore.cpp +++ b/pcsx2/x86/iCore.cpp @@ -28,6 +28,12 @@ #include "iCore.h" #include "R3000A.h" +// Required because the iCore has tons of code shared between both the EE and IOP.. ugh. +using namespace R5900; + +namespace Dynarec +{ + u16 g_x86AllocCounter = 0; u16 g_xmmAllocCounter = 0; @@ -38,7 +44,6 @@ u32 g_cpuRegHasSignExt = 0, g_cpuPrevRegHasSignExt = 0; // set if upper 32 bits // used to make sure regs don't get changed while in recompiler // use FreezeMMXRegs, FreezeXMMRegs -u8 g_globalXMMSaved = 0; u32 g_recWriteback = 0; #ifdef _DEBUG @@ -46,7 +51,6 @@ char g_globalXMMLocked = 0; #endif _xmmregs xmmregs[XMMREGS], s_saveXMMregs[XMMREGS]; -PCSX2_ALIGNED16(u64 g_globalXMMData[2*XMMREGS]); // X86 caching _x86regs x86regs[X86REGS], s_saveX86regs[X86REGS]; @@ -1004,84 +1008,6 @@ void _freeXMMregs() } } -__forceinline void FreezeXMMRegs_(int save) -{ - //SysPrintf("FreezeXMMRegs_(%d); [%d]\n", save, g_globalXMMSaved); - assert( g_EEFreezeRegs ); - - if( save ) { - g_globalXMMSaved++; - if( g_globalXMMSaved > 1 ){ - //SysPrintf("XMM Already saved\n"); - return; - } - - -#ifdef _MSC_VER - __asm { - movaps xmmword ptr [g_globalXMMData + 0x00], xmm0 - movaps xmmword ptr [g_globalXMMData + 0x10], xmm1 - movaps xmmword ptr [g_globalXMMData + 0x20], xmm2 - movaps xmmword ptr [g_globalXMMData + 0x30], xmm3 - movaps xmmword ptr [g_globalXMMData + 0x40], xmm4 - movaps xmmword ptr [g_globalXMMData + 0x50], xmm5 - movaps xmmword ptr [g_globalXMMData + 0x60], xmm6 - movaps xmmword ptr [g_globalXMMData + 0x70], xmm7 - } - -#else - __asm__(".intel_syntax\n" - "movaps [%0+0x00], %%xmm0\n" - "movaps [%0+0x10], %%xmm1\n" - "movaps [%0+0x20], %%xmm2\n" - "movaps [%0+0x30], %%xmm3\n" - "movaps [%0+0x40], %%xmm4\n" - "movaps [%0+0x50], %%xmm5\n" - "movaps [%0+0x60], %%xmm6\n" - "movaps [%0+0x70], %%xmm7\n" - ".att_syntax\n" : : "r"(g_globalXMMData) ); - -#endif // _MSC_VER - } - else { - if( g_globalXMMSaved==0 ) - { - //SysPrintf("XMM Regs not saved!\n"); - return; - } - - // TODO: really need to backup all regs? - g_globalXMMSaved--; - if( g_globalXMMSaved > 0 ) return; - -#ifdef _MSC_VER - __asm { - movaps xmm0, xmmword ptr [g_globalXMMData + 0x00] - movaps xmm1, xmmword ptr [g_globalXMMData + 0x10] - movaps xmm2, xmmword ptr [g_globalXMMData + 0x20] - movaps xmm3, xmmword ptr [g_globalXMMData + 0x30] - movaps xmm4, xmmword ptr [g_globalXMMData + 0x40] - movaps xmm5, xmmword ptr [g_globalXMMData + 0x50] - movaps xmm6, xmmword ptr [g_globalXMMData + 0x60] - movaps xmm7, xmmword ptr [g_globalXMMData + 0x70] - } - -#else - __asm__(".intel_syntax\n" - "movaps %%xmm0, [%0+0x00]\n" - "movaps %%xmm1, [%0+0x10]\n" - "movaps %%xmm2, [%0+0x20]\n" - "movaps %%xmm3, [%0+0x30]\n" - "movaps %%xmm4, [%0+0x40]\n" - "movaps %%xmm5, [%0+0x50]\n" - "movaps %%xmm6, [%0+0x60]\n" - "movaps %%xmm7, [%0+0x70]\n" - ".att_syntax\n" : : "r"(g_globalXMMData) ); - -#endif // _MSC_VER - } -} - // PSX void _psxMoveGPRtoR(x86IntRegType to, int fromgpr) { @@ -1389,3 +1315,75 @@ BASEBLOCKEX** GetAllBaseBlocks(int* pnum, int cpu) { return s_vecBaseBlocksEx[cpu].GetAll(pnum); } + +//////////////////////////////////////////////////// +//#include "R3000A.h" +//#include "PsxCounters.h" +//#include "PsxMem.h" +//extern tIPU_BP g_BP; + +#if 0 +extern u32 psxdump; +extern void iDumpPsxRegisters(u32 startpc, u32 temp); +extern Counter counters[6]; +extern int rdram_devices; // put 8 for TOOL and 2 for PS2 and PSX +extern int rdram_sdevid; +#endif + +void iDumpRegisters(u32 startpc, u32 temp) +{ +// [TODO] fixme : thie code is broken and has no labels. Needs a rewrite to be useful. + +#if 0 + + int i; + const char* pstr;// = temp ? "t" : ""; + const u32 dmacs[] = {0x8000, 0x9000, 0xa000, 0xb000, 0xb400, 0xc000, 0xc400, 0xc800, 0xd000, 0xd400 }; + const char* psymb; + + if (temp) + pstr = "t"; + else + pstr = ""; + + psymb = disR5900GetSym(startpc); + + if( psymb != NULL ) + __Log("%sreg(%s): %x %x c:%x\n", pstr, psymb, startpc, cpuRegs.interrupt, cpuRegs.cycle); + else + __Log("%sreg: %x %x c:%x\n", pstr, startpc, cpuRegs.interrupt, cpuRegs.cycle); + for(i = 1; i < 32; ++i) __Log("%s: %x_%x_%x_%x\n", disRNameGPR[i], cpuRegs.GPR.r[i].UL[3], cpuRegs.GPR.r[i].UL[2], cpuRegs.GPR.r[i].UL[1], cpuRegs.GPR.r[i].UL[0]); + //for(i = 0; i < 32; i+=4) __Log("cp%d: %x_%x_%x_%x\n", i, cpuRegs.CP0.r[i], cpuRegs.CP0.r[i+1], cpuRegs.CP0.r[i+2], cpuRegs.CP0.r[i+3]); + //for(i = 0; i < 32; ++i) __Log("%sf%d: %f %x\n", pstr, i, fpuRegs.fpr[i].f, fpuRegs.fprc[i]); + //for(i = 1; i < 32; ++i) __Log("%svf%d: %f %f %f %f, vi: %x\n", pstr, i, VU0.VF[i].F[3], VU0.VF[i].F[2], VU0.VF[i].F[1], VU0.VF[i].F[0], VU0.VI[i].UL); + for(i = 0; i < 32; ++i) __Log("%sf%d: %x %x\n", pstr, i, fpuRegs.fpr[i].UL, fpuRegs.fprc[i]); + for(i = 1; i < 32; ++i) __Log("%svf%d: %x %x %x %x, vi: %x\n", pstr, i, VU0.VF[i].UL[3], VU0.VF[i].UL[2], VU0.VF[i].UL[1], VU0.VF[i].UL[0], VU0.VI[i].UL); + __Log("%svfACC: %x %x %x %x\n", pstr, VU0.ACC.UL[3], VU0.ACC.UL[2], VU0.ACC.UL[1], VU0.ACC.UL[0]); + __Log("%sLO: %x_%x_%x_%x, HI: %x_%x_%x_%x\n", pstr, cpuRegs.LO.UL[3], cpuRegs.LO.UL[2], cpuRegs.LO.UL[1], cpuRegs.LO.UL[0], + cpuRegs.HI.UL[3], cpuRegs.HI.UL[2], cpuRegs.HI.UL[1], cpuRegs.HI.UL[0]); + __Log("%sCycle: %x %x, Count: %x\n", pstr, cpuRegs.cycle, g_nextBranchCycle, cpuRegs.CP0.n.Count); + iDumpPsxRegisters(psxRegs.pc, temp); + + __Log("f410,30,40: %x %x %x, %d %d\n", psHu32(0xf410), psHu32(0xf430), psHu32(0xf440), rdram_sdevid, rdram_devices); + __Log("cyc11: %x %x; vu0: %x, vu1: %x\n", cpuRegs.sCycle[1], cpuRegs.eCycle[1], VU0.cycle, VU1.cycle); + + __Log("%scounters: %x %x; psx: %x %x\n", pstr, nextsCounter, nextCounter, psxNextsCounter, psxNextCounter); + for(i = 0; i < 4; ++i) { + __Log("eetimer%d: count: %x mode: %x target: %x %x; %x %x; %x %x %x %x\n", i, + counters[i].count, counters[i].mode, counters[i].target, counters[i].hold, counters[i].rate, + counters[i].interrupt, counters[i].Cycle, counters[i].sCycle, counters[i].CycleT, counters[i].sCycleT); + } + __Log("VIF0_STAT = %x, VIF1_STAT = %x\n", psHu32(0x3800), psHu32(0x3C00)); + __Log("ipu %x %x %x %x; bp: %x %x %x %x\n", psHu32(0x2000), psHu32(0x2010), psHu32(0x2020), psHu32(0x2030), g_BP.BP, g_BP.bufferhasnew, g_BP.FP, g_BP.IFC); + __Log("gif: %x %x %x\n", psHu32(0x3000), psHu32(0x3010), psHu32(0x3020)); + for(i = 0; i < ARRAYSIZE(dmacs); ++i) { + DMACh* p = (DMACh*)(PS2MEM_HW+dmacs[i]); + __Log("dma%d c%x m%x q%x t%x s%x\n", i, p->chcr, p->madr, p->qwc, p->tadr, p->sadr); + } + __Log("dmac %x %x %x %x\n", psHu32(DMAC_CTRL), psHu32(DMAC_STAT), psHu32(DMAC_RBSR), psHu32(DMAC_RBOR)); + __Log("intc %x %x\n", psHu32(INTC_STAT), psHu32(INTC_MASK)); + __Log("sif: %x %x %x %x %x\n", psHu32(0xf200), psHu32(0xf220), psHu32(0xf230), psHu32(0xf240), psHu32(0xf260)); +#endif +} + +} \ No newline at end of file diff --git a/pcsx2/x86/iCore.h b/pcsx2/x86/iCore.h index 1a0fdd34be..b0c6f00651 100644 --- a/pcsx2/x86/iCore.h +++ b/pcsx2/x86/iCore.h @@ -16,16 +16,18 @@ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA */ -// NOTE: x86-64 recompiler didn't support mmx #ifndef _PCSX2_CORE_RECOMPILER_ #define _PCSX2_CORE_RECOMPILER_ #include "ix86/ix86.h" #include "iVUmicro.h" -// xp64 had a stack shadow memory -#define REC_INC_STACK 0 +// Namespace Note : Dyanmic recompiler tools used by EE, IOP, and PS2 hardware. +// Underneath this namespace thenare Dynarec::R5900, Dynarec::R3000a, etc. for each +// of the items specific to those CPUs (those are defined in other headers). +namespace Dynarec +{ // used to keep block information #define BLOCKTYPE_STARTPC 4 // startpc offset #define BLOCKTYPE_DELAYSLOT 1 // if bit set, delay slot @@ -100,6 +102,9 @@ void _flushX86regs(); void _freeX86regs(); void _freeX86tempregs(); u8 _hasFreeX86reg(); +void _flushCachedRegs(); +void _flushConstRegs(); +void _flushConstReg(int reg); // see MEM_X defines for argX format extern void _callPushArg(u32 arg, uptr argmem); /// X86ARG is ignored for 32bit recs @@ -107,15 +112,6 @@ extern void _callFunctionArg1(uptr fn, u32 arg1, uptr arg1mem); extern void _callFunctionArg2(uptr fn, u32 arg1, u32 arg2, uptr arg1mem, uptr arg2mem); extern void _callFunctionArg3(uptr fn, u32 arg1, u32 arg2, u32 arg3, uptr arg1mem, uptr arg2mem, uptr arg3mem); - -// when using mmx/xmm regs, use; 0 is load -// freezes no matter the state -extern void FreezeXMMRegs_(int save); - -void _flushCachedRegs(); -void _flushConstRegs(); -void _flushConstReg(int reg); - // return type: 0 - const, 1 - mmx, 2 - xmm #define PROCESS_EE_MMX 0x01 #define PROCESS_EE_XMM 0x02 @@ -370,6 +366,9 @@ extern u32 g_cpuRegHasSignExt, g_cpuPrevRegHasSignExt; extern u8 g_globalXMMSaved; extern _xmmregs xmmregs[XMMREGS], s_saveXMMregs[XMMREGS]; +extern u16 g_x86AllocCounter; +extern u16 g_xmmAllocCounter; + #ifdef _DEBUG extern char g_globalXMMLocked; #endif @@ -403,14 +402,13 @@ void SetMMXstate(); void _recMove128MtoM(u32 to, u32 from); -///////////////////// -// MMX x86-32 only // -///////////////////// +///////////////////////////// +// MMX x86-32 only // +///////////////////////////// #define FPU_STATE 0 #define MMX_STATE 1 -extern void FreezeMMXRegs_(int save); void SetFPUstate(); // max is 0x7f, when 0x80 is set, need to flush reg @@ -468,7 +466,6 @@ void LogicalOpMtoR(x86MMXRegType to, u32 from, int op); // a negative shift is for sign extension int _signExtendGPRtoMMX(x86MMXRegType to, u32 gprreg, int shift); -extern u8 g_globalMMXSaved; extern _mmxregs mmxregs[MMXREGS], s_saveMMXregs[MMXREGS]; extern u16 x86FpuState, iCWstate; @@ -477,4 +474,13 @@ void LogicalOp32MtoR(x86IntRegType to, uptr from, int op); void LogicalOp32ItoR(x86IntRegType to, u32 from, int op); void LogicalOp32ItoM(uptr to, u32 from, int op); +#ifdef ARITHMETICIMM_RECOMPILE +extern void LogicalOpRtoR(x86MMXRegType to, x86MMXRegType from, int op); +extern void LogicalOpMtoR(x86MMXRegType to, u32 from, int op); +#endif + +void iDumpRegisters(u32 startpc, u32 temp); + +} + #endif diff --git a/pcsx2/x86/iFPU.cpp b/pcsx2/x86/iFPU.cpp index d7f9416456..53c1a1728e 100644 --- a/pcsx2/x86/iFPU.cpp +++ b/pcsx2/x86/iFPU.cpp @@ -24,13 +24,50 @@ #include "iR5900.h" #include "iFPU.h" -// Needed for gcc 4.3, due to header revisions. -// (really? that makes no sense... commented out, if they break something -// on gcc, re-add them.. if not, delete (air)) -//#include "stdio.h" -//#include "stdlib.h" -//------------------------------------------------------------------ +extern PCSX2_ALIGNED16_DECL(u32 g_minvals[4]); +extern PCSX2_ALIGNED16_DECL(u32 g_maxvals[4]); +//------------------------------------------------------------------ +// Misc... +//------------------------------------------------------------------ +//static u32 _mxcsr = 0x7F80; +//static u32 _mxcsrs; +static u32 fpucw = 0x007f; +static u32 fpucws = 0; + +//------------------------------------------------------------------ +namespace Dynarec { +namespace R5900 +{ + +void SaveCW(int type) { + if (iCWstate & type) return; + + if (type == 2) { +// SSE_STMXCSR((uptr)&_mxcsrs); +// SSE_LDMXCSR((uptr)&_mxcsr); + } else { + FNSTCW( (uptr)&fpucws ); + FLDCW( (uptr)&fpucw ); + } + iCWstate|= type; +} + +void LoadCW() { + if (iCWstate == 0) return; + + if (iCWstate & 2) { + //SSE_LDMXCSR((uptr)&_mxcsrs); + } + if (iCWstate & 1) { + FLDCW( (uptr)&fpucws ); + } + iCWstate = 0; +} + +//------------------------------------------------------------------ +namespace OpcodeImpl +{ //------------------------------------------------------------------ // Helper Macros @@ -52,9 +89,6 @@ #define FPU_ADD_SUB_HACK 1 // Add/Sub opcodes produce more ps2-like results if set to 1 -extern PCSX2_ALIGNED16_DECL(u32 g_minvals[4]); -extern PCSX2_ALIGNED16_DECL(u32 g_maxvals[4]); - static u32 PCSX2_ALIGNED16(s_neg[4]) = { 0x80000000, 0xffffffff, 0xffffffff, 0xffffffff }; static u32 PCSX2_ALIGNED16(s_pos[4]) = { 0x7fffffff, 0xffffffff, 0xffffffff, 0xffffffff }; @@ -78,55 +112,6 @@ static u32 PCSX2_ALIGNED16(s_pos[4]) = { 0x7fffffff, 0xffffffff, 0xffffffff, 0xf } //------------------------------------------------------------------ - -//------------------------------------------------------------------ -// Misc... -//------------------------------------------------------------------ -//static u32 _mxcsr = 0x7F80; -//static u32 _mxcsrs; -static u32 fpucw = 0x007f; -static u32 fpucws = 0; - -void recCOP1_BC1() -{ - recCP1BC1[_Rt_](); -} - -void SaveCW(int type) { - if (iCWstate & type) return; - - if (type == 2) { -// SSE_STMXCSR((uptr)&_mxcsrs); -// SSE_LDMXCSR((uptr)&_mxcsr); - } else { - FNSTCW( (uptr)&fpucws ); - FLDCW( (uptr)&fpucw ); - } - iCWstate|= type; -} - -void LoadCW( void ) { - if (iCWstate == 0) return; - - if (iCWstate & 2) { - //SSE_LDMXCSR((uptr)&_mxcsrs); - } - if (iCWstate & 1) { - FLDCW( (uptr)&fpucws ); - } - iCWstate = 0; -} - -void recCOP1_S( void ) { - recCP1S[ _Funct_ ]( ); -} - -void recCOP1_W( void ) { - recCP1W[ _Funct_ ]( ); -} -//------------------------------------------------------------------ - - //------------------------------------------------------------------ // *FPU Opcodes!* //------------------------------------------------------------------ @@ -1776,3 +1761,5 @@ void recRSQRT_S_xmm(int info) FPURECOMPILE_CONSTCODE(RSQRT_S, XMMINFO_WRITED|XMMINFO_READS|XMMINFO_READT); #endif // FPU_RECOMPILE + +}}} \ No newline at end of file diff --git a/pcsx2/x86/iFPU.h b/pcsx2/x86/iFPU.h index 54ef19dc2c..f30cf8a1f5 100644 --- a/pcsx2/x86/iFPU.h +++ b/pcsx2/x86/iFPU.h @@ -19,41 +19,54 @@ #ifndef __IFPU_H__ #define __IFPU_H__ -void recMFC1( void ); -void recCFC1( void ); -void recMTC1( void ); -void recCTC1( void ); -void recCOP1_BC1( void ); -void recCOP1_S( void ); -void recCOP1_W( void ); -void recC_EQ( void ); -void recC_F( void ); -void recC_LT( void ); -void recC_LE( void ); -void recADD_S( void ); -void recSUB_S( void ); -void recMUL_S( void ); -void recDIV_S( void ); -void recSQRT_S( void ); -void recABS_S( void ); -void recMOV_S( void ); -void recNEG_S( void ); -void recRSQRT_S( void ); -void recADDA_S( void ); -void recSUBA_S( void ); -void recMULA_S( void ); -void recMADD_S( void ); -void recMSUB_S( void ); -void recMADDA_S( void ); -void recMSUBA_S( void ); -void recCVT_S( void ); -void recCVT_W( void ); -void recMAX_S( void ); -void recMIN_S( void ); -void recBC1F( void ); -void recBC1T( void ); -void recBC1FL( void ); -void recBC1TL( void ); +namespace Dynarec { +namespace R5900 +{ + + void SaveCW(); + void LoadCW(); + + namespace OpcodeImpl + { + void recCOP1_Unknown(); + + void recMFC1( void ); + void recCFC1( void ); + void recMTC1( void ); + void recCTC1( void ); + void recCOP1_BC1( void ); + void recCOP1_S( void ); + void recCOP1_W( void ); + void recC_EQ( void ); + void recC_F( void ); + void recC_LT( void ); + void recC_LE( void ); + void recADD_S( void ); + void recSUB_S( void ); + void recMUL_S( void ); + void recDIV_S( void ); + void recSQRT_S( void ); + void recABS_S( void ); + void recMOV_S( void ); + void recNEG_S( void ); + void recRSQRT_S( void ); + void recADDA_S( void ); + void recSUBA_S( void ); + void recMULA_S( void ); + void recMADD_S( void ); + void recMSUB_S( void ); + void recMADDA_S( void ); + void recMSUBA_S( void ); + void recCVT_S( void ); + void recCVT_W( void ); + void recMAX_S( void ); + void recMIN_S( void ); + void recBC1F( void ); + void recBC1T( void ); + void recBC1FL( void ); + void recBC1TL( void ); + } +} } #endif diff --git a/pcsx2/x86/iGS.cpp b/pcsx2/x86/iGS.cpp index 880f96990b..7685966b30 100644 --- a/pcsx2/x86/iGS.cpp +++ b/pcsx2/x86/iGS.cpp @@ -34,6 +34,10 @@ extern u8 g_RealGSMem[0x2000]; #define PS2GS_BASE(mem) (g_RealGSMem+(mem&0x13ff)) #endif +namespace Dynarec { + +using namespace R5900; + // __thiscall -- Calling Convention Notes. // ** MSVC passes the pointer to the object as ECX. Other parameters are passed normally @@ -301,3 +305,5 @@ void gsConstRead128(u32 mem, int xmmreg) GIF_LOG("GS read 128 %8.8lx (%8.8x), at %8.8lx\n", (uptr)PS2GS_BASE(mem), mem); _eeReadConstMem128( xmmreg, (uptr)PS2GS_BASE(mem)); } + +} // end namespace Dynarec \ No newline at end of file diff --git a/pcsx2/x86/iHw.cpp b/pcsx2/x86/iHw.cpp index 5dac1c31e3..2f6ac6eac6 100644 --- a/pcsx2/x86/iHw.cpp +++ b/pcsx2/x86/iHw.cpp @@ -37,6 +37,9 @@ extern int rdram_sdevid; extern char sio_buffer[1024]; extern int sio_count; +using namespace Dynarec; +using namespace Dynarec::R5900; + int hwConstRead8(u32 x86reg, u32 mem, u32 sign) { if( mem >= 0x10000000 && mem < 0x10008000 ) diff --git a/pcsx2/x86/iMMI.cpp b/pcsx2/x86/iMMI.cpp index 5f532e301a..25a479339b 100644 --- a/pcsx2/x86/iMMI.cpp +++ b/pcsx2/x86/iMMI.cpp @@ -29,7 +29,9 @@ #include "iR5900.h" #include "iMMI.h" -namespace EE { namespace Dynarec { namespace OpcodeImpl +namespace Dynarec { +namespace R5900 { +namespace OpcodeImpl { #ifndef MMI_RECOMPILE @@ -247,7 +249,7 @@ CPU_SSE2_XMMCACHE_START(XMMINFO_WRITED|XMMINFO_READLO|XMMINFO_READHI) _deleteEEreg(XMMGPR_LO, 1); _deleteEEreg(XMMGPR_HI, 1); iFlushCall(FLUSH_CACHED_REGS); // since calling CALLFunc - CALLFunc( (uptr)Interpreter::OpcodeImpl::PMFHL ); + CALLFunc( (uptr)R5900::Interpreter::OpcodeImpl::PMFHL ); break; case 0x03: // LH @@ -543,42 +545,6 @@ void recPLZCW( void ) } */ -#ifdef MMI0_RECOMPILE - -void recMMI0( void ) -{ - EE::OpcodeTables::MMI0[ _Sa_ ].recompile( ); -} - -#endif - -#ifdef MMI1_RECOMPILE - -void recMMI1( void ) -{ - EE::OpcodeTables::MMI1[ _Sa_ ].recompile( ); -} - -#endif - -#ifdef MMI2_RECOMPILE - -void recMMI2( void ) -{ - EE::OpcodeTables::MMI2[ _Sa_ ].recompile( ); -} - -#endif - -#ifdef MMI3_RECOMPILE - -void recMMI3( void ) -{ - EE::OpcodeTables::MMI3[ _Sa_ ].recompile( ); -} - -#endif - #endif /********************************************************* @@ -1026,7 +992,7 @@ void recPADDSW( void ) MOV32ItoM( (uptr)&cpuRegs.code, cpuRegs.code ); MOV32ItoM( (uptr)&cpuRegs.pc, pc ); - CALLFunc( (uptr)Interpreter::OpcodeImpl::PADDSW ); + CALLFunc( (uptr)R5900::Interpreter::OpcodeImpl::PADDSW ); } //////////////////////////////////////////////////// @@ -1117,7 +1083,7 @@ void recPSUBSW( void ) MOV32ItoM( (uptr)&cpuRegs.code, cpuRegs.code ); MOV32ItoM( (uptr)&cpuRegs.pc, pc ); - CALLFunc( (uptr)Interpreter::OpcodeImpl::PSUBSW ); + CALLFunc( (uptr)R5900::Interpreter::OpcodeImpl::PSUBSW ); } //////////////////////////////////////////////////// @@ -1545,7 +1511,7 @@ CPU_SSE_XMMCACHE_END MOV32ItoM( (uptr)&cpuRegs.code, cpuRegs.code ); MOV32ItoM( (uptr)&cpuRegs.pc, pc ); - CALLFunc( (uptr)Interpreter::OpcodeImpl::PABSW ); + CALLFunc( (uptr)R5900::Interpreter::OpcodeImpl::PABSW ); } //////////////////////////////////////////////////// @@ -1569,7 +1535,7 @@ CPU_SSE_XMMCACHE_END MOV32ItoM( (uptr)&cpuRegs.code, cpuRegs.code ); MOV32ItoM( (uptr)&cpuRegs.pc, pc ); - CALLFunc( (uptr)Interpreter::OpcodeImpl::PABSW ); + CALLFunc( (uptr)R5900::Interpreter::OpcodeImpl::PABSW ); } //////////////////////////////////////////////////// @@ -2907,7 +2873,7 @@ void recPSRAVW( void ) MOV32ItoM( (uptr)&cpuRegs.pc, (u32)pc ); iFlushCall(FLUSH_EVERYTHING); if( _Rd_ > 0 ) _deleteEEreg(_Rd_, 0); - CALLFunc( (uptr)Interpreter::OpcodeImpl::PSRAVW ); + CALLFunc( (uptr)R5900::Interpreter::OpcodeImpl::PSRAVW ); } diff --git a/pcsx2/x86/iMMI.h b/pcsx2/x86/iMMI.h index 76e597831f..f2aa2f5e11 100644 --- a/pcsx2/x86/iMMI.h +++ b/pcsx2/x86/iMMI.h @@ -24,8 +24,12 @@ #ifndef __IMMI_H__ #define __IMMI_H__ -namespace EE { namespace Dynarec { namespace OpcodeImpl +namespace Dynarec { +namespace R5900 { +namespace OpcodeImpl { + void recMMI_Unknown(); + void recMADD(); void recMADDU(); void recPLZCW(); @@ -135,4 +139,3 @@ namespace EE { namespace Dynarec { namespace OpcodeImpl #endif - diff --git a/pcsx2/x86/iPsxHw.cpp b/pcsx2/x86/iPsxHw.cpp index f84bf4b73c..eebe8bdc27 100644 --- a/pcsx2/x86/iPsxHw.cpp +++ b/pcsx2/x86/iPsxHw.cpp @@ -21,9 +21,17 @@ #include "PsxCommon.h" #include "iR5900.h" +// iPsxHw uses the R5900 flushcall because this module can be called from both +// the EE and the IOP -- R5900's iFlushCall is compatible with iPsxFlushcall, but +// iPsxFlushCall does not flush all the regtypes that iFlushCall does. +using ::Dynarec::R5900::iFlushCall; + extern int g_pbufi; extern s8 g_pbuf[1024]; +namespace Dynarec +{ + #define CONSTREAD8_CALL(name) { \ iFlushCall(0); \ CALLFunc((uptr)name); \ @@ -1178,3 +1186,4 @@ void psxHw4ConstWrite8(u32 add, int mmreg) { } } +} // end namespace Dynarec diff --git a/pcsx2/x86/iPsxMem.cpp b/pcsx2/x86/iPsxMem.cpp index b4e208ab0c..4a705a1e24 100644 --- a/pcsx2/x86/iPsxMem.cpp +++ b/pcsx2/x86/iPsxMem.cpp @@ -23,8 +23,12 @@ #include "iCore.h" #include "iR3000A.h" -extern u32 g_psxMaxRecMem; extern int g_psxWriteOk; + +namespace Dynarec +{ + +extern u32 g_psxMaxRecMem; static u32 writectrl; #ifdef PCSX2_VIRTUAL_MEM @@ -869,3 +873,4 @@ int psxRecMemConstWrite32(u32 mem, int mmreg) } #endif +} diff --git a/pcsx2/x86/iR3000A.cpp b/pcsx2/x86/iR3000A.cpp index bf716fc070..c5ef253406 100644 --- a/pcsx2/x86/iR3000A.cpp +++ b/pcsx2/x86/iR3000A.cpp @@ -42,10 +42,16 @@ #include "SamplProf.h" -u32 g_psxMaxRecMem = 0; -extern const char *disRNameGPR[]; +using namespace R3000a; extern char* disR3000Fasm(u32 code, u32 pc); +extern u32 g_psxNextBranchCycle; +extern void psxBREAK(); + +namespace Dynarec +{ + +u32 g_psxMaxRecMem = 0; u32 s_psxrecblocks[] = {0}; //Using assembly code from an external file. @@ -689,7 +695,6 @@ static __forceinline void R3000AExecute() } } -extern u32 g_psxNextBranchCycle; u32 g_psxlastpc = 0; #if defined(_MSC_VER) @@ -1006,8 +1011,6 @@ static void iPsxBranchTest(u32 newpc, u32 cpuBranch) j8Ptr[2] = JG8( 0 ); // jump if psxCycleEE > 0 - if( REC_INC_STACK ) - ADD64ItoR(ESP, REC_INC_STACK); RET2(); // returns control to the EE // Continue onward with branching here: @@ -1066,7 +1069,6 @@ void rpsxSYSCALL() //if (!psxbranch) psxbranch = 2; } -void psxBREAK(); void rpsxBREAK() { MOV32ItoM( (uptr)&psxRegs.code, psxRegs.code ); @@ -1554,6 +1556,9 @@ StartRecomp: assert( s_pCurBlock->pFnptr != 0 ); } +} + +using namespace Dynarec; R3000Acpu psxRec = { recInit, recReset, diff --git a/pcsx2/x86/iR3000A.h b/pcsx2/x86/iR3000A.h index ced713bc36..329b1bcb71 100644 --- a/pcsx2/x86/iR3000A.h +++ b/pcsx2/x86/iR3000A.h @@ -29,7 +29,8 @@ static const int psxInstCycles_Peephole_Store = 0; static const int psxInstCycles_Store = 0; static const int psxInstCycles_Load = 0; - +namespace Dynarec +{ // to be consistent with EE #define PSX_HI XMMGPR_HI #define PSX_LO XMMGPR_LO @@ -114,4 +115,6 @@ void psxRecompileCodeConst2(R3000AFNPTR constcode, R3000AFNPTR_INFO noconstcode) // [lo,hi] = rt op rs void psxRecompileCodeConst3(R3000AFNPTR constcode, R3000AFNPTR_INFO constscode, R3000AFNPTR_INFO consttcode, R3000AFNPTR_INFO noconstcode, int LOHI); +} // end namespace Dynarec + #endif diff --git a/pcsx2/x86/iR3000Atables.cpp b/pcsx2/x86/iR3000Atables.cpp index d733662aa5..d17b10953b 100644 --- a/pcsx2/x86/iR3000Atables.cpp +++ b/pcsx2/x86/iR3000Atables.cpp @@ -32,11 +32,14 @@ extern void psxSWL(); extern void psxSWR(); extern int g_psxWriteOk; + +namespace Dynarec +{ + extern u32 g_psxMaxRecMem; // R3000A instruction implementation #define REC_FUNC(f) \ -void psx##f(); \ static void rpsx##f() { \ MOV32ItoM((uptr)&psxRegs.code, (u32)psxRegs.code); \ _psxFlushCall(FLUSH_EVERYTHING); \ @@ -2004,9 +2007,7 @@ void rpsxpropREGIMM(EEINST* prev, EEINST* pinst) rpsxpropSetRead(_Rs_); break; - default: - assert(0); - break; + jNO_DEFAULT } } @@ -2028,7 +2029,9 @@ void rpsxpropCP0(EEINST* prev, EEINST* pinst) break; case 16: // rfe break; - default: - assert(0); + + jNO_DEFAULT } } + +} \ No newline at end of file diff --git a/pcsx2/x86/iR5900.h b/pcsx2/x86/iR5900.h index aaecdcdd18..e98849199f 100644 --- a/pcsx2/x86/iR5900.h +++ b/pcsx2/x86/iR5900.h @@ -19,6 +19,7 @@ #ifndef __IR5900_H__ #define __IR5900_H__ +#include "R5900.h" #include "VU.h" #include "iCore.h" @@ -41,18 +42,14 @@ #define CP2_RECOMPILE #define EE_CONST_PROP // rec2 - enables constant propagation (faster) -//#define EE_FPU_REGCACHING 1 // Not used anymore, its always on! + +namespace Dynarec { +namespace R5900 { + +using namespace ::R5900; // This makes sure the Dynarec inherits all R5900 globals. #define PC_GETBLOCK(x) PC_GETBLOCK_(x, recLUT) -void recClearMem(BASEBLOCK* p); -#define REC_CLEARM(mem) { \ - if ((mem) < maxrecmem && recLUT[(mem) >> 16]) { \ - BASEBLOCK* p = PC_GETBLOCK(mem); \ - if( *(u32*)p ) recClearMem(p); \ - } \ -} \ - extern u32 pc; extern int branch; extern uptr* recLUT; @@ -61,39 +58,41 @@ extern u32 maxrecmem; extern u32 pc; // recompiler pc extern int branch; // set for branch extern u32 target; // branch target -extern u16 x86FpuState; -extern u16 iCWstate; extern u32 s_nBlockCycles; // cycles of current block recompiling +extern u32 s_saveConstGPRreg; +extern GPR_reg64 s_ConstGPRreg; #define REC_FUNC_INLINE( f, delreg ) \ MOV32ItoM( (uptr)&cpuRegs.code, (u32)cpuRegs.code ); \ MOV32ItoM( (uptr)&cpuRegs.pc, (u32)pc ); \ iFlushCall(FLUSH_EVERYTHING); \ if( (delreg) > 0 ) _deleteEEreg(delreg, 0); \ - CALLFunc( (uptr)EE::Interpreter::OpcodeImpl::f ); + CALLFunc( (uptr)R5900::Interpreter::OpcodeImpl::f ); #define REC_FUNC( f, delreg ) \ - void f( void ); \ void rec##f( void ) \ { \ MOV32ItoM( (uptr)&cpuRegs.code, (u32)cpuRegs.code ); \ MOV32ItoM( (uptr)&cpuRegs.pc, (u32)pc ); \ iFlushCall(FLUSH_EVERYTHING); \ if( (delreg) > 0 ) _deleteEEreg(delreg, 0); \ - CALLFunc( (uptr)Interpreter::OpcodeImpl::f ); \ + CALLFunc( (uptr)R5900::Interpreter::OpcodeImpl::f ); \ } #define REC_SYS( f ) \ - void f( void ); \ void rec##f( void ) \ { \ MOV32ItoM( (uptr)&cpuRegs.code, (u32)cpuRegs.code ); \ MOV32ItoM( (uptr)&cpuRegs.pc, (u32)pc ); \ iFlushCall(FLUSH_EVERYTHING); \ - CALLFunc( (uptr)f ); \ + CALLFunc( (uptr)R5900::Interpreter::OpcodeImpl::f ); \ branch = 2; \ } +// Used to clear recompiled code blocks during memory/dma write operations. +void recClearMem(BASEBLOCK* p); +void REC_CLEARM( u32 mem ); + // used when processing branches void SaveBranchState(); void LoadBranchState(); @@ -103,29 +102,19 @@ void SetBranchReg( u32 reg ); void SetBranchImm( u32 imm ); void iFlushCall(int flushtype); -void SaveCW(); -void LoadCW(); -extern void (*recCP0[32])(); -extern void (*recCP0BC0[32])(); -extern void (*recCP0C0[64])(); -extern void (*recCP1[32])(); -extern void (*recCP1BC1[32])(); -extern void (*recCP1S[64])(); -extern void (*recCP1W[64])(); - -namespace EE { namespace Dynarec { - - extern void (*recBSC_co[64])(); - void recBranchCall( void (*func)() ); - -} } +extern void (*recBSC_co[64])(); +void recBranchCall( void (*func)() ); u32* _eeGetConstReg(int reg); // gets a memory pointer to the constant reg void _eeFlushAllUnused(); void _eeOnWriteReg(int reg, int signext); +// these are defined in iFPU.cpp +void LoadCW(); +void SaveCW(int type); + // totally deletes from const, xmm, and mmx entries // if flush is 1, also flushes to memory // if 0, only flushes if not an xmm reg (used when overwriting lower 64bits of reg) @@ -234,7 +223,7 @@ void eeRecompileCodeConstSPECIAL(R5900FNPTR constcode, R5900FNPTR_INFO multicode #define FPURECOMPILE_CONSTCODE(fn, xmminfo) \ void rec##fn(void) \ { \ - eeFPURecompileCode(rec##fn##_xmm, fn, xmminfo); \ + eeFPURecompileCode(rec##fn##_xmm, R5900::Interpreter::OpcodeImpl::fn, xmminfo); \ } // rd = rs op rt (all regs need to be in xmm) @@ -288,13 +277,6 @@ protected: }; -// perf counters -#ifdef PCSX2_DEVBUILD -extern void StartPerfCounter(); -extern void StopPerfCounter(); -#else -#define StartPerfCounter() -#define StopPerfCounter() -#endif +} } #endif // __IR5900_H__ diff --git a/pcsx2/x86/iR5900Arit.h b/pcsx2/x86/iR5900Arit.h index fa205ec979..9fde668e3d 100644 --- a/pcsx2/x86/iR5900Arit.h +++ b/pcsx2/x86/iR5900Arit.h @@ -24,7 +24,9 @@ * Format: OP rd, rs, rt * *********************************************************/ -namespace EE { namespace Dynarec { namespace OpcodeImpl +namespace Dynarec { +namespace R5900 { +namespace OpcodeImpl { void recADD( void ); void recADDU( void ); diff --git a/pcsx2/x86/iR5900AritImm.h b/pcsx2/x86/iR5900AritImm.h index 78a6d2ae4c..bf5b066f20 100644 --- a/pcsx2/x86/iR5900AritImm.h +++ b/pcsx2/x86/iR5900AritImm.h @@ -23,7 +23,9 @@ * Arithmetic with immediate operand * * Format: OP rt, rs, immediate * *********************************************************/ -namespace EE { namespace Dynarec { namespace OpcodeImpl +namespace Dynarec { +namespace R5900 { +namespace OpcodeImpl { void recADDI( void ); void recADDIU( void ); diff --git a/pcsx2/x86/iR5900Branch.h b/pcsx2/x86/iR5900Branch.h index 317e448fd5..8ade69c19a 100644 --- a/pcsx2/x86/iR5900Branch.h +++ b/pcsx2/x86/iR5900Branch.h @@ -24,7 +24,9 @@ * Format: OP rd, rt, sa * *********************************************************/ -namespace EE { namespace Dynarec { namespace OpcodeImpl +namespace Dynarec { +namespace R5900 { +namespace OpcodeImpl { void recBEQ( void ); void recBEQL( void ); diff --git a/pcsx2/x86/iR5900Jump.h b/pcsx2/x86/iR5900Jump.h index 3c010327d7..d0dece07dd 100644 --- a/pcsx2/x86/iR5900Jump.h +++ b/pcsx2/x86/iR5900Jump.h @@ -24,7 +24,9 @@ * Format: OP target * *********************************************************/ -namespace EE { namespace Dynarec { namespace OpcodeImpl +namespace Dynarec { +namespace R5900 { +namespace OpcodeImpl { void recJ( void ); void recJAL( void ); diff --git a/pcsx2/x86/iR5900LoadStore.h b/pcsx2/x86/iR5900LoadStore.h index e35ca4c993..d6c0228900 100644 --- a/pcsx2/x86/iR5900LoadStore.h +++ b/pcsx2/x86/iR5900LoadStore.h @@ -23,7 +23,9 @@ * Format: OP rt, offset(base) * *********************************************************/ -namespace EE { namespace Dynarec { namespace OpcodeImpl +namespace Dynarec { +namespace R5900 { +namespace OpcodeImpl { void recLB( void ); void recLBU( void ); @@ -52,7 +54,7 @@ namespace EE { namespace Dynarec { namespace OpcodeImpl void recSQC2( void ); // coissues - #ifdef PCSX2_VIRTUAL_MEM +#ifdef PCSX2_VIRTUAL_MEM void recLB_co( void ); void recLBU_co( void ); void recLH_co( void ); diff --git a/pcsx2/x86/iR5900Move.h b/pcsx2/x86/iR5900Move.h index 95022242ec..d5923d1dbd 100644 --- a/pcsx2/x86/iR5900Move.h +++ b/pcsx2/x86/iR5900Move.h @@ -19,7 +19,9 @@ #ifndef __IR5900MOVE_H__ #define __IR5900MOVE_H__ -namespace EE { namespace Dynarec { namespace OpcodeImpl +namespace Dynarec { +namespace R5900 { +namespace OpcodeImpl { void recLUI( void ); void recMFLO( void ); diff --git a/pcsx2/x86/iR5900MultDiv.h b/pcsx2/x86/iR5900MultDiv.h index 551d8c3367..ae417ecdc7 100644 --- a/pcsx2/x86/iR5900MultDiv.h +++ b/pcsx2/x86/iR5900MultDiv.h @@ -24,7 +24,9 @@ * Format: OP rs, rt * *********************************************************/ -namespace EE { namespace Dynarec { namespace OpcodeImpl +namespace Dynarec { +namespace R5900 { +namespace OpcodeImpl { void recMULT( void ); void recMULTU( void ); diff --git a/pcsx2/x86/iR5900Shift.h b/pcsx2/x86/iR5900Shift.h index bd5a709d08..ef3c86c865 100644 --- a/pcsx2/x86/iR5900Shift.h +++ b/pcsx2/x86/iR5900Shift.h @@ -24,7 +24,9 @@ * Format: OP rd, rt, sa * *********************************************************/ -namespace EE { namespace Dynarec { namespace OpcodeImpl +namespace Dynarec { +namespace R5900 { +namespace OpcodeImpl { void recSLL( void ); void recSRL( void ); diff --git a/pcsx2/x86/iVU0micro.cpp b/pcsx2/x86/iVU0micro.cpp index 55ff61ee9f..3ea71a8268 100644 --- a/pcsx2/x86/iVU0micro.cpp +++ b/pcsx2/x86/iVU0micro.cpp @@ -37,7 +37,9 @@ #pragma warning(disable:4761) #endif -static VURegs * const VU = (VURegs*)&VU0; +namespace Dynarec +{ + #ifdef _DEBUG extern u32 vudump; #endif @@ -61,7 +63,7 @@ void recExecuteVU0Block( void ) SuperVUExecuteProgram(VU0.VI[ REG_TPC ].UL & 0xfff, 0); FreezeXMMRegs(0); } - else intExecuteVU0Block(); + else ::R5900::Interpreter::intExecuteVU0Block(); //} } @@ -72,3 +74,9 @@ void recClearVU0( u32 Addr, u32 Size ) } } +void recResetVU0( void ) +{ + SuperVUReset(0); +} + +} diff --git a/pcsx2/x86/iVU1micro.cpp b/pcsx2/x86/iVU1micro.cpp index 17cf4d1527..f6f3bd118a 100644 --- a/pcsx2/x86/iVU1micro.cpp +++ b/pcsx2/x86/iVU1micro.cpp @@ -29,7 +29,7 @@ #include "iCP0.h" #include "VU.h" #include "VUmicro.h" -#include "iVUmicro.h" +#include "iVUzerorec.h" #include "iVUops.h" #include "VUops.h" @@ -40,6 +40,14 @@ #pragma warning(disable:4761) #endif +// fixme - having the VUs share the branch/pc values of the R5900 is bad on so many levels... >_< (air) + +using ::Dynarec::R5900::pc; +using ::Dynarec::R5900::branch; + +namespace Dynarec +{ + #define VU ((VURegs*)&VU1) //Lower/Upper instructions can use that.. @@ -73,11 +81,6 @@ #define VU1_ACCz_ADDR (uptr)&VU1.ACC.UL[2] #define VU1_ACCw_ADDR (uptr)&VU1.ACC.UL[3] -extern void SuperVUInit(int vuindex); -extern void SuperVUDestroy(int vuindex); -extern void SuperVUReset(int vuindex); -extern void SuperVUExecuteProgram(u32 startpc, int vuindex); -extern void SuperVUClear(u32 startpc, u32 size, int vuindex); void recVU1Init() { @@ -169,7 +172,7 @@ void recExecuteVU1Block(void) } #endif while (VU0.VI[ REG_VPU_STAT ].UL&0x100) { - intExecuteVU1Block(); + ::R5900::Interpreter::intExecuteVU1Block(); } } } @@ -178,3 +181,4 @@ void recClearVU1( u32 Addr, u32 Size ) { assert( (Addr&7) == 0 ); if( CHECK_VU1REC ) SuperVUClear(Addr, Size*4, 1); } +} diff --git a/pcsx2/x86/iVUmicro.cpp b/pcsx2/x86/iVUmicro.cpp index f202f87d7f..4f491aef41 100644 --- a/pcsx2/x86/iVUmicro.cpp +++ b/pcsx2/x86/iVUmicro.cpp @@ -38,6 +38,10 @@ #endif //------------------------------------------------------------------ +namespace Dynarec +{ + using ::Dynarec::R5900::pc; + using ::Dynarec::R5900::branch; //------------------------------------------------------------------ // Helper Macros @@ -1269,3 +1273,4 @@ void SetVUNanMode(int mode) if ( mode ) SysPrintf("enabling vunan mode"); } +} \ No newline at end of file diff --git a/pcsx2/x86/iVUmicro.h b/pcsx2/x86/iVUmicro.h index 6172304b73..a09e4fe45a 100644 --- a/pcsx2/x86/iVUmicro.h +++ b/pcsx2/x86/iVUmicro.h @@ -19,6 +19,9 @@ #ifndef __IVUMICRO_H__ #define __IVUMICRO_H__ +namespace Dynarec +{ + #define VU0_MEMSIZE 0x1000 #define VU1_MEMSIZE 0x4000 @@ -279,4 +282,6 @@ void recVUMI_XTOP(VURegs *vuRegs, int info); void recVUMI_XITOP(VURegs *vuRegs, int info); void recVUMI_XTOP( VURegs *VU , int info); +} // end namespace Dynarec + #endif /* __IVUMICRO_H__ */ diff --git a/pcsx2/x86/iVUmicroLower.cpp b/pcsx2/x86/iVUmicroLower.cpp index 3145b33bd7..585c5618de 100644 --- a/pcsx2/x86/iVUmicroLower.cpp +++ b/pcsx2/x86/iVUmicroLower.cpp @@ -33,6 +33,8 @@ #include "iVUzerorec.h" //------------------------------------------------------------------ +namespace Dynarec +{ //------------------------------------------------------------------ // Helper Macros @@ -2036,3 +2038,5 @@ void VU1XGKICK_MTGSTransfer(u32 *pMem, u32 addr) } } //------------------------------------------------------------------ + +} // end namespace Dynarec diff --git a/pcsx2/x86/iVUmicroUpper.cpp b/pcsx2/x86/iVUmicroUpper.cpp index 1205d28016..f3efcb6fd1 100644 --- a/pcsx2/x86/iVUmicroUpper.cpp +++ b/pcsx2/x86/iVUmicroUpper.cpp @@ -33,6 +33,8 @@ #include "iVUzerorec.h" //------------------------------------------------------------------ +namespace Dynarec +{ //------------------------------------------------------------------ // Helper Macros @@ -2534,4 +2536,6 @@ void recVUMI_CLIP(VURegs *VU, int info) _freeX86reg(x86temp1); _freeX86reg(x86temp2); -} \ No newline at end of file +} + +} // end namespace Dynarec \ No newline at end of file diff --git a/pcsx2/x86/iVUzerorec.cpp b/pcsx2/x86/iVUzerorec.cpp index a644d2c8ff..40b159b2de 100644 --- a/pcsx2/x86/iVUzerorec.cpp +++ b/pcsx2/x86/iVUzerorec.cpp @@ -21,6 +21,10 @@ #include "PrecompiledHeader.h" #include +#include +#include +#include +#include #ifndef _WIN32 #include @@ -37,30 +41,24 @@ #include "iVUzerorec.h" #include "SamplProf.h" -// temporary externs -extern u32 vudump; -extern void iDumpVU0Registers(); -extern void iDumpVU1Registers(); - -extern char* disVU1MicroUF(u32 code, u32 pc); -extern char* disVU1MicroLF(u32 code, u32 pc); - -#ifdef __LINUX__ -#undef max -#undef min -#endif - -#include -#include -#include -#include -using namespace std; - #ifdef _WIN32 #pragma warning(disable:4244) #pragma warning(disable:4761) #endif +using namespace std; + +using namespace R5900; +using namespace Dynarec::R5900; + +namespace Dynarec +{ + +// temporary externs +extern u32 vudump; +extern void iDumpVU0Registers(); +extern void iDumpVU1Registers(); + // SuperVURec optimization options, uncomment only for debugging purposes #define SUPERVU_CACHING // vu programs are saved and queried via memcompare (should be no reason to disable this) #define SUPERVU_WRITEBACKS // don't flush the writebacks after every block @@ -94,7 +92,7 @@ static u32 s_vuInfo; // info passed into rec insts static const u32 s_MemSize[2] = {VU0_MEMSIZE, VU1_MEMSIZE}; static u8* s_recVUMem = NULL, *s_recVUPtr = NULL; -// tables +// tables which are defined at the bottom of this massive file. extern void (*recVU_UPPER_OPCODE[64])( VURegs* VU, s32 info ); extern void (*recVU_LOWER_OPCODE[128])( VURegs* VU, s32 info ); @@ -2263,8 +2261,6 @@ static int s_needFlush; // first bit - Q, second bit - P, third bit - Q has been static int s_JumpX86; static int s_ScheduleXGKICK = 0, s_XGKICKReg = -1; -extern u32 g_sseVUMXCSR, g_sseMXCSR; - void recVUMI_XGKICK_( VURegs *VU ); void SuperVUCleanupProgram(u32 startpc, int vuindex) @@ -4138,3 +4134,5 @@ void recVUunknown( VURegs* VU, s32 info ) { SysPrintf("Unknown SVU micromode opcode called\n"); } + +} \ No newline at end of file diff --git a/pcsx2/x86/iVUzerorec.h b/pcsx2/x86/iVUzerorec.h index f65b9187c1..60cdd5ae1b 100644 --- a/pcsx2/x86/iVUzerorec.h +++ b/pcsx2/x86/iVUzerorec.h @@ -23,9 +23,11 @@ #include "iVUmicro.h" -void SuperVUInit(int vuindex); // if vuindex is -1, inits the global VU resources -void SuperVUDestroy(int vuindex); // if vuindex is -1, destroys everything -void SuperVUReset(int vuindex); // if vuindex is -1, resets everything +namespace Dynarec +{ +extern void SuperVUInit(int vuindex); // if vuindex is -1, inits the global VU resources +extern void SuperVUDestroy(int vuindex); // if vuindex is -1, destroys everything +extern void SuperVUReset(int vuindex); // if vuindex is -1, resets everything //Using assembly code from an external file. #ifdef __LINUX__ @@ -47,7 +49,6 @@ u32 SuperVUGetVIAddr(int reg, int read); // if p == 0, flush q else flush p; if wait is != 0, waits for p/q void SuperVUFlush(int p, int wait); -// These are for recCode called from iVUmicroLower: - +} #endif diff --git a/pcsx2/x86/ir5900tables.cpp b/pcsx2/x86/ir5900tables.cpp index e1abcea1f9..2a6a851900 100644 --- a/pcsx2/x86/ir5900tables.cpp +++ b/pcsx2/x86/ir5900tables.cpp @@ -37,13 +37,8 @@ #include "iFPU.h" #include "iCP0.h" -//////////////////////////////////////////////////// -void recNULL( void ) -{ - Console::Error("EE: Unimplemented op %x", params cpuRegs.code); -} - -namespace EE { namespace Dynarec +namespace Dynarec { +namespace R5900 { // Use this to call into interpreter functions that require an immediate branchtest // to be done afterward (anything that throws an exception or enables interrupts, etc). @@ -66,6 +61,12 @@ namespace EE { namespace Dynarec namespace OpcodeImpl { + //////////////////////////////////////////////////// + void recNULL( void ) + { + Console::Error("EE: Unimplemented op %x", params cpuRegs.code); + } + //////////////////////////////////////////////////// void recUnknown() { @@ -79,34 +80,16 @@ namespace OpcodeImpl Console::Error("EE: Unrecognized MMI op %x", params cpuRegs.code); } - //////////////////////////////////////////////////// - void recREGIMM( void ) + void recCOP0_Unknown() { - EE::OpcodeTables::RegImm[ _Rt_ ].recompile(); + // TODO : Unknown ops should throw an exception. + Console::Error("EE: Unrecognized COP0 op %x", params cpuRegs.code); } - //////////////////////////////////////////////////// - void recSPECIAL( void ) + void recCOP1_Unknown() { - EE::OpcodeTables::Special[ _Funct_ ].recompile( ); - } - - //////////////////////////////////////////////////// - void recCOP0( void ) - { - recCP0[ _Rs_ ]( ); - } - - //////////////////////////////////////////////////// - void recCOP1( void ) - { - recCP1[ _Rs_ ]( ); - } - - //////////////////////////////////////////////////// - void recMMI( void ) - { - EE::OpcodeTables::MMI[ _Funct_ ].recompile( ); + // TODO : Unknown ops should throw an exception. + Console::Error("EE: Unrecognized FPU/COP1 op %x", params cpuRegs.code); } /********************************************************** @@ -156,68 +139,68 @@ namespace OpcodeImpl MOV32ItoM( (uptr)&cpuRegs.code, (u32)cpuRegs.code ); MOV32ItoM( (uptr)&cpuRegs.pc, (u32)pc ); iFlushCall(FLUSH_EVERYTHING); - CALLFunc( (uptr)Interpreter::OpcodeImpl::CACHE ); + CALLFunc( (uptr)R5900::Interpreter::OpcodeImpl::CACHE ); branch = 2; } void recTGE( void ) { - recBranchCall( Interpreter::OpcodeImpl::TGE ); + recBranchCall( R5900::Interpreter::OpcodeImpl::TGE ); } void recTGEU( void ) { - recBranchCall( Interpreter::OpcodeImpl::TGEU ); + recBranchCall( R5900::Interpreter::OpcodeImpl::TGEU ); } void recTLT( void ) { - recBranchCall( Interpreter::OpcodeImpl::TLT ); + recBranchCall( R5900::Interpreter::OpcodeImpl::TLT ); } void recTLTU( void ) { - recBranchCall( Interpreter::OpcodeImpl::TLTU ); + recBranchCall( R5900::Interpreter::OpcodeImpl::TLTU ); } void recTEQ( void ) { - recBranchCall( Interpreter::OpcodeImpl::TEQ ); + recBranchCall( R5900::Interpreter::OpcodeImpl::TEQ ); } void recTNE( void ) { - recBranchCall( Interpreter::OpcodeImpl::TNE ); + recBranchCall( R5900::Interpreter::OpcodeImpl::TNE ); } void recTGEI( void ) { - recBranchCall( Interpreter::OpcodeImpl::TGEI ); + recBranchCall( R5900::Interpreter::OpcodeImpl::TGEI ); } void recTGEIU( void ) { - recBranchCall( Interpreter::OpcodeImpl::TGEIU ); + recBranchCall( R5900::Interpreter::OpcodeImpl::TGEIU ); } void recTLTI( void ) { - recBranchCall( Interpreter::OpcodeImpl::TLTI ); + recBranchCall( R5900::Interpreter::OpcodeImpl::TLTI ); } void recTLTIU( void ) { - recBranchCall( Interpreter::OpcodeImpl::TLTIU ); + recBranchCall( R5900::Interpreter::OpcodeImpl::TLTIU ); } void recTEQI( void ) { - recBranchCall( Interpreter::OpcodeImpl::TEQI ); + recBranchCall( R5900::Interpreter::OpcodeImpl::TEQI ); } void recTNEI( void ) { - recBranchCall( Interpreter::OpcodeImpl::TNEI ); + recBranchCall( R5900::Interpreter::OpcodeImpl::TNEI ); } } // End OpcodeImpl @@ -238,8 +221,8 @@ namespace OpcodeImpl }; #endif -} } // End namespace EE::Dynarec +/* //////////////////////////////////////////////////// static void recCOP0BC0( void ) { @@ -250,72 +233,7 @@ static void recCOP0BC0( void ) static void recCOP0C0( void ) { recCP0C0[ _Funct_ ]( ); -} - -///////////////////////////////// -// Foward-Prob Function Tables // -///////////////////////////////// - -void (*recCP0[32] )() = { - recMFC0, recNULL, recNULL, recNULL, recMTC0, recNULL, recNULL, recNULL, - recCOP0BC0, recNULL, recNULL, recNULL, recNULL, recNULL, recNULL, recNULL, - recCOP0C0, recNULL, recNULL, recNULL, recNULL, recNULL, recNULL, recNULL, - recNULL, recNULL, recNULL, recNULL, recNULL, recNULL, recNULL, recNULL, -}; - -void (*recCP0BC0[32] )() = { - recBC0F, recBC0T, recBC0FL, recBC0TL, recNULL, recNULL, recNULL, recNULL, - recNULL, recNULL, recNULL, recNULL, recNULL, recNULL, recNULL, recNULL, - recNULL, recNULL, recNULL, recNULL, recNULL, recNULL, recNULL, recNULL, - recNULL, recNULL, recNULL, recNULL, recNULL, recNULL, recNULL, recNULL, -}; - -void (*recCP0C0[64] )() = { - recNULL, recTLBR, recTLBWI, recNULL, recNULL, recNULL, recTLBWR, recNULL, - recTLBP, recNULL, recNULL, recNULL, recNULL, recNULL, recNULL, recNULL, - recNULL, recNULL, recNULL, recNULL, recNULL, recNULL, recNULL, recNULL, - recERET, recNULL, recNULL, recNULL, recNULL, recNULL, recNULL, recNULL, - recNULL, recNULL, recNULL, recNULL, recNULL, recNULL, recNULL, recNULL, - recNULL, recNULL, recNULL, recNULL, recNULL, recNULL, recNULL, recNULL, - recNULL, recNULL, recNULL, recNULL, recNULL, recNULL, recNULL, recNULL, - recEI, recDI, recNULL, recNULL, recNULL, recNULL, recNULL, recNULL, -}; - -void (*recCP1[32] )() = { - recMFC1, recNULL, recCFC1, recNULL, recMTC1, recNULL, recCTC1, recNULL, - recCOP1_BC1, recNULL, recNULL, recNULL, recNULL, recNULL, recNULL, recNULL, - recCOP1_S, recNULL, recNULL, recNULL, recCOP1_W, recNULL, recNULL, recNULL, - recNULL, recNULL, recNULL, recNULL, recNULL, recNULL, recNULL, recNULL, -}; - -void (*recCP1BC1[32] )() = { - recBC1F, recBC1T, recBC1FL, recBC1TL, recNULL, recNULL, recNULL, recNULL, - recNULL, recNULL, recNULL, recNULL, recNULL, recNULL, recNULL, recNULL, - recNULL, recNULL, recNULL, recNULL, recNULL, recNULL, recNULL, recNULL, - recNULL, recNULL, recNULL, recNULL, recNULL, recNULL, recNULL, recNULL, -}; - -void (*recCP1S[64] )() = { - recADD_S, recSUB_S, recMUL_S, recDIV_S, recSQRT_S, recABS_S, recMOV_S, recNEG_S, - recNULL, recNULL, recNULL, recNULL, recNULL, recNULL, recNULL, recNULL, - recNULL, recNULL, recNULL, recNULL, recNULL, recNULL, recRSQRT_S, recNULL, - recADDA_S, recSUBA_S, recMULA_S, recNULL, recMADD_S, recMSUB_S, recMADDA_S, recMSUBA_S, - recNULL, recNULL, recNULL, recNULL, recCVT_W, recNULL, recNULL, recNULL, - recMAX_S, recMIN_S, recNULL, recNULL, recNULL, recNULL, recNULL, recNULL, - recC_F, recNULL, recC_EQ, recNULL, recC_LT, recNULL, recC_LE, recNULL, - recNULL, recNULL, recNULL, recNULL, recNULL, recNULL, recNULL, recNULL, -}; - -void (*recCP1W[64] )() = { - recNULL, recNULL, recNULL, recNULL, recNULL, recNULL, recNULL, recNULL, - recNULL, recNULL, recNULL, recNULL, recNULL, recNULL, recNULL, recNULL, - recNULL, recNULL, recNULL, recNULL, recNULL, recNULL, recNULL, recNULL, - recNULL, recNULL, recNULL, recNULL, recNULL, recNULL, recNULL, recNULL, - recCVT_S, recNULL, recNULL, recNULL, recNULL, recNULL, recNULL, recNULL, - recNULL, recNULL, recNULL, recNULL, recNULL, recNULL, recNULL, recNULL, - recNULL, recNULL, recNULL, recNULL, recNULL, recNULL, recNULL, recNULL, - recNULL, recNULL, recNULL, recNULL, recNULL, recNULL, recNULL, recNULL, -}; +}*/ //////////////////////////////////////////////// // Back-Prob Function Tables - Gathering Info // @@ -1280,4 +1198,6 @@ void BSCPropagate::rprop() rpropSetRead(_Rs_, EEINST_LIVE1|(_Rs_!=0?EEINST_MMX:0)); break; } -} +} // End namespace OpcodeImpl + +} } // End namespace Dynarec::R5900 diff --git a/pcsx2/x86/ix86-32/iCore-32.cpp b/pcsx2/x86/ix86-32/iCore-32.cpp index 769f75194a..68c3bdc8ae 100644 --- a/pcsx2/x86/ix86-32/iCore-32.cpp +++ b/pcsx2/x86/ix86-32/iCore-32.cpp @@ -25,22 +25,19 @@ #include "iCore.h" #include "R3000A.h" +#include + +using namespace std; +using namespace R5900; + +namespace Dynarec +{ + u16 x86FpuState, iCWstate; u16 g_mmxAllocCounter = 0; -// used to make sure regs don't get changed while in recompiler -// use FreezeMMXRegs, FreezeXMMRegs -u8 g_globalMMXSaved = 0; - -PCSX2_ALIGNED16(u64 g_globalMMXData[8]); - // X86 caching -extern _x86regs x86regs[X86REGS]; int g_x86checknext; -extern u16 g_x86AllocCounter; - -#include -using namespace std; // use special x86 register allocation for ia32 @@ -123,6 +120,63 @@ int _getFreeX86reg(int mode) return -1; } +void _flushCachedRegs() +{ + _flushConstRegs(); + _flushMMXregs(); + _flushXMMregs(); +} + +void _flushConstReg(int reg) +{ + if( GPR_IS_CONST1( reg ) && !(g_cpuFlushedConstReg&(1<1 ) - { - //SysPrintf("MMX Already Saved!\n"); - return; - } - -#ifdef _MSC_VER - __asm { - movntq mmword ptr [g_globalMMXData + 0], mm0 - movntq mmword ptr [g_globalMMXData + 8], mm1 - movntq mmword ptr [g_globalMMXData + 16], mm2 - movntq mmword ptr [g_globalMMXData + 24], mm3 - movntq mmword ptr [g_globalMMXData + 32], mm4 - movntq mmword ptr [g_globalMMXData + 40], mm5 - movntq mmword ptr [g_globalMMXData + 48], mm6 - movntq mmword ptr [g_globalMMXData + 56], mm7 - emms - } -#else - __asm__(".intel_syntax\n" - "movq [%0+0x00], %%mm0\n" - "movq [%0+0x08], %%mm1\n" - "movq [%0+0x10], %%mm2\n" - "movq [%0+0x18], %%mm3\n" - "movq [%0+0x20], %%mm4\n" - "movq [%0+0x28], %%mm5\n" - "movq [%0+0x30], %%mm6\n" - "movq [%0+0x38], %%mm7\n" - "emms\n" - ".att_syntax\n" : : "r"(g_globalMMXData) ); -#endif - - } - else { - if( g_globalMMXSaved==0 ) - { - //SysPrintf("MMX Not Saved!\n"); - return; - } - g_globalMMXSaved--; - - if( g_globalMMXSaved > 0 ) return; - -#ifdef _MSC_VER - __asm { - movq mm0, mmword ptr [g_globalMMXData + 0] - movq mm1, mmword ptr [g_globalMMXData + 8] - movq mm2, mmword ptr [g_globalMMXData + 16] - movq mm3, mmword ptr [g_globalMMXData + 24] - movq mm4, mmword ptr [g_globalMMXData + 32] - movq mm5, mmword ptr [g_globalMMXData + 40] - movq mm6, mmword ptr [g_globalMMXData + 48] - movq mm7, mmword ptr [g_globalMMXData + 56] - emms - } -#else - __asm__(".intel_syntax\n" - "movq %%mm0, [%0+0x00]\n" - "movq %%mm1, [%0+0x08]\n" - "movq %%mm2, [%0+0x10]\n" - "movq %%mm3, [%0+0x18]\n" - "movq %%mm4, [%0+0x20]\n" - "movq %%mm5, [%0+0x28]\n" - "movq %%mm6, [%0+0x30]\n" - "movq %%mm7, [%0+0x38]\n" - "emms\n" - ".att_syntax\n" : : "r"(g_globalMMXData) ); -#endif - } -} - void SetFPUstate() { _freeMMXreg(6); _freeMMXreg(7); @@ -1196,3 +1173,5 @@ void LogicalOp32ItoM(u32 to, u32 from, int op) case 3: OR32ItoM(to, from); break; } } + +} // end namespace Dynarec \ No newline at end of file diff --git a/pcsx2/x86/ix86-32/iR5900-32.cpp b/pcsx2/x86/ix86-32/iR5900-32.cpp index 7fc34d8322..2c77358eb2 100644 --- a/pcsx2/x86/ix86-32/iR5900-32.cpp +++ b/pcsx2/x86/ix86-32/iR5900-32.cpp @@ -45,16 +45,49 @@ #ifdef _WIN32 #pragma warning(disable:4244) -#pragma warning(disable:4761) +//#pragma warning(disable:4761) +#endif + +// used to disable register freezing during cpuBranchTests (registers +// are safe then since they've been completely flushed) +bool g_EEFreezeRegs = false; + +namespace Dynarec +{ + +extern void recCOP22( void ); + +namespace R5900 +{ + +// I can't find where the Linux recRecompile is defined. Is it used anymore? +// If so, namespacing might break it. :/ (air) +#ifdef __LINUX__ +extern "C" { +#endif +void recRecompile( u32 startpc ); +#ifdef __LINUX__ +} #endif u32 maxrecmem = 0; uptr *recLUT = NULL; -#define X86 -#define RECSTACK_SIZE 0x00010000 +u32 s_nBlockCycles = 0; // cycles of current block recompiling +u8* dyna_block_discard_recmem=0; -#define EE_NUMBLOCKS (1<<15) +u32 pc; // recompiler pc +int branch; // set for branch + +u32 s_saveConstGPRreg = 0; +GPR_reg64 s_ConstGPRreg; + +//////////////////////////////////////////////////////////////// +// Static Private Variables - R5900 Dynarec + +#define X86 +static const int RECSTACK_SIZE = 0x00010000; +static const int EE_NUMBLOCKS = (1<<15); static u8 *recMem = NULL; // the recompiled blocks will be here static u8* recStack = NULL; // stack mem @@ -66,10 +99,6 @@ static u8* recPtr = NULL, *recStackPtr = NULL; static EEINST* s_pInstCache = NULL; static u32 s_nInstCacheSize = 0; -// used to disable register freezing during cpuBranchTests (registers -// are safe then since they've been completely flushed) -bool g_EEFreezeRegs = false; - static BASEBLOCK* s_pCurBlock = NULL; static BASEBLOCKEX* s_pCurBlockEx = NULL; static BASEBLOCK* s_pDispatchBlock = NULL; @@ -80,47 +109,27 @@ static u32 s_nNextBlock = 0; // next free block in recBlocks // save states for branches static u16 s_savex86FpuState, s_saveiCWstate; -static GPR_reg64 s_ConstGPRreg; -static u32 s_saveConstGPRreg = 0, s_saveHasConstReg = 0, s_saveFlushedConstReg = 0, s_saveRegHasLive1 = 0, s_saveRegHasSignExt = 0; +static u32 s_saveHasConstReg = 0, s_saveFlushedConstReg = 0, s_saveRegHasLive1 = 0, s_saveRegHasSignExt = 0; static EEINST* s_psaveInstInfo = NULL; -u32 s_nBlockCycles = 0; // cycles of current block recompiling - static u32 s_savenBlockCycles = 0; -void recCOP2RecompileInst(); -int recCOP2AnalyzeBlock(u32 startpc, u32 endpc); -void recCOP2EndBlock(void); -u8* dyna_block_discard_recmem=0; - #ifdef _DEBUG -u32 dumplog = 0; +static u32 dumplog = 0; #else #define dumplog 0 #endif -u32 pc; // recompiler pc -int branch; // set for branch - -//#ifdef PCSX2_DEVBUILD -LARGE_INTEGER lbase = {0}, lfinal = {0}; -//static u32 s_startcount = 0; -//#endif - +#ifdef PCSX2_DEVBUILD +// and not sure what these might have once been used for... (air) static const char *txt0 = "EAX = %x : ECX = %x : EDX = %x\n"; static const char *txt0RC = "EAX = %x : EBX = %x : ECX = %x : EDX = %x : ESI = %x : EDI = %x\n"; static const char *txt1 = "REG[%d] = %x_%x\n"; static const char *txt2 = "M32 = %x\n"; +#endif static void iBranchTest(u32 newpc, u32 cpuBranch); -void recCOP22( void ); -#ifdef __LINUX__ -extern "C" { -#endif -void recRecompile( u32 startpc ); -#ifdef __LINUX__ -} -#endif + BASEBLOCKEX* PC_GETBLOCKEX(BASEBLOCK* p) { // BASEBLOCKEX* pex = *(BASEBLOCKEX**)(p+1); @@ -138,7 +147,6 @@ static void iDumpBlock( int startpc, u8 * ptr ) char filename[ g_MaxPath ]; u32 i, j; EEINST* pcur; - extern const char *disRNameGPR[]; u8 used[34]; u8 fpuused[33]; int numused, count, fpunumused; @@ -235,7 +243,7 @@ static void iDumpBlock( int startpc, u8 * ptr ) fclose( f ); } -u8 _eeLoadWritesRs(u32 tempcode) +static u8 _eeLoadWritesRs(u32 tempcode) { switch(tempcode>>26) { case 26: // ldl @@ -248,7 +256,7 @@ u8 _eeLoadWritesRs(u32 tempcode) return 0; } -u8 _eeIsLoadStoreCoIssue(u32 firstcode, u32 secondcode) +static u8 _eeIsLoadStoreCoIssue(u32 firstcode, u32 secondcode) { switch(firstcode>>26) { case 34: // lwl @@ -287,7 +295,7 @@ u8 _eeIsLoadStoreCoIssue(u32 firstcode, u32 secondcode) return 0; } -u8 _eeIsLoadStoreCoX(u32 tempcode) +static u8 _eeIsLoadStoreCoX(u32 tempcode) { switch( tempcode>>26 ) { case 30: case 31: case 49: case 57: case 55: case 63: @@ -397,63 +405,6 @@ int _flushUnusedConstReg() return 0; } -void _flushCachedRegs() -{ - _flushConstRegs(); - _flushMMXregs(); - _flushXMMregs(); -} - -void _flushConstReg(int reg) -{ - if( GPR_IS_CONST1( reg ) && !(g_cpuFlushedConstReg&(1<regs[reg]&EEINST_LASTUSE) ) { - if( usemmx ) return _allocMMXreg(-1, MMX_GPR+reg, mode); - return _allocGPRtoXMMreg(-1, reg, mode); - } - - return -1; -} - -#define PROCESS_EE_SETMODES(mmreg) ((mmxregs[mmreg].mode&MODE_WRITE)?PROCESS_EE_MODEWRITES:0) -#define PROCESS_EE_SETMODET(mmreg) ((mmxregs[mmreg].mode&MODE_WRITE)?PROCESS_EE_MODEWRITET:0) - -// ignores XMMINFO_READS, XMMINFO_READT, and XMMINFO_READD_LO from xmminfo -// core of reg caching -void eeRecompileCode0(R5900FNPTR constcode, R5900FNPTR_INFO constscode, R5900FNPTR_INFO consttcode, R5900FNPTR_INFO noconstcode, int xmminfo) -{ - int mmreg1, mmreg2, mmreg3, mmtemp, moded; - - if ( ! _Rd_ && (xmminfo&XMMINFO_WRITED) ) return; - - if( xmminfo&XMMINFO_WRITED) { - CHECK_SAVE_REG(_Rd_); - _eeProcessHasLive(_Rd_, 0); - EEINST_RESETSIGNEXT(_Rd_); - } - - if( GPR_IS_CONST2(_Rs_, _Rt_) ) { - if( xmminfo & XMMINFO_WRITED ) { - _deleteMMXreg(MMX_GPR+_Rd_, 2); - _deleteGPRtoXMMreg(_Rd_, 2); - } - if( xmminfo&XMMINFO_WRITED ) GPR_SET_CONST(_Rd_); - constcode(); - return; - } - - moded = MODE_WRITE|((xmminfo&XMMINFO_READD)?MODE_READ:0); - - // test if should write mmx - if( g_pCurInstInfo->info & EEINST_MMX ) { - - if( xmminfo & (XMMINFO_READLO|XMMINFO_WRITELO) ) _addNeededMMXreg(MMX_GPR+MMX_LO); - if( xmminfo & (XMMINFO_READHI|XMMINFO_WRITEHI) ) _addNeededMMXreg(MMX_GPR+MMX_HI); - _addNeededMMXreg(MMX_GPR+_Rs_); - _addNeededMMXreg(MMX_GPR+_Rt_); - - if( GPR_IS_CONST1(_Rs_) || GPR_IS_CONST1(_Rt_) ) { - int creg = GPR_IS_CONST1(_Rs_) ? _Rs_ : _Rt_; - int vreg = creg == _Rs_ ? _Rt_ : _Rs_; - -// if(g_pCurInstInfo->regs[vreg]&EEINST_MMX) { -// mmreg1 = _allocMMXreg(-1, MMX_GPR+vreg, MODE_READ); -// _addNeededMMXreg(MMX_GPR+vreg); -// } - mmreg1 = _allocCheckGPRtoMMX(g_pCurInstInfo, vreg, MODE_READ); - - if( mmreg1 >= 0 ) { - int info = PROCESS_EE_MMX; - - if( GPR_IS_CONST1(_Rs_) ) info |= PROCESS_EE_SETMODET(mmreg1); - else info |= PROCESS_EE_SETMODES(mmreg1); - - if( xmminfo & XMMINFO_WRITED ) { - _addNeededMMXreg(MMX_GPR+_Rd_); - mmreg3 = _checkMMXreg(MMX_GPR+_Rd_, moded); - - if( !(xmminfo&XMMINFO_READD) && mmreg3 < 0 && ((g_pCurInstInfo->regs[vreg] & EEINST_LASTUSE) || !EEINST_ISLIVE64(vreg)) ) { - if( EEINST_ISLIVE64(vreg) ) { - _freeMMXreg(mmreg1); - if( GPR_IS_CONST1(_Rs_) ) info &= ~PROCESS_EE_MODEWRITET; - else info &= ~PROCESS_EE_MODEWRITES; - } - _deleteGPRtoXMMreg(_Rd_, 2); - mmxregs[mmreg1].inuse = 1; - mmxregs[mmreg1].reg = _Rd_; - mmxregs[mmreg1].mode = moded; - mmreg3 = mmreg1; - } - else if( mmreg3 < 0 ) mmreg3 = _allocMMXreg(-1, MMX_GPR+_Rd_, moded); - - info |= PROCESS_EE_SET_D(mmreg3); - } - - if( xmminfo & (XMMINFO_READLO|XMMINFO_WRITELO) ) { - mmtemp = eeProcessHILO(MMX_LO, ((xmminfo&XMMINFO_READLO)?MODE_READ:0)|((xmminfo&XMMINFO_WRITELO)?MODE_WRITE:0), 1); - if( mmtemp >= 0 ) info |= PROCESS_EE_SET_LO(mmtemp); - } - if( xmminfo & (XMMINFO_READHI|XMMINFO_WRITEHI) ) { - mmtemp = eeProcessHILO(MMX_HI, ((xmminfo&XMMINFO_READLO)?MODE_READ:0)|((xmminfo&XMMINFO_WRITELO)?MODE_WRITE:0), 1); - if( mmtemp >= 0 ) info |= PROCESS_EE_SET_HI(mmtemp); - } - - SetMMXstate(); - if( creg == _Rs_ ) constscode(info|PROCESS_EE_SET_T(mmreg1)); - else consttcode(info|PROCESS_EE_SET_S(mmreg1)); - _clearNeededMMXregs(); - if( xmminfo & XMMINFO_WRITED ) GPR_DEL_CONST(_Rd_); - return; - } - } - else { - // no const regs - mmreg1 = _allocCheckGPRtoMMX(g_pCurInstInfo, _Rs_, MODE_READ); - mmreg2 = _allocCheckGPRtoMMX(g_pCurInstInfo, _Rt_, MODE_READ); - - if( mmreg1 >= 0 || mmreg2 >= 0 ) { - int info = PROCESS_EE_MMX; - - // do it all in mmx - if( mmreg1 < 0 ) mmreg1 = _allocMMXreg(-1, MMX_GPR+_Rs_, MODE_READ); - if( mmreg2 < 0 ) mmreg2 = _allocMMXreg(-1, MMX_GPR+_Rt_, MODE_READ); - - info |= PROCESS_EE_SETMODES(mmreg1)|PROCESS_EE_SETMODET(mmreg2); - - // check for last used, if so don't alloc a new MMX reg - if( xmminfo & XMMINFO_WRITED ) { - _addNeededMMXreg(MMX_GPR+_Rd_); - mmreg3 = _checkMMXreg(MMX_GPR+_Rd_, moded); - - if( mmreg3 < 0 ) { - if( !(xmminfo&XMMINFO_READD) && ((g_pCurInstInfo->regs[_Rt_] & EEINST_LASTUSE) || !EEINST_ISLIVE64(_Rt_)) ) { - if( EEINST_ISLIVE64(_Rt_) ) { - _freeMMXreg(mmreg2); - info &= ~PROCESS_EE_MODEWRITET; - } - _deleteGPRtoXMMreg(_Rd_, 2); - mmxregs[mmreg2].inuse = 1; - mmxregs[mmreg2].reg = _Rd_; - mmxregs[mmreg2].mode = moded; - mmreg3 = mmreg2; - } - else if( !(xmminfo&XMMINFO_READD) && ((g_pCurInstInfo->regs[_Rs_] & EEINST_LASTUSE) || !EEINST_ISLIVE64(_Rs_)) ) { - if( EEINST_ISLIVE64(_Rs_) ) { - _freeMMXreg(mmreg1); - info &= ~PROCESS_EE_MODEWRITES; - } - _deleteGPRtoXMMreg(_Rd_, 2); - mmxregs[mmreg1].inuse = 1; - mmxregs[mmreg1].reg = _Rd_; - mmxregs[mmreg1].mode = moded; - mmreg3 = mmreg1; - } - else mmreg3 = _allocMMXreg(-1, MMX_GPR+_Rd_, moded); - } - - info |= PROCESS_EE_SET_D(mmreg3); - } - - if( xmminfo & (XMMINFO_READLO|XMMINFO_WRITELO) ) { - mmtemp = eeProcessHILO(MMX_LO, ((xmminfo&XMMINFO_READLO)?MODE_READ:0)|((xmminfo&XMMINFO_WRITELO)?MODE_WRITE:0), 1); - if( mmtemp >= 0 ) info |= PROCESS_EE_SET_LO(mmtemp); - } - if( xmminfo & (XMMINFO_READHI|XMMINFO_WRITEHI) ) { - mmtemp = eeProcessHILO(MMX_HI, ((xmminfo&XMMINFO_READLO)?MODE_READ:0)|((xmminfo&XMMINFO_WRITELO)?MODE_WRITE:0), 1); - if( mmtemp >= 0 ) info |= PROCESS_EE_SET_HI(mmtemp); - } - - SetMMXstate(); - noconstcode(info|PROCESS_EE_SET_S(mmreg1)|PROCESS_EE_SET_T(mmreg2)); - _clearNeededMMXregs(); - if( xmminfo & XMMINFO_WRITED ) GPR_DEL_CONST(_Rd_); - return; - } - } - - _clearNeededMMXregs(); - } - - // test if should write xmm, mirror to mmx code - if( g_pCurInstInfo->info & EEINST_XMM ) { - - if( xmminfo & (XMMINFO_READLO|XMMINFO_WRITELO) ) _addNeededGPRtoXMMreg(XMMGPR_LO); - if( xmminfo & (XMMINFO_READHI|XMMINFO_WRITEHI) ) _addNeededGPRtoXMMreg(XMMGPR_HI); - _addNeededGPRtoXMMreg(_Rs_); - _addNeededGPRtoXMMreg(_Rt_); - - if( GPR_IS_CONST1(_Rs_) || GPR_IS_CONST1(_Rt_) ) { - int creg = GPR_IS_CONST1(_Rs_) ? _Rs_ : _Rt_; - int vreg = creg == _Rs_ ? _Rt_ : _Rs_; - -// if(g_pCurInstInfo->regs[vreg]&EEINST_XMM) { -// mmreg1 = _allocGPRtoXMMreg(-1, vreg, MODE_READ); -// _addNeededGPRtoXMMreg(vreg); -// } - mmreg1 = _allocCheckGPRtoXMM(g_pCurInstInfo, vreg, MODE_READ); - - if( mmreg1 >= 0 ) { - int info = PROCESS_EE_XMM; - - if( GPR_IS_CONST1(_Rs_) ) info |= PROCESS_EE_SETMODET(mmreg1); - else info |= PROCESS_EE_SETMODES(mmreg1); - - if( xmminfo & XMMINFO_WRITED ) { - - _addNeededGPRtoXMMreg(_Rd_); - mmreg3 = _checkXMMreg(XMMTYPE_GPRREG, _Rd_, MODE_WRITE); - - if( !(xmminfo&XMMINFO_READD) && mmreg3 < 0 && ((g_pCurInstInfo->regs[vreg] & EEINST_LASTUSE) || !EEINST_ISLIVEXMM(vreg)) ) { - _freeXMMreg(mmreg1); - if( GPR_IS_CONST1(_Rs_) ) info &= ~PROCESS_EE_MODEWRITET; - else info &= ~PROCESS_EE_MODEWRITES; - _deleteMMXreg(MMX_GPR+_Rd_, 2); - xmmregs[mmreg1].inuse = 1; - xmmregs[mmreg1].reg = _Rd_; - xmmregs[mmreg1].mode = moded; - mmreg3 = mmreg1; - } - else if( mmreg3 < 0 ) mmreg3 = _allocGPRtoXMMreg(-1, _Rd_, moded); - - info |= PROCESS_EE_SET_D(mmreg3); - } - - if( xmminfo & (XMMINFO_READLO|XMMINFO_WRITELO) ) { - mmtemp = eeProcessHILO(XMMGPR_LO, ((xmminfo&XMMINFO_READLO)?MODE_READ:0)|((xmminfo&XMMINFO_WRITELO)?MODE_WRITE:0), 0); - if( mmtemp >= 0 ) info |= PROCESS_EE_SET_LO(mmtemp); - } - if( xmminfo & (XMMINFO_READHI|XMMINFO_WRITEHI) ) { - mmtemp = eeProcessHILO(XMMGPR_HI, ((xmminfo&XMMINFO_READLO)?MODE_READ:0)|((xmminfo&XMMINFO_WRITELO)?MODE_WRITE:0), 0); - if( mmtemp >= 0 ) info |= PROCESS_EE_SET_HI(mmtemp); - } - - if( creg == _Rs_ ) constscode(info|PROCESS_EE_SET_T(mmreg1)); - else consttcode(info|PROCESS_EE_SET_S(mmreg1)); - _clearNeededXMMregs(); - if( xmminfo & XMMINFO_WRITED ) GPR_DEL_CONST(_Rd_); - return; - } - } - else { - // no const regs - mmreg1 = _allocCheckGPRtoXMM(g_pCurInstInfo, _Rs_, MODE_READ); - mmreg2 = _allocCheckGPRtoXMM(g_pCurInstInfo, _Rt_, MODE_READ); - - if( mmreg1 >= 0 || mmreg2 >= 0 ) { - int info = PROCESS_EE_XMM; - - // do it all in xmm - if( mmreg1 < 0 ) mmreg1 = _allocGPRtoXMMreg(-1, _Rs_, MODE_READ); - if( mmreg2 < 0 ) mmreg2 = _allocGPRtoXMMreg(-1, _Rt_, MODE_READ); - - info |= PROCESS_EE_SETMODES(mmreg1)|PROCESS_EE_SETMODET(mmreg2); - - if( xmminfo & XMMINFO_WRITED ) { - // check for last used, if so don't alloc a new XMM reg - _addNeededGPRtoXMMreg(_Rd_); - mmreg3 = _checkXMMreg(XMMTYPE_GPRREG, _Rd_, moded); - - if( mmreg3 < 0 ) { - if( !(xmminfo&XMMINFO_READD) && ((g_pCurInstInfo->regs[_Rt_] & EEINST_LASTUSE) || !EEINST_ISLIVEXMM(_Rt_)) ) { - _freeXMMreg(mmreg2); - info &= ~PROCESS_EE_MODEWRITET; - _deleteMMXreg(MMX_GPR+_Rd_, 2); - xmmregs[mmreg2].inuse = 1; - xmmregs[mmreg2].reg = _Rd_; - xmmregs[mmreg2].mode = moded; - mmreg3 = mmreg2; - } - else if( !(xmminfo&XMMINFO_READD) && ((g_pCurInstInfo->regs[_Rs_] & EEINST_LASTUSE) || !EEINST_ISLIVEXMM(_Rs_)) ) { - _freeXMMreg(mmreg1); - info &= ~PROCESS_EE_MODEWRITES; - _deleteMMXreg(MMX_GPR+_Rd_, 2); - xmmregs[mmreg1].inuse = 1; - xmmregs[mmreg1].reg = _Rd_; - xmmregs[mmreg1].mode = moded; - mmreg3 = mmreg1; - } - else mmreg3 = _allocGPRtoXMMreg(-1, _Rd_, moded); - } - - info |= PROCESS_EE_SET_D(mmreg3); - } - - if( xmminfo & (XMMINFO_READLO|XMMINFO_WRITELO) ) { - mmtemp = eeProcessHILO(XMMGPR_LO, ((xmminfo&XMMINFO_READLO)?MODE_READ:0)|((xmminfo&XMMINFO_WRITELO)?MODE_WRITE:0), 0); - if( mmtemp >= 0 ) info |= PROCESS_EE_SET_LO(mmtemp); - } - if( xmminfo & (XMMINFO_READHI|XMMINFO_WRITEHI) ) { - mmtemp = eeProcessHILO(XMMGPR_HI, ((xmminfo&XMMINFO_READLO)?MODE_READ:0)|((xmminfo&XMMINFO_WRITELO)?MODE_WRITE:0), 0); - if( mmtemp >= 0 ) info |= PROCESS_EE_SET_HI(mmtemp); - } - - noconstcode(info|PROCESS_EE_SET_S(mmreg1)|PROCESS_EE_SET_T(mmreg2)); - _clearNeededXMMregs(); - if( xmminfo & XMMINFO_WRITED ) GPR_DEL_CONST(_Rd_); - return; - } - } - - _clearNeededXMMregs(); - } - - // regular x86 - _deleteGPRtoXMMreg(_Rs_, 1); - _deleteGPRtoXMMreg(_Rt_, 1); - if( xmminfo&XMMINFO_WRITED ) - _deleteGPRtoXMMreg(_Rd_, (xmminfo&XMMINFO_READD)?0:2); - _deleteMMXreg(MMX_GPR+_Rs_, 1); - _deleteMMXreg(MMX_GPR+_Rt_, 1); - if( xmminfo&XMMINFO_WRITED ) - _deleteMMXreg(MMX_GPR+_Rd_, (xmminfo&XMMINFO_READD)?0:2); - - // don't delete, fn will take care of them -// if( xmminfo & (XMMINFO_READLO|XMMINFO_WRITELO) ) { -// _deleteGPRtoXMMreg(XMMGPR_LO, (xmminfo&XMMINFO_READLO)?1:0); -// _deleteMMXreg(MMX_GPR+MMX_LO, (xmminfo&XMMINFO_READLO)?1:0); -// } -// if( xmminfo & (XMMINFO_READHI|XMMINFO_WRITEHI) ) { -// _deleteGPRtoXMMreg(XMMGPR_HI, (xmminfo&XMMINFO_READHI)?1:0); -// _deleteMMXreg(MMX_GPR+MMX_HI, (xmminfo&XMMINFO_READHI)?1:0); -// } - - if( GPR_IS_CONST1(_Rs_) ) { - constscode(0); - if( xmminfo&XMMINFO_WRITED ) GPR_DEL_CONST(_Rd_); - return; - } - - if( GPR_IS_CONST1(_Rt_) ) { - consttcode(0); - if( xmminfo&XMMINFO_WRITED ) GPR_DEL_CONST(_Rd_); - return; - } - - noconstcode(0); - if( xmminfo&XMMINFO_WRITED ) GPR_DEL_CONST(_Rd_); -} - -// rt = rs op imm16 -void eeRecompileCode1(R5900FNPTR constcode, R5900FNPTR_INFO noconstcode) -{ - int mmreg1, mmreg2; - if ( ! _Rt_ ) return; - - CHECK_SAVE_REG(_Rt_); - _eeProcessHasLive(_Rt_, 0); - EEINST_RESETSIGNEXT(_Rt_); - - if( GPR_IS_CONST1(_Rs_) ) { - _deleteMMXreg(MMX_GPR+_Rt_, 2); - _deleteGPRtoXMMreg(_Rt_, 2); - GPR_SET_CONST(_Rt_); - constcode(); - return; - } - - // test if should write mmx - if( g_pCurInstInfo->info & EEINST_MMX ) { - - // no const regs - mmreg1 = _allocCheckGPRtoMMX(g_pCurInstInfo, _Rs_, MODE_READ); - - if( mmreg1 >= 0 ) { - int info = PROCESS_EE_MMX|PROCESS_EE_SETMODES(mmreg1); - - // check for last used, if so don't alloc a new MMX reg - _addNeededMMXreg(MMX_GPR+_Rt_); - mmreg2 = _checkMMXreg(MMX_GPR+_Rt_, MODE_WRITE); - - if( mmreg2 < 0 ) { - if( (g_pCurInstInfo->regs[_Rs_] & EEINST_LASTUSE) || !EEINST_ISLIVE64(_Rs_) ) { - if( EEINST_ISLIVE64(_Rs_) ) { - _freeMMXreg(mmreg1); - info &= ~PROCESS_EE_MODEWRITES; - } - _deleteGPRtoXMMreg(_Rt_, 2); - mmxregs[mmreg1].inuse = 1; - mmxregs[mmreg1].reg = _Rt_; - mmxregs[mmreg1].mode = MODE_WRITE|MODE_READ; - mmreg2 = mmreg1; - } - else mmreg2 = _allocMMXreg(-1, MMX_GPR+_Rt_, MODE_WRITE); - } - - SetMMXstate(); - noconstcode(info|PROCESS_EE_SET_S(mmreg1)|PROCESS_EE_SET_T(mmreg2)); - _clearNeededMMXregs(); - GPR_DEL_CONST(_Rt_); - return; - } - - _clearNeededMMXregs(); - } - - // test if should write xmm, mirror to mmx code - if( g_pCurInstInfo->info & EEINST_XMM ) { - - // no const regs - mmreg1 = _allocCheckGPRtoXMM(g_pCurInstInfo, _Rs_, MODE_READ); - - if( mmreg1 >= 0 ) { - int info = PROCESS_EE_XMM|PROCESS_EE_SETMODES(mmreg1); - - // check for last used, if so don't alloc a new XMM reg - _addNeededGPRtoXMMreg(_Rt_); - mmreg2 = _checkXMMreg(XMMTYPE_GPRREG, _Rt_, MODE_WRITE); - - if( mmreg2 < 0 ) { - if( (g_pCurInstInfo->regs[_Rs_] & EEINST_LASTUSE) || !EEINST_ISLIVEXMM(_Rs_) ) { - _freeXMMreg(mmreg1); - info &= ~PROCESS_EE_MODEWRITES; - _deleteMMXreg(MMX_GPR+_Rt_, 2); - xmmregs[mmreg1].inuse = 1; - xmmregs[mmreg1].reg = _Rt_; - xmmregs[mmreg1].mode = MODE_WRITE|MODE_READ; - mmreg2 = mmreg1; - } - else mmreg2 = _allocGPRtoXMMreg(-1, _Rt_, MODE_WRITE); - } - - noconstcode(info|PROCESS_EE_SET_S(mmreg1)|PROCESS_EE_SET_T(mmreg2)); - _clearNeededXMMregs(); - GPR_DEL_CONST(_Rt_); - return; - } - - _clearNeededXMMregs(); - } - - // regular x86 - _deleteGPRtoXMMreg(_Rs_, 1); - _deleteGPRtoXMMreg(_Rt_, 2); - _deleteMMXreg(MMX_GPR+_Rs_, 1); - _deleteMMXreg(MMX_GPR+_Rt_, 2); - - noconstcode(0); - GPR_DEL_CONST(_Rt_); -} - -// rd = rt op sa -void eeRecompileCode2(R5900FNPTR constcode, R5900FNPTR_INFO noconstcode) -{ - int mmreg1, mmreg2; - if ( ! _Rd_ ) return; - - CHECK_SAVE_REG(_Rd_); - _eeProcessHasLive(_Rd_, 0); - EEINST_RESETSIGNEXT(_Rd_); - - if( GPR_IS_CONST1(_Rt_) ) { - _deleteMMXreg(MMX_GPR+_Rd_, 2); - _deleteGPRtoXMMreg(_Rd_, 2); - GPR_SET_CONST(_Rd_); - constcode(); - return; - } - - // test if should write mmx - if( g_pCurInstInfo->info & EEINST_MMX ) { - - // no const regs - mmreg1 = _allocCheckGPRtoMMX(g_pCurInstInfo, _Rt_, MODE_READ); - - if( mmreg1 >= 0 ) { - int info = PROCESS_EE_MMX|PROCESS_EE_SETMODET(mmreg1); - - // check for last used, if so don't alloc a new MMX reg - _addNeededMMXreg(MMX_GPR+_Rd_); - mmreg2 = _checkMMXreg(MMX_GPR+_Rd_, MODE_WRITE); - - if( mmreg2 < 0 ) { - if( (g_pCurInstInfo->regs[_Rt_] & EEINST_LASTUSE) || !EEINST_ISLIVE64(_Rt_) ) { - if( EEINST_ISLIVE64(_Rt_) ) { - _freeMMXreg(mmreg1); - info &= ~PROCESS_EE_MODEWRITET; - } - _deleteGPRtoXMMreg(_Rd_, 2); - mmxregs[mmreg1].inuse = 1; - mmxregs[mmreg1].reg = _Rd_; - mmxregs[mmreg1].mode = MODE_WRITE|MODE_READ; - mmreg2 = mmreg1; - } - else mmreg2 = _allocMMXreg(-1, MMX_GPR+_Rd_, MODE_WRITE); - } - - SetMMXstate(); - noconstcode(info|PROCESS_EE_SET_T(mmreg1)|PROCESS_EE_SET_D(mmreg2)); - _clearNeededMMXregs(); - GPR_DEL_CONST(_Rd_); - return; - } - - _clearNeededMMXregs(); - } - - // test if should write xmm, mirror to mmx code - if( g_pCurInstInfo->info & EEINST_XMM ) { - - // no const regs - mmreg1 = _allocCheckGPRtoXMM(g_pCurInstInfo, _Rt_, MODE_READ); - - if( mmreg1 >= 0 ) { - int info = PROCESS_EE_XMM|PROCESS_EE_SETMODET(mmreg1); - - // check for last used, if so don't alloc a new XMM reg - _addNeededGPRtoXMMreg(_Rd_); - mmreg2 = _checkXMMreg(XMMTYPE_GPRREG, _Rd_, MODE_WRITE); - - if( mmreg2 < 0 ) { - if( (g_pCurInstInfo->regs[_Rt_] & EEINST_LASTUSE) || !EEINST_ISLIVE64(_Rt_) ) { - _freeXMMreg(mmreg1); - info &= ~PROCESS_EE_MODEWRITET; - _deleteMMXreg(MMX_GPR+_Rd_, 2); - xmmregs[mmreg1].inuse = 1; - xmmregs[mmreg1].reg = _Rd_; - xmmregs[mmreg1].mode = MODE_WRITE|MODE_READ; - mmreg2 = mmreg1; - } - else mmreg2 = _allocGPRtoXMMreg(-1, _Rd_, MODE_WRITE); - } - - noconstcode(info|PROCESS_EE_SET_T(mmreg1)|PROCESS_EE_SET_D(mmreg2)); - _clearNeededXMMregs(); - GPR_DEL_CONST(_Rd_); - return; - } - - _clearNeededXMMregs(); - } - - // regular x86 - _deleteGPRtoXMMreg(_Rt_, 1); - _deleteGPRtoXMMreg(_Rd_, 2); - _deleteMMXreg(MMX_GPR+_Rt_, 1); - _deleteMMXreg(MMX_GPR+_Rd_, 2); - - noconstcode(0); - GPR_DEL_CONST(_Rd_); -} - -// rt op rs -void eeRecompileCode3(R5900FNPTR constcode, R5900FNPTR_INFO multicode) -{ - assert(0); - // for now, don't support xmm - _deleteEEreg(_Rs_, 1); - _deleteEEreg(_Rt_, 1); - - if( GPR_IS_CONST2(_Rs_, _Rt_) ) { - constcode(); - return; - } - - if( GPR_IS_CONST1(_Rs_) ) { - //multicode(PROCESS_EE_CONSTT); - return; - } - - if( GPR_IS_CONST1(_Rt_) ) { - //multicode(PROCESS_EE_CONSTT); - return; - } - - multicode(0); -} - -// Simple Code Templates // - -// rd = rs op rt -void eeRecompileCodeConst0(R5900FNPTR constcode, R5900FNPTR_INFO constscode, R5900FNPTR_INFO consttcode, R5900FNPTR_INFO noconstcode) -{ - if ( ! _Rd_ ) return; - - // for now, don't support xmm - CHECK_SAVE_REG(_Rd_); - - _deleteGPRtoXMMreg(_Rs_, 1); - _deleteGPRtoXMMreg(_Rt_, 1); - _deleteGPRtoXMMreg(_Rd_, 0); - _deleteMMXreg(MMX_GPR+_Rs_, 1); - _deleteMMXreg(MMX_GPR+_Rt_, 1); - _deleteMMXreg(MMX_GPR+_Rd_, 0); - - if( GPR_IS_CONST2(_Rs_, _Rt_) ) { - GPR_SET_CONST(_Rd_); - constcode(); - return; - } - - if( GPR_IS_CONST1(_Rs_) ) { - constscode(0); - GPR_DEL_CONST(_Rd_); - return; - } - - if( GPR_IS_CONST1(_Rt_) ) { - consttcode(0); - GPR_DEL_CONST(_Rd_); - return; - } - - noconstcode(0); - GPR_DEL_CONST(_Rd_); -} - -// rt = rs op imm16 -void eeRecompileCodeConst1(R5900FNPTR constcode, R5900FNPTR_INFO noconstcode) -{ - if ( ! _Rt_ ) - return; - - // for now, don't support xmm - CHECK_SAVE_REG(_Rt_); - - _deleteGPRtoXMMreg(_Rs_, 1); - _deleteGPRtoXMMreg(_Rt_, 0); - - if( GPR_IS_CONST1(_Rs_) ) { - GPR_SET_CONST(_Rt_); - constcode(); - return; - } - - noconstcode(0); - GPR_DEL_CONST(_Rt_); -} - -// rd = rt op sa -void eeRecompileCodeConst2(R5900FNPTR constcode, R5900FNPTR_INFO noconstcode) -{ - if ( ! _Rd_ ) return; - - // for now, don't support xmm - CHECK_SAVE_REG(_Rd_); - - _deleteGPRtoXMMreg(_Rt_, 1); - _deleteGPRtoXMMreg(_Rd_, 0); - - if( GPR_IS_CONST1(_Rt_) ) { - GPR_SET_CONST(_Rd_); - constcode(); - return; - } - - noconstcode(0); - GPR_DEL_CONST(_Rd_); -} - -// rd = rt MULT rs (SPECIAL) -void eeRecompileCodeConstSPECIAL(R5900FNPTR constcode, R5900FNPTR_INFO multicode, int MULT) -{ - assert(0); - // for now, don't support xmm - if( MULT ) { - CHECK_SAVE_REG(_Rd_); - _deleteGPRtoXMMreg(_Rd_, 0); - } - - _deleteGPRtoXMMreg(_Rs_, 1); - _deleteGPRtoXMMreg(_Rt_, 1); - - if( GPR_IS_CONST2(_Rs_, _Rt_) ) { - if( MULT && _Rd_ ) GPR_SET_CONST(_Rd_); - constcode(); - return; - } - - if( GPR_IS_CONST1(_Rs_) ) { - //multicode(PROCESS_EE_CONSTS); - if( MULT && _Rd_ ) GPR_DEL_CONST(_Rd_); - return; - } - - if( GPR_IS_CONST1(_Rt_) ) { - //multicode(PROCESS_EE_CONSTT); - if( MULT && _Rd_ ) GPR_DEL_CONST(_Rd_); - return; - } - - multicode(0); - if( MULT && _Rd_ ) GPR_DEL_CONST(_Rd_); -} - -// EE XMM allocation code -int eeRecompileCodeXMM(int xmminfo) -{ - int info = PROCESS_EE_XMM; - - // save state - if( xmminfo & XMMINFO_WRITED ) { - CHECK_SAVE_REG(_Rd_); - _eeProcessHasLive(_Rd_, 0); - EEINST_RESETSIGNEXT(_Rd_); - } - - // flush consts - if( xmminfo & XMMINFO_READT ) { - if( GPR_IS_CONST1( _Rt_ ) && !(g_cpuFlushedConstReg&(1<<_Rt_)) ) { - MOV32ItoM((int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ], g_cpuConstRegs[_Rt_].UL[0]); - MOV32ItoM((int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 1 ], g_cpuConstRegs[_Rt_].UL[1]); - g_cpuFlushedConstReg |= (1<<_Rt_); - } - } - if( xmminfo & XMMINFO_READS) { - if( GPR_IS_CONST1( _Rs_ ) && !(g_cpuFlushedConstReg&(1<<_Rs_)) ) { - MOV32ItoM((int)&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ], g_cpuConstRegs[_Rs_].UL[0]); - MOV32ItoM((int)&cpuRegs.GPR.r[ _Rs_ ].UL[ 1 ], g_cpuConstRegs[_Rs_].UL[1]); - g_cpuFlushedConstReg |= (1<<_Rs_); - } - } - - if( xmminfo & XMMINFO_WRITED ) { - GPR_DEL_CONST(_Rd_); - } - - // add needed - if( xmminfo & (XMMINFO_READLO|XMMINFO_WRITELO) ) { - _addNeededGPRtoXMMreg(XMMGPR_LO); - } - if( xmminfo & (XMMINFO_READHI|XMMINFO_WRITEHI) ) { - _addNeededGPRtoXMMreg(XMMGPR_HI); - } - if( xmminfo & XMMINFO_READS) _addNeededGPRtoXMMreg(_Rs_); - if( xmminfo & XMMINFO_READT) _addNeededGPRtoXMMreg(_Rt_); - if( xmminfo & XMMINFO_WRITED ) _addNeededGPRtoXMMreg(_Rd_); - - // allocate - if( xmminfo & XMMINFO_READS) { - int reg = _allocGPRtoXMMreg(-1, _Rs_, MODE_READ); - info |= PROCESS_EE_SET_S(reg)|PROCESS_EE_SETMODES(reg); - } - if( xmminfo & XMMINFO_READT) { - int reg = _allocGPRtoXMMreg(-1, _Rt_, MODE_READ); - info |= PROCESS_EE_SET_T(reg)|PROCESS_EE_SETMODET(reg); - } - - if( xmminfo & XMMINFO_WRITED ) { - int readd = MODE_WRITE|((xmminfo&XMMINFO_READD)?((xmminfo&XMMINFO_READD_LO)?(MODE_READ|MODE_READHALF):MODE_READ):0); - - int regd = _checkXMMreg(XMMTYPE_GPRREG, _Rd_, readd); - - if( regd < 0 ) { - if( !(xmminfo&XMMINFO_READD) && (xmminfo & XMMINFO_READT) && (_Rt_ == 0 || (g_pCurInstInfo->regs[_Rt_] & EEINST_LASTUSE) || !EEINST_ISLIVEXMM(_Rt_)) ) { - _freeXMMreg(EEREC_T); - _deleteMMXreg(MMX_GPR+_Rd_, 2); - xmmregs[EEREC_T].inuse = 1; - xmmregs[EEREC_T].reg = _Rd_; - xmmregs[EEREC_T].mode = readd; - regd = EEREC_T; - } - else if( !(xmminfo&XMMINFO_READD) && (xmminfo & XMMINFO_READS) && (_Rs_ == 0 || (g_pCurInstInfo->regs[_Rs_] & EEINST_LASTUSE) || !EEINST_ISLIVEXMM(_Rs_)) ) { - _freeXMMreg(EEREC_S); - _deleteMMXreg(MMX_GPR+_Rd_, 2); - xmmregs[EEREC_S].inuse = 1; - xmmregs[EEREC_S].reg = _Rd_; - xmmregs[EEREC_S].mode = readd; - regd = EEREC_S; - } - else regd = _allocGPRtoXMMreg(-1, _Rd_, readd); - } - - info |= PROCESS_EE_SET_D(regd); - } - if( xmminfo & (XMMINFO_READLO|XMMINFO_WRITELO) ) { - info |= PROCESS_EE_SET_LO(_allocGPRtoXMMreg(-1, XMMGPR_LO, ((xmminfo&XMMINFO_READLO)?MODE_READ:0)|((xmminfo&XMMINFO_WRITELO)?MODE_WRITE:0))); - info |= PROCESS_EE_LO; - } - if( xmminfo & (XMMINFO_READHI|XMMINFO_WRITEHI) ) { - info |= PROCESS_EE_SET_HI(_allocGPRtoXMMreg(-1, XMMGPR_HI, ((xmminfo&XMMINFO_READHI)?MODE_READ:0)|((xmminfo&XMMINFO_WRITEHI)?MODE_WRITE:0))); - info |= PROCESS_EE_HI; - } - return info; -} - -// EE COP1(FPU) XMM allocation code -#define _Ft_ _Rt_ -#define _Fs_ _Rd_ -#define _Fd_ _Sa_ - -#define PROCESS_EE_SETMODES_XMM(mmreg) ((xmmregs[mmreg].mode&MODE_WRITE)?PROCESS_EE_MODEWRITES:0) -#define PROCESS_EE_SETMODET_XMM(mmreg) ((xmmregs[mmreg].mode&MODE_WRITE)?PROCESS_EE_MODEWRITET:0) - -// rd = rs op rt -void eeFPURecompileCode(R5900FNPTR_INFO xmmcode, R5900FNPTR fpucode, int xmminfo) -{ - int mmregs=-1, mmregt=-1, mmregd=-1, mmregacc=-1; - int info = PROCESS_EE_XMM; - - if( xmminfo & XMMINFO_READS ) _addNeededFPtoXMMreg(_Fs_); - if( xmminfo & XMMINFO_READT ) _addNeededFPtoXMMreg(_Ft_); - if( xmminfo & (XMMINFO_WRITED|XMMINFO_READD) ) _addNeededFPtoXMMreg(_Fd_); - if( xmminfo & (XMMINFO_WRITEACC|XMMINFO_READACC) ) _addNeededFPACCtoXMMreg(); - - if( xmminfo & XMMINFO_READT ) { - if( g_pCurInstInfo->fpuregs[_Ft_] & EEINST_LASTUSE ) mmregt = _checkXMMreg(XMMTYPE_FPREG, _Ft_, MODE_READ); - else mmregt = _allocFPtoXMMreg(-1, _Ft_, MODE_READ); - } - - if( xmminfo & XMMINFO_READS ) { - if( ( !(xmminfo & XMMINFO_READT) || (mmregt >= 0) ) && (g_pCurInstInfo->fpuregs[_Fs_] & EEINST_LASTUSE) ) { - mmregs = _checkXMMreg(XMMTYPE_FPREG, _Fs_, MODE_READ); - } - else mmregs = _allocFPtoXMMreg(-1, _Fs_, MODE_READ); - } - - if( mmregs >= 0 ) info |= PROCESS_EE_SETMODES_XMM(mmregs); - if( mmregt >= 0 ) info |= PROCESS_EE_SETMODET_XMM(mmregt); - - if( xmminfo & XMMINFO_READD ) { - assert( xmminfo & XMMINFO_WRITED ); - mmregd = _allocFPtoXMMreg(-1, _Fd_, MODE_READ); - } - - if( xmminfo & XMMINFO_READACC ) { - if( !(xmminfo&XMMINFO_WRITEACC) && (g_pCurInstInfo->fpuregs[_Ft_] & EEINST_LASTUSE) ) - mmregacc = _checkXMMreg(XMMTYPE_FPACC, 0, MODE_READ); - else mmregacc = _allocFPACCtoXMMreg(-1, MODE_READ); - } - - if( xmminfo & XMMINFO_WRITEACC ) { - - // check for last used, if so don't alloc a new XMM reg - int readacc = MODE_WRITE|((xmminfo&XMMINFO_READACC)?MODE_READ:0); - - mmregacc = _checkXMMreg(XMMTYPE_FPACC, 0, readacc); - - if( mmregacc < 0 ) { - if( (xmminfo&XMMINFO_READT) && mmregt >= 0 && (FPUINST_LASTUSE(_Ft_) || !FPUINST_ISLIVE(_Ft_)) ) { - if( FPUINST_ISLIVE(_Ft_) ) { - _freeXMMreg(mmregt); - info &= ~PROCESS_EE_MODEWRITET; - } - _deleteMMXreg(MMX_FPU+XMMFPU_ACC, 2); - xmmregs[mmregt].inuse = 1; - xmmregs[mmregt].reg = 0; - xmmregs[mmregt].mode = readacc; - xmmregs[mmregt].type = XMMTYPE_FPACC; - mmregacc = mmregt; - } - else if( (xmminfo&XMMINFO_READS) && mmregs >= 0 && (FPUINST_LASTUSE(_Fs_) || !FPUINST_ISLIVE(_Fs_)) ) { - if( FPUINST_ISLIVE(_Fs_) ) { - _freeXMMreg(mmregs); - info &= ~PROCESS_EE_MODEWRITES; - } - _deleteMMXreg(MMX_FPU+XMMFPU_ACC, 2); - xmmregs[mmregs].inuse = 1; - xmmregs[mmregs].reg = 0; - xmmregs[mmregs].mode = readacc; - xmmregs[mmregs].type = XMMTYPE_FPACC; - mmregacc = mmregs; - } - else mmregacc = _allocFPACCtoXMMreg(-1, readacc); - } - - xmmregs[mmregacc].mode |= MODE_WRITE; - } - else if( xmminfo & XMMINFO_WRITED ) { - // check for last used, if so don't alloc a new XMM reg - int readd = MODE_WRITE|((xmminfo&XMMINFO_READD)?MODE_READ:0); - if( xmminfo&XMMINFO_READD ) mmregd = _allocFPtoXMMreg(-1, _Fd_, readd); - else mmregd = _checkXMMreg(XMMTYPE_FPREG, _Fd_, readd); - - if( mmregd < 0 ) { - if( (xmminfo&XMMINFO_READT) && mmregt >= 0 && (FPUINST_LASTUSE(_Ft_) || !FPUINST_ISLIVE(_Ft_)) ) { - if( FPUINST_ISLIVE(_Ft_) ) { - _freeXMMreg(mmregt); - info &= ~PROCESS_EE_MODEWRITET; - } - _deleteMMXreg(MMX_FPU+_Fd_, 2); - xmmregs[mmregt].inuse = 1; - xmmregs[mmregt].reg = _Fd_; - xmmregs[mmregt].mode = readd; - mmregd = mmregt; - } - else if( (xmminfo&XMMINFO_READS) && mmregs >= 0 && (FPUINST_LASTUSE(_Fs_) || !FPUINST_ISLIVE(_Fs_)) ) { - if( FPUINST_ISLIVE(_Fs_) ) { - _freeXMMreg(mmregs); - info &= ~PROCESS_EE_MODEWRITES; - } - _deleteMMXreg(MMX_FPU+_Fd_, 2); - xmmregs[mmregs].inuse = 1; - xmmregs[mmregs].reg = _Fd_; - xmmregs[mmregs].mode = readd; - mmregd = mmregs; - } - else if( (xmminfo&XMMINFO_READACC) && mmregacc >= 0 && (FPUINST_LASTUSE(XMMFPU_ACC) || !FPUINST_ISLIVE(XMMFPU_ACC)) ) { - if( FPUINST_ISLIVE(XMMFPU_ACC) ) - _freeXMMreg(mmregacc); - _deleteMMXreg(MMX_FPU+_Fd_, 2); - xmmregs[mmregacc].inuse = 1; - xmmregs[mmregacc].reg = _Fd_; - xmmregs[mmregacc].mode = readd; - xmmregs[mmregacc].type = XMMTYPE_FPREG; - mmregd = mmregacc; - } - else mmregd = _allocFPtoXMMreg(-1, _Fd_, readd); - } - } - - assert( mmregs >= 0 || mmregt >= 0 || mmregd >= 0 || mmregacc >= 0 ); - - if( xmminfo & XMMINFO_WRITED ) { - assert( mmregd >= 0 ); - info |= PROCESS_EE_SET_D(mmregd); - } - if( xmminfo & (XMMINFO_WRITEACC|XMMINFO_READACC) ) { - if( mmregacc >= 0 ) info |= PROCESS_EE_SET_ACC(mmregacc)|PROCESS_EE_ACC; - else assert( !(xmminfo&XMMINFO_WRITEACC)); - } - - if( xmminfo & XMMINFO_READS ) { - if( mmregs >= 0 ) info |= PROCESS_EE_SET_S(mmregs)|PROCESS_EE_S; - } - if( xmminfo & XMMINFO_READT ) { - if( mmregt >= 0 ) info |= PROCESS_EE_SET_T(mmregt)|PROCESS_EE_T; - } - - // at least one must be in xmm - if( (xmminfo & (XMMINFO_READS|XMMINFO_READT)) == (XMMINFO_READS|XMMINFO_READT) ) { - assert( mmregs >= 0 || mmregt >= 0 ); - } - - xmmcode(info); - _clearNeededXMMregs(); -} - -#undef _Ft_ -#undef _Fs_ -#undef _Fd_ - -//////////////////////////////////////////////////// -u32 g_sseMXCSR = DEFAULT_sseMXCSR; -u32 g_sseVUMXCSR = DEFAULT_sseVUMXCSR; - -void SetCPUState(u32 sseMXCSR, u32 sseVUMXCSR) -{ - //Msgbox::Alert("SetCPUState: Config.sseMXCSR = %x; Config.sseVUMXCSR = %x \n", Config.sseMXCSR, Config.sseVUMXCSR); - // SSE STATE // - // WARNING: do not touch unless you know what you are doing - - sseMXCSR &= 0xffff; // clear the upper 16 bits since they shouldn't be set - sseVUMXCSR &= 0xffff; - - if( !cpucaps.hasStreamingSIMD2Extensions ) - { - // SSE1 cpus do not support Denormals Are Zero flag (throws an exception - // if we don't mask them off) - - sseMXCSR &= ~0x0040; - sseVUMXCSR &= ~0x0040; - } - - g_sseMXCSR = sseMXCSR; - g_sseVUMXCSR = sseVUMXCSR; - // do NOT set Denormals-Are-Zero flag (charlie and chocfac messes up) - // Update 11/05/08 - Doesnt seem to effect it anymore, for the speed boost, its on :p - //g_sseMXCSR = 0x9f80; // changing the rounding mode to 0x2000 (near) kills grandia III! - // changing the rounding mode to 0x0000 or 0x4000 totally kills gitaroo - // so... grandia III wins (you can change individual games with the 'roundmode' patch command) - -#ifdef _MSC_VER - __asm ldmxcsr g_sseMXCSR; // set the new sse control -#else - __asm__("ldmxcsr %0" : : "m"(g_sseMXCSR) ); -#endif - //g_sseVUMXCSR = g_sseMXCSR|0x6000; -} - -#define REC_CACHEMEM 0x01000000 -void __fastcall dyna_block_discard(u32 start,u32 sz); +static const int REC_CACHEMEM = 0x01000000; +static void __fastcall dyna_block_discard(u32 start,u32 sz); static void recInit() { @@ -1730,11 +671,9 @@ void recExecuteBlock( void ) { } //////////////////////////////////////////////////// -extern u32 g_nextBranchCycle; -u32 g_lastpc = 0; -u32 g_EEDispatchTemp; -u32 s_pCurBlock_ltime; +static u32 g_lastpc = 0; +static u32 g_EEDispatchTemp; #ifdef _MSC_VER @@ -1885,84 +824,12 @@ recomp: } } -#ifdef PCSX2_DEVBUILD -__declspec(naked) void _StartPerfCounter() -{ - __asm { - push eax - push ebx - push ecx - - rdtsc - mov dword ptr [offset lbase], eax - mov dword ptr [offset lbase + 4], edx - - pop ecx - pop ebx - pop eax - ret - } -} - -__declspec(naked) void _StopPerfCounter() -{ - __asm { - push eax - push ebx - push ecx - - rdtsc - - sub eax, dword ptr [offset lbase] - sbb edx, dword ptr [offset lbase + 4] - mov ecx, s_pCurBlock_ltime - add eax, dword ptr [ecx] - adc edx, dword ptr [ecx + 4] - mov dword ptr [ecx], eax - mov dword ptr [ecx + 4], edx - pop ecx - pop ebx - pop eax - ret - } -} - -#endif // PCSX2_DEVBUILD - #else // _MSC_VER // Linux uses an assembly version of these routines. -#ifdef __LINUX__ extern "C" { -#endif extern void Dispatcher(); extern void DispatcherClear(); extern void DispatcherReg(); -#ifdef __LINUX__ -} -#endif -extern void _StartPerfCounter(); -extern void _StopPerfCounter(); - -#endif - -#ifdef PCSX2_DEVBUILD -void StartPerfCounter() -{ -#ifdef PCSX2_DEVBUILD -// if( s_startcount ) { -// CALLFunc((uptr)_StartPerfCounter); -// } -#endif -} - -void StopPerfCounter() -{ -#ifdef PCSX2_DEVBUILD -// if( s_startcount ) { -// MOV32ItoM((uptr)&s_pCurBlock_ltime, (u32)&s_pCurBlockEx->ltime); -// CALLFunc((uptr)_StopPerfCounter); -// } -#endif } #endif @@ -1975,7 +842,7 @@ void recClear( u32 Addr, u32 Size ) } } -#define EE_MIN_BLOCK_BYTES 15 +static const int EE_MIN_BLOCK_BYTES = 15; void recClearMem(BASEBLOCK* p) { @@ -2050,6 +917,14 @@ void recClearMem(BASEBLOCK* p) pexblock->startpc = 0; } +void REC_CLEARM( u32 mem ) +{ + if ((mem) < maxrecmem && recLUT[(mem) >> 16]) { + BASEBLOCK* p = PC_GETBLOCK(mem); + if( *(u32*)p ) recClearMem(p); + } +} + // check for end of bios void CheckForBIOSEnd() { @@ -2284,13 +1159,6 @@ static u32 eeScaleBlockCycles() static void iBranchTest(u32 newpc, u32 cpuBranch) { -#ifdef PCSX2_DEVBUILD -// if( s_startcount ) { -// StopPerfCounter(); -// ADD32ItoM( (u32)&s_pCurBlockEx->visited, 1 ); -// } -#endif - #ifdef _DEBUG //CALLFunc((uptr)testfpu); #endif @@ -2315,7 +1183,7 @@ static void iBranchTest(u32 newpc, u32 cpuBranch) x86SetJ8( j8Ptr[0] ); } -namespace EE { namespace Dynarec { namespace OpcodeImpl +namespace OpcodeImpl { //////////////////////////////////////////////////// @@ -2327,9 +1195,7 @@ REC_SYS(COP2); void recCOP2( void ) { - // This CPU_LOG call triggers a "Source Log Stack Corruption Detected." - // error and crashes pcsx2 if called here. - //CPU_LOG( "Recompiling COP2:%s\n", disR5900Current.getString() ); + //CPU_LOG( "Recompiling COP2: %s\n", disR5900Current.getCString() ); recCOP22( ); } @@ -2340,7 +1206,7 @@ void recSYSCALL( void ) { MOV32ItoM( (uptr)&cpuRegs.code, cpuRegs.code ); MOV32ItoM( (uptr)&cpuRegs.pc, pc ); iFlushCall(FLUSH_NODESTROY); - CALLFunc( (uptr)Interpreter::OpcodeImpl::SYSCALL ); + CALLFunc( (uptr)R5900::Interpreter::OpcodeImpl::SYSCALL ); CMP32ItoM((uptr)&cpuRegs.pc, pc); j8Ptr[0] = JE8(0); @@ -2355,7 +1221,7 @@ void recBREAK( void ) { MOV32ItoM( (uptr)&cpuRegs.code, cpuRegs.code ); MOV32ItoM( (uptr)&cpuRegs.pc, pc ); iFlushCall(FLUSH_EVERYTHING); - CALLFunc( (uptr)EE::Interpreter::OpcodeImpl::BREAK ); + CALLFunc( (uptr)R5900::Interpreter::OpcodeImpl::BREAK ); CMP32ItoM((uptr)&cpuRegs.pc, pc); j8Ptr[0] = JE8(0); @@ -2459,7 +1325,7 @@ void recMTSAH( void ) } } -}}} // end Namespace EE::Dynarec::OpcodeImpl +} // end Namespace Dynarec::R5900::OpcodeImpl static void checkcodefn() { @@ -2475,11 +1341,6 @@ static void checkcodefn() assert(0); } -void checkpchanged(u32 startpc) -{ - assert(0); -} - //#ifdef _DEBUG //#define CHECK_XMMCHANGED() CALLFunc((uptr)checkxmmchanged); //#else @@ -2574,7 +1435,6 @@ void recompileNextInstruction(int delayslot) // x86SetJ8( j8Ptr[ 0 ] ); // x86SetJ8( j8Ptr[ 1 ] ); // PUSH32I(s_pCurBlockEx->startpc); -// CALLFunc((uptr)checkpchanged); // ADD32ItoR(ESP, 4); // x86SetJ8( j8Ptr[ 2 ] ); // } @@ -2607,7 +1467,7 @@ void recompileNextInstruction(int delayslot) } } - const EE::OPCODE& opcode = EE::GetCurrentInstruction(); + const OPCODE& opcode = GetCurrentInstruction(); // peephole optimizations if( g_pCurInstInfo->info & EEINSTINFO_COREC ) { @@ -2615,21 +1475,21 @@ void recompileNextInstruction(int delayslot) #ifdef PCSX2_VIRTUAL_MEM if( g_pCurInstInfo->numpeeps > 1 ) { switch(_Opcode_) { - case 30: EE::Dynarec::OpcodeImpl::recLQ_coX(g_pCurInstInfo->numpeeps); break; - case 31: EE::Dynarec::OpcodeImpl::recSQ_coX(g_pCurInstInfo->numpeeps); break; - case 49: EE::Dynarec::OpcodeImpl::recLWC1_coX(g_pCurInstInfo->numpeeps); break; - case 57: EE::Dynarec::OpcodeImpl::recSWC1_coX(g_pCurInstInfo->numpeeps); break; - case 55: EE::Dynarec::OpcodeImpl::recLD_coX(g_pCurInstInfo->numpeeps); break; - case 63: EE::Dynarec::OpcodeImpl::recSD_coX(g_pCurInstInfo->numpeeps, 1); break; //not sure if should be set to 1 or 0; looks like "1" handles alignment, so i'm going with that for now - default: - assert(0); + case 30: OpcodeImpl::recLQ_coX(g_pCurInstInfo->numpeeps); break; + case 31: OpcodeImpl::recSQ_coX(g_pCurInstInfo->numpeeps); break; + case 49: OpcodeImpl::recLWC1_coX(g_pCurInstInfo->numpeeps); break; + case 57: OpcodeImpl::recSWC1_coX(g_pCurInstInfo->numpeeps); break; + case 55: OpcodeImpl::recLD_coX(g_pCurInstInfo->numpeeps); break; + case 63: OpcodeImpl::recSD_coX(g_pCurInstInfo->numpeeps, 1); break; //not sure if should be set to 1 or 0; looks like "1" handles alignment, so i'm going with that for now + + jNO_DEFAULT } pc += g_pCurInstInfo->numpeeps*4; s_nBlockCycles += (g_pCurInstInfo->numpeeps+1) * opcode.cycles; g_pCurInstInfo += g_pCurInstInfo->numpeeps; } else { - EE::Dynarec::recBSC_co[_Opcode_](); + recBSC_co[_Opcode_](); pc += 4; g_pCurInstInfo++; s_nBlockCycles += opcode.cycles*2; @@ -2712,74 +1572,6 @@ void recompileNextInstruction(int delayslot) // } //} -//////////////////////////////////////////////////// -#include "R3000A.h" -#include "PsxCounters.h" -#include "PsxMem.h" -extern tIPU_BP g_BP; - -extern u32 psxdump; -extern void iDumpPsxRegisters(u32 startpc, u32 temp); -extern Counter counters[6]; -extern int rdram_devices; // put 8 for TOOL and 2 for PS2 and PSX -extern int rdram_sdevid; - -void iDumpRegisters(u32 startpc, u32 temp) -{ -// [TODO] fixme : thie code is broken and has no labels. Needs a rewrite to be useful. - -#if 0 - - int i; - const char* pstr;// = temp ? "t" : ""; - const u32 dmacs[] = {0x8000, 0x9000, 0xa000, 0xb000, 0xb400, 0xc000, 0xc400, 0xc800, 0xd000, 0xd400 }; - extern const char *disRNameGPR[]; - const char* psymb; - - if (temp) - pstr = "t"; - else - pstr = ""; - - psymb = disR5900GetSym(startpc); - - if( psymb != NULL ) - __Log("%sreg(%s): %x %x c:%x\n", pstr, psymb, startpc, cpuRegs.interrupt, cpuRegs.cycle); - else - __Log("%sreg: %x %x c:%x\n", pstr, startpc, cpuRegs.interrupt, cpuRegs.cycle); - for(i = 1; i < 32; ++i) __Log("%s: %x_%x_%x_%x\n", disRNameGPR[i], cpuRegs.GPR.r[i].UL[3], cpuRegs.GPR.r[i].UL[2], cpuRegs.GPR.r[i].UL[1], cpuRegs.GPR.r[i].UL[0]); - //for(i = 0; i < 32; i+=4) __Log("cp%d: %x_%x_%x_%x\n", i, cpuRegs.CP0.r[i], cpuRegs.CP0.r[i+1], cpuRegs.CP0.r[i+2], cpuRegs.CP0.r[i+3]); - //for(i = 0; i < 32; ++i) __Log("%sf%d: %f %x\n", pstr, i, fpuRegs.fpr[i].f, fpuRegs.fprc[i]); - //for(i = 1; i < 32; ++i) __Log("%svf%d: %f %f %f %f, vi: %x\n", pstr, i, VU0.VF[i].F[3], VU0.VF[i].F[2], VU0.VF[i].F[1], VU0.VF[i].F[0], VU0.VI[i].UL); - for(i = 0; i < 32; ++i) __Log("%sf%d: %x %x\n", pstr, i, fpuRegs.fpr[i].UL, fpuRegs.fprc[i]); - for(i = 1; i < 32; ++i) __Log("%svf%d: %x %x %x %x, vi: %x\n", pstr, i, VU0.VF[i].UL[3], VU0.VF[i].UL[2], VU0.VF[i].UL[1], VU0.VF[i].UL[0], VU0.VI[i].UL); - __Log("%svfACC: %x %x %x %x\n", pstr, VU0.ACC.UL[3], VU0.ACC.UL[2], VU0.ACC.UL[1], VU0.ACC.UL[0]); - __Log("%sLO: %x_%x_%x_%x, HI: %x_%x_%x_%x\n", pstr, cpuRegs.LO.UL[3], cpuRegs.LO.UL[2], cpuRegs.LO.UL[1], cpuRegs.LO.UL[0], - cpuRegs.HI.UL[3], cpuRegs.HI.UL[2], cpuRegs.HI.UL[1], cpuRegs.HI.UL[0]); - __Log("%sCycle: %x %x, Count: %x\n", pstr, cpuRegs.cycle, g_nextBranchCycle, cpuRegs.CP0.n.Count); - iDumpPsxRegisters(psxRegs.pc, temp); - - __Log("f410,30,40: %x %x %x, %d %d\n", psHu32(0xf410), psHu32(0xf430), psHu32(0xf440), rdram_sdevid, rdram_devices); - __Log("cyc11: %x %x; vu0: %x, vu1: %x\n", cpuRegs.sCycle[1], cpuRegs.eCycle[1], VU0.cycle, VU1.cycle); - - __Log("%scounters: %x %x; psx: %x %x\n", pstr, nextsCounter, nextCounter, psxNextsCounter, psxNextCounter); - for(i = 0; i < 4; ++i) { - __Log("eetimer%d: count: %x mode: %x target: %x %x; %x %x; %x %x %x %x\n", i, - counters[i].count, counters[i].mode, counters[i].target, counters[i].hold, counters[i].rate, - counters[i].interrupt, counters[i].Cycle, counters[i].sCycle, counters[i].CycleT, counters[i].sCycleT); - } - __Log("VIF0_STAT = %x, VIF1_STAT = %x\n", psHu32(0x3800), psHu32(0x3C00)); - __Log("ipu %x %x %x %x; bp: %x %x %x %x\n", psHu32(0x2000), psHu32(0x2010), psHu32(0x2020), psHu32(0x2030), g_BP.BP, g_BP.bufferhasnew, g_BP.FP, g_BP.IFC); - __Log("gif: %x %x %x\n", psHu32(0x3000), psHu32(0x3010), psHu32(0x3020)); - for(i = 0; i < ARRAYSIZE(dmacs); ++i) { - DMACh* p = (DMACh*)(PS2MEM_HW+dmacs[i]); - __Log("dma%d c%x m%x q%x t%x s%x\n", i, p->chcr, p->madr, p->qwc, p->tadr, p->sadr); - } - __Log("dmac %x %x %x %x\n", psHu32(DMAC_CTRL), psHu32(DMAC_STAT), psHu32(DMAC_RBSR), psHu32(DMAC_RBOR)); - __Log("intc %x %x\n", psHu32(INTC_STAT), psHu32(INTC_MASK)); - __Log("sif: %x %x %x %x %x\n", psHu32(0xf200), psHu32(0xf220), psHu32(0xf230), psHu32(0xf240), psHu32(0xf260)); -#endif -} extern u32 psxdump; @@ -2811,8 +1603,6 @@ void badespfn() { assert(0); } -#define OPTIMIZE_COP2 0//CHECK_VU0REC - void __fastcall dyna_block_discard(u32 start,u32 sz) { #ifdef _MSC_VER @@ -2829,6 +1619,7 @@ void __fastcall dyna_block_discard(u32 start,u32 sz) #endif return; } + void recRecompile( u32 startpc ) { u32 i = 0; @@ -3110,7 +1901,7 @@ StartRecomp: if( i < s_nEndBlock-4 && recompileCodeSafe(i) ) { u32 curcode = cpuRegs.code; u32 nextcode = *(u32*)PSM(i+4); - if( _eeIsLoadStoreCoIssue(curcode, nextcode) && EE::Dynarec::recBSC_co[curcode>>26] != NULL ) { + if( _eeIsLoadStoreCoIssue(curcode, nextcode) && recBSC_co[curcode>>26] != NULL ) { // rs has to be the same, and cannot be just written if( ((curcode >> 21) & 0x1F) == ((nextcode >> 21) & 0x1F) && !_eeLoadWritesRs(curcode) ) { @@ -3214,18 +2005,6 @@ StartRecomp: } } - // perf counters // -#ifdef PCSX2_DEVBUILD -// s_startcount = 0; -// if( pc+32 < s_nEndBlock ) { -// // only blocks with more than 8 insts -// //PUSH32I((uptr)&lbase); -// //CALLFunc((uptr)QueryPerformanceCounter); -// lbase.QuadPart = GetCPUTick(); -// s_startcount = 1; -// } -#endif - #ifdef _DEBUG // dump code for(i = 0; i < ARRAYSIZE(s_recblocks); ++i) { @@ -3397,6 +2176,14 @@ StartRecomp: } } +} } // end namespace Dynarec::R5900 + +using namespace Dynarec; +using namespace Dynarec::R5900; + +namespace R5900 +{ + R5900cpu recCpu = { recInit, recReset, @@ -3412,3 +2199,5 @@ R5900cpu recCpu = { recClearVU1, recShutdown }; + +} \ No newline at end of file diff --git a/pcsx2/x86/ix86-32/iR5900Arit.cpp b/pcsx2/x86/ix86-32/iR5900Arit.cpp index 79abf26dea..5cd7a241f2 100644 --- a/pcsx2/x86/ix86-32/iR5900Arit.cpp +++ b/pcsx2/x86/ix86-32/iR5900Arit.cpp @@ -29,10 +29,11 @@ #pragma warning(disable:4761) #endif -namespace EE { namespace Dynarec { namespace OpcodeImpl +namespace Dynarec { +namespace R5900 { +namespace OpcodeImpl { - /********************************************************* * Register arithmetic * * Format: OP rd, rs, rt * diff --git a/pcsx2/x86/ix86-32/iR5900AritImm.cpp b/pcsx2/x86/ix86-32/iR5900AritImm.cpp index 14fe22b3b2..78cba0b8e0 100644 --- a/pcsx2/x86/ix86-32/iR5900AritImm.cpp +++ b/pcsx2/x86/ix86-32/iR5900AritImm.cpp @@ -23,21 +23,14 @@ #include "ix86/ix86.h" #include "iR5900.h" -#ifdef _WIN32 -#pragma warning(disable:4244) -#pragma warning(disable:4761) -#endif +//#ifdef _WIN32 +//#pragma warning(disable:4244) +//#pragma warning(disable:4761) +//#endif -#ifdef ARITHMETICIMM_RECOMPILE -extern void LogicalOpRtoR(x86MMXRegType to, x86MMXRegType from, int op); -extern void LogicalOpMtoR(x86MMXRegType to, u32 from, int op); -extern void LogicalOp32RtoM(u32 to, x86IntRegType from, int op); -extern void LogicalOp32MtoR(x86IntRegType to, u32 from, int op); -extern void LogicalOp32ItoR(x86IntRegType to, u32 from, int op); -extern void LogicalOp32ItoM(u32 to, u32 from, int op); -#endif - -namespace EE { namespace Dynarec { namespace OpcodeImpl +namespace Dynarec { +namespace R5900 { +namespace OpcodeImpl { /********************************************************* diff --git a/pcsx2/x86/ix86-32/iR5900Branch.cpp b/pcsx2/x86/ix86-32/iR5900Branch.cpp index 02391aad0f..87260bb997 100644 --- a/pcsx2/x86/ix86-32/iR5900Branch.cpp +++ b/pcsx2/x86/ix86-32/iR5900Branch.cpp @@ -26,14 +26,15 @@ #include "iR5900.h" -#ifdef _WIN32 -#pragma warning(disable:4244) -#pragma warning(disable:4761) -#endif +//#ifdef _WIN32 +//#pragma warning(disable:4244) +//#pragma warning(disable:4761) +//#endif -namespace EE { namespace Dynarec { namespace OpcodeImpl +namespace Dynarec { +namespace R5900 { +namespace OpcodeImpl { - /********************************************************* * Register branch logic * * Format: OP rs, rt, offset * diff --git a/pcsx2/x86/ix86-32/iR5900Jump.cpp b/pcsx2/x86/ix86-32/iR5900Jump.cpp index 666bbb2ef4..9d1d954ef8 100644 --- a/pcsx2/x86/ix86-32/iR5900Jump.cpp +++ b/pcsx2/x86/ix86-32/iR5900Jump.cpp @@ -30,7 +30,9 @@ #pragma warning(disable:4761) #endif -namespace EE { namespace Dynarec { namespace OpcodeImpl +namespace Dynarec { +namespace R5900 { +namespace OpcodeImpl { /********************************************************* diff --git a/pcsx2/x86/ix86-32/iR5900LoadStore.cpp b/pcsx2/x86/ix86-32/iR5900LoadStore.cpp index 72c300da4c..1c37eefccb 100644 --- a/pcsx2/x86/ix86-32/iR5900LoadStore.cpp +++ b/pcsx2/x86/ix86-32/iR5900LoadStore.cpp @@ -28,11 +28,12 @@ #pragma warning(disable:4761) #endif -namespace EE { namespace Dynarec { +namespace Dynarec { // Implemented at the bottom of the module: void SetFastMemory(int bSetFast); +namespace R5900 { namespace OpcodeImpl { @@ -1189,7 +1190,7 @@ void recLDL( void ) MOV32ItoM( (int)&cpuRegs.code, cpuRegs.code ); MOV32ItoM( (int)&cpuRegs.pc, pc ); - CALLFunc( (int)Interpreter::OpcodeImpl::LDL ); + CALLFunc( (int)R5900::Interpreter::OpcodeImpl::LDL ); } //////////////////////////////////////////////////// @@ -1214,7 +1215,7 @@ void recLDR( void ) MOV32ItoM( (int)&cpuRegs.code, cpuRegs.code ); MOV32ItoM( (int)&cpuRegs.pc, pc ); - CALLFunc( (int)Interpreter::OpcodeImpl::LDR ); + CALLFunc( (int)R5900::Interpreter::OpcodeImpl::LDR ); } //////////////////////////////////////////////////// @@ -2105,7 +2106,6 @@ void recStore(int bit, u32 imm, int align) if( GPR_IS_CONST1( _Rs_ ) ) { u32 addr = g_cpuConstRegs[_Rs_].UL[0]+imm; int doclear = 0; - StopPerfCounter(); switch(bit) { case 8: if( GPR_IS_CONST1(_Rt_) ) doclear = recMemConstWrite8(addr, MEM_EECONSTTAG|(_Rt_<<16)); @@ -2183,8 +2183,6 @@ void recStore(int bit, u32 imm, int align) break; } - - StartPerfCounter(); } else #endif @@ -2218,9 +2216,7 @@ void recStore(int bit, u32 imm, int align) SET_HWLOC_R5900(); - StopPerfCounter(); recStore_call(bit, _Rt_, s_nAddMemOffset); - StartPerfCounter(); if( s_bCachingMem & 2 ) x86SetJ32(j32Ptr[5]); else x86SetJ8(j8Ptr[2]); @@ -2731,7 +2727,7 @@ void recSDL( void ) MOV32ItoM( (int)&cpuRegs.code, cpuRegs.code ); MOV32ItoM( (int)&cpuRegs.pc, pc ); - CALLFunc( (int)Interpreter::OpcodeImpl::SDL ); + CALLFunc( (int)R5900::Interpreter::OpcodeImpl::SDL ); } //////////////////////////////////////////////////// @@ -2755,7 +2751,7 @@ void recSDR( void ) MOV32ItoM( (int)&cpuRegs.code, cpuRegs.code ); MOV32ItoM( (int)&cpuRegs.pc, pc ); - CALLFunc( (int)Interpreter::OpcodeImpl::SDR ); + CALLFunc( (int)R5900::Interpreter::OpcodeImpl::SDR ); } //////////////////////////////////////////////////// @@ -4475,10 +4471,11 @@ void recSQC2( void ) #endif -} // end namespace OpcodeImpl +} } // end namespace R5900::OpcodeImpl + +using namespace R5900::OpcodeImpl; #ifdef PCSX2_VIRTUAL_MEM - using namespace OpcodeImpl; #ifndef LOADSTORE_RECOMPILE void SetFastMemory(int bSetFast) {} @@ -4505,4 +4502,4 @@ void recSQC2( void ) void SetFastMemory(int bSetFast) {} #endif -} } +} diff --git a/pcsx2/x86/ix86-32/iR5900Move.cpp b/pcsx2/x86/ix86-32/iR5900Move.cpp index b9a48872a4..3f6a3d2a5b 100644 --- a/pcsx2/x86/ix86-32/iR5900Move.cpp +++ b/pcsx2/x86/ix86-32/iR5900Move.cpp @@ -29,7 +29,9 @@ #pragma warning(disable:4761) #endif -namespace EE { namespace Dynarec { namespace OpcodeImpl +namespace Dynarec { +namespace R5900 { +namespace OpcodeImpl { /********************************************************* diff --git a/pcsx2/x86/ix86-32/iR5900MultDiv.cpp b/pcsx2/x86/ix86-32/iR5900MultDiv.cpp index 8a3c65434e..9398886aa6 100644 --- a/pcsx2/x86/ix86-32/iR5900MultDiv.cpp +++ b/pcsx2/x86/ix86-32/iR5900MultDiv.cpp @@ -28,7 +28,9 @@ #pragma warning(disable:4761) #endif -namespace EE { namespace Dynarec { namespace OpcodeImpl +namespace Dynarec { +namespace R5900 { +namespace OpcodeImpl { /********************************************************* diff --git a/pcsx2/x86/ix86-32/iR5900Shift.cpp b/pcsx2/x86/ix86-32/iR5900Shift.cpp index f2169c5e18..660297611c 100644 --- a/pcsx2/x86/ix86-32/iR5900Shift.cpp +++ b/pcsx2/x86/ix86-32/iR5900Shift.cpp @@ -29,7 +29,9 @@ #pragma warning(disable:4761) #endif -namespace EE { namespace Dynarec { namespace OpcodeImpl +namespace Dynarec { +namespace R5900 { +namespace OpcodeImpl { /********************************************************* diff --git a/pcsx2/x86/ix86-32/iR5900Templates.cpp b/pcsx2/x86/ix86-32/iR5900Templates.cpp new file mode 100644 index 0000000000..56ad46fbc3 --- /dev/null +++ b/pcsx2/x86/ix86-32/iR5900Templates.cpp @@ -0,0 +1,1011 @@ +/* Pcsx2 - Pc Ps2 Emulator + * Copyright (C) 2002-2008 Pcsx2 Team + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA + */ + + +#include "PrecompiledHeader.h" + +#include "Common.h" +#include "Memory.h" +#include "InterTables.h" +#include "ix86/ix86.h" +#include "iR5900.h" +#include "iMMI.h" +#include "iFPU.h" +#include "iCP0.h" +#include "iVUmicro.h" +#include "VU.h" +#include "VUmicro.h" + +#include "iVUzerorec.h" + +#include "vtlb.h" + +namespace Dynarec { +namespace R5900 +{ + +//////////////////// +// Code Templates // +//////////////////// + +void CHECK_SAVE_REG(int reg) +{ + if( s_saveConstGPRreg == 0xffffffff ) { + if( GPR_IS_CONST1(reg) ) { + s_saveConstGPRreg = reg; + s_ConstGPRreg = g_cpuConstRegs[reg]; + } + } + else { + assert( s_saveConstGPRreg == 0 || s_saveConstGPRreg == reg ); + } +} + +void _eeProcessHasLive(int reg, int signext) +{ + g_cpuPrevRegHasLive1 = g_cpuRegHasLive1; + g_cpuRegHasLive1 |= 1<regs[reg]&EEINST_LASTUSE) ) { + if( usemmx ) return _allocMMXreg(-1, MMX_GPR+reg, mode); + return _allocGPRtoXMMreg(-1, reg, mode); + } + + return -1; +} + +#define PROCESS_EE_SETMODES(mmreg) ((mmxregs[mmreg].mode&MODE_WRITE)?PROCESS_EE_MODEWRITES:0) +#define PROCESS_EE_SETMODET(mmreg) ((mmxregs[mmreg].mode&MODE_WRITE)?PROCESS_EE_MODEWRITET:0) + +// ignores XMMINFO_READS, XMMINFO_READT, and XMMINFO_READD_LO from xmminfo +// core of reg caching +void eeRecompileCode0(R5900FNPTR constcode, R5900FNPTR_INFO constscode, R5900FNPTR_INFO consttcode, R5900FNPTR_INFO noconstcode, int xmminfo) +{ + int mmreg1, mmreg2, mmreg3, mmtemp, moded; + + if ( ! _Rd_ && (xmminfo&XMMINFO_WRITED) ) return; + + if( xmminfo&XMMINFO_WRITED) { + CHECK_SAVE_REG(_Rd_); + _eeProcessHasLive(_Rd_, 0); + EEINST_RESETSIGNEXT(_Rd_); + } + + if( GPR_IS_CONST2(_Rs_, _Rt_) ) { + if( xmminfo & XMMINFO_WRITED ) { + _deleteMMXreg(MMX_GPR+_Rd_, 2); + _deleteGPRtoXMMreg(_Rd_, 2); + } + if( xmminfo&XMMINFO_WRITED ) GPR_SET_CONST(_Rd_); + constcode(); + return; + } + + moded = MODE_WRITE|((xmminfo&XMMINFO_READD)?MODE_READ:0); + + // test if should write mmx + if( g_pCurInstInfo->info & EEINST_MMX ) { + + if( xmminfo & (XMMINFO_READLO|XMMINFO_WRITELO) ) _addNeededMMXreg(MMX_GPR+MMX_LO); + if( xmminfo & (XMMINFO_READHI|XMMINFO_WRITEHI) ) _addNeededMMXreg(MMX_GPR+MMX_HI); + _addNeededMMXreg(MMX_GPR+_Rs_); + _addNeededMMXreg(MMX_GPR+_Rt_); + + if( GPR_IS_CONST1(_Rs_) || GPR_IS_CONST1(_Rt_) ) { + int creg = GPR_IS_CONST1(_Rs_) ? _Rs_ : _Rt_; + int vreg = creg == _Rs_ ? _Rt_ : _Rs_; + +// if(g_pCurInstInfo->regs[vreg]&EEINST_MMX) { +// mmreg1 = _allocMMXreg(-1, MMX_GPR+vreg, MODE_READ); +// _addNeededMMXreg(MMX_GPR+vreg); +// } + mmreg1 = _allocCheckGPRtoMMX(g_pCurInstInfo, vreg, MODE_READ); + + if( mmreg1 >= 0 ) { + int info = PROCESS_EE_MMX; + + if( GPR_IS_CONST1(_Rs_) ) info |= PROCESS_EE_SETMODET(mmreg1); + else info |= PROCESS_EE_SETMODES(mmreg1); + + if( xmminfo & XMMINFO_WRITED ) { + _addNeededMMXreg(MMX_GPR+_Rd_); + mmreg3 = _checkMMXreg(MMX_GPR+_Rd_, moded); + + if( !(xmminfo&XMMINFO_READD) && mmreg3 < 0 && ((g_pCurInstInfo->regs[vreg] & EEINST_LASTUSE) || !EEINST_ISLIVE64(vreg)) ) { + if( EEINST_ISLIVE64(vreg) ) { + _freeMMXreg(mmreg1); + if( GPR_IS_CONST1(_Rs_) ) info &= ~PROCESS_EE_MODEWRITET; + else info &= ~PROCESS_EE_MODEWRITES; + } + _deleteGPRtoXMMreg(_Rd_, 2); + mmxregs[mmreg1].inuse = 1; + mmxregs[mmreg1].reg = _Rd_; + mmxregs[mmreg1].mode = moded; + mmreg3 = mmreg1; + } + else if( mmreg3 < 0 ) mmreg3 = _allocMMXreg(-1, MMX_GPR+_Rd_, moded); + + info |= PROCESS_EE_SET_D(mmreg3); + } + + if( xmminfo & (XMMINFO_READLO|XMMINFO_WRITELO) ) { + mmtemp = eeProcessHILO(MMX_LO, ((xmminfo&XMMINFO_READLO)?MODE_READ:0)|((xmminfo&XMMINFO_WRITELO)?MODE_WRITE:0), 1); + if( mmtemp >= 0 ) info |= PROCESS_EE_SET_LO(mmtemp); + } + if( xmminfo & (XMMINFO_READHI|XMMINFO_WRITEHI) ) { + mmtemp = eeProcessHILO(MMX_HI, ((xmminfo&XMMINFO_READLO)?MODE_READ:0)|((xmminfo&XMMINFO_WRITELO)?MODE_WRITE:0), 1); + if( mmtemp >= 0 ) info |= PROCESS_EE_SET_HI(mmtemp); + } + + SetMMXstate(); + if( creg == _Rs_ ) constscode(info|PROCESS_EE_SET_T(mmreg1)); + else consttcode(info|PROCESS_EE_SET_S(mmreg1)); + _clearNeededMMXregs(); + if( xmminfo & XMMINFO_WRITED ) GPR_DEL_CONST(_Rd_); + return; + } + } + else { + // no const regs + mmreg1 = _allocCheckGPRtoMMX(g_pCurInstInfo, _Rs_, MODE_READ); + mmreg2 = _allocCheckGPRtoMMX(g_pCurInstInfo, _Rt_, MODE_READ); + + if( mmreg1 >= 0 || mmreg2 >= 0 ) { + int info = PROCESS_EE_MMX; + + // do it all in mmx + if( mmreg1 < 0 ) mmreg1 = _allocMMXreg(-1, MMX_GPR+_Rs_, MODE_READ); + if( mmreg2 < 0 ) mmreg2 = _allocMMXreg(-1, MMX_GPR+_Rt_, MODE_READ); + + info |= PROCESS_EE_SETMODES(mmreg1)|PROCESS_EE_SETMODET(mmreg2); + + // check for last used, if so don't alloc a new MMX reg + if( xmminfo & XMMINFO_WRITED ) { + _addNeededMMXreg(MMX_GPR+_Rd_); + mmreg3 = _checkMMXreg(MMX_GPR+_Rd_, moded); + + if( mmreg3 < 0 ) { + if( !(xmminfo&XMMINFO_READD) && ((g_pCurInstInfo->regs[_Rt_] & EEINST_LASTUSE) || !EEINST_ISLIVE64(_Rt_)) ) { + if( EEINST_ISLIVE64(_Rt_) ) { + _freeMMXreg(mmreg2); + info &= ~PROCESS_EE_MODEWRITET; + } + _deleteGPRtoXMMreg(_Rd_, 2); + mmxregs[mmreg2].inuse = 1; + mmxregs[mmreg2].reg = _Rd_; + mmxregs[mmreg2].mode = moded; + mmreg3 = mmreg2; + } + else if( !(xmminfo&XMMINFO_READD) && ((g_pCurInstInfo->regs[_Rs_] & EEINST_LASTUSE) || !EEINST_ISLIVE64(_Rs_)) ) { + if( EEINST_ISLIVE64(_Rs_) ) { + _freeMMXreg(mmreg1); + info &= ~PROCESS_EE_MODEWRITES; + } + _deleteGPRtoXMMreg(_Rd_, 2); + mmxregs[mmreg1].inuse = 1; + mmxregs[mmreg1].reg = _Rd_; + mmxregs[mmreg1].mode = moded; + mmreg3 = mmreg1; + } + else mmreg3 = _allocMMXreg(-1, MMX_GPR+_Rd_, moded); + } + + info |= PROCESS_EE_SET_D(mmreg3); + } + + if( xmminfo & (XMMINFO_READLO|XMMINFO_WRITELO) ) { + mmtemp = eeProcessHILO(MMX_LO, ((xmminfo&XMMINFO_READLO)?MODE_READ:0)|((xmminfo&XMMINFO_WRITELO)?MODE_WRITE:0), 1); + if( mmtemp >= 0 ) info |= PROCESS_EE_SET_LO(mmtemp); + } + if( xmminfo & (XMMINFO_READHI|XMMINFO_WRITEHI) ) { + mmtemp = eeProcessHILO(MMX_HI, ((xmminfo&XMMINFO_READLO)?MODE_READ:0)|((xmminfo&XMMINFO_WRITELO)?MODE_WRITE:0), 1); + if( mmtemp >= 0 ) info |= PROCESS_EE_SET_HI(mmtemp); + } + + SetMMXstate(); + noconstcode(info|PROCESS_EE_SET_S(mmreg1)|PROCESS_EE_SET_T(mmreg2)); + _clearNeededMMXregs(); + if( xmminfo & XMMINFO_WRITED ) GPR_DEL_CONST(_Rd_); + return; + } + } + + _clearNeededMMXregs(); + } + + // test if should write xmm, mirror to mmx code + if( g_pCurInstInfo->info & EEINST_XMM ) { + + if( xmminfo & (XMMINFO_READLO|XMMINFO_WRITELO) ) _addNeededGPRtoXMMreg(XMMGPR_LO); + if( xmminfo & (XMMINFO_READHI|XMMINFO_WRITEHI) ) _addNeededGPRtoXMMreg(XMMGPR_HI); + _addNeededGPRtoXMMreg(_Rs_); + _addNeededGPRtoXMMreg(_Rt_); + + if( GPR_IS_CONST1(_Rs_) || GPR_IS_CONST1(_Rt_) ) { + int creg = GPR_IS_CONST1(_Rs_) ? _Rs_ : _Rt_; + int vreg = creg == _Rs_ ? _Rt_ : _Rs_; + +// if(g_pCurInstInfo->regs[vreg]&EEINST_XMM) { +// mmreg1 = _allocGPRtoXMMreg(-1, vreg, MODE_READ); +// _addNeededGPRtoXMMreg(vreg); +// } + mmreg1 = _allocCheckGPRtoXMM(g_pCurInstInfo, vreg, MODE_READ); + + if( mmreg1 >= 0 ) { + int info = PROCESS_EE_XMM; + + if( GPR_IS_CONST1(_Rs_) ) info |= PROCESS_EE_SETMODET(mmreg1); + else info |= PROCESS_EE_SETMODES(mmreg1); + + if( xmminfo & XMMINFO_WRITED ) { + + _addNeededGPRtoXMMreg(_Rd_); + mmreg3 = _checkXMMreg(XMMTYPE_GPRREG, _Rd_, MODE_WRITE); + + if( !(xmminfo&XMMINFO_READD) && mmreg3 < 0 && ((g_pCurInstInfo->regs[vreg] & EEINST_LASTUSE) || !EEINST_ISLIVEXMM(vreg)) ) { + _freeXMMreg(mmreg1); + if( GPR_IS_CONST1(_Rs_) ) info &= ~PROCESS_EE_MODEWRITET; + else info &= ~PROCESS_EE_MODEWRITES; + _deleteMMXreg(MMX_GPR+_Rd_, 2); + xmmregs[mmreg1].inuse = 1; + xmmregs[mmreg1].reg = _Rd_; + xmmregs[mmreg1].mode = moded; + mmreg3 = mmreg1; + } + else if( mmreg3 < 0 ) mmreg3 = _allocGPRtoXMMreg(-1, _Rd_, moded); + + info |= PROCESS_EE_SET_D(mmreg3); + } + + if( xmminfo & (XMMINFO_READLO|XMMINFO_WRITELO) ) { + mmtemp = eeProcessHILO(XMMGPR_LO, ((xmminfo&XMMINFO_READLO)?MODE_READ:0)|((xmminfo&XMMINFO_WRITELO)?MODE_WRITE:0), 0); + if( mmtemp >= 0 ) info |= PROCESS_EE_SET_LO(mmtemp); + } + if( xmminfo & (XMMINFO_READHI|XMMINFO_WRITEHI) ) { + mmtemp = eeProcessHILO(XMMGPR_HI, ((xmminfo&XMMINFO_READLO)?MODE_READ:0)|((xmminfo&XMMINFO_WRITELO)?MODE_WRITE:0), 0); + if( mmtemp >= 0 ) info |= PROCESS_EE_SET_HI(mmtemp); + } + + if( creg == _Rs_ ) constscode(info|PROCESS_EE_SET_T(mmreg1)); + else consttcode(info|PROCESS_EE_SET_S(mmreg1)); + _clearNeededXMMregs(); + if( xmminfo & XMMINFO_WRITED ) GPR_DEL_CONST(_Rd_); + return; + } + } + else { + // no const regs + mmreg1 = _allocCheckGPRtoXMM(g_pCurInstInfo, _Rs_, MODE_READ); + mmreg2 = _allocCheckGPRtoXMM(g_pCurInstInfo, _Rt_, MODE_READ); + + if( mmreg1 >= 0 || mmreg2 >= 0 ) { + int info = PROCESS_EE_XMM; + + // do it all in xmm + if( mmreg1 < 0 ) mmreg1 = _allocGPRtoXMMreg(-1, _Rs_, MODE_READ); + if( mmreg2 < 0 ) mmreg2 = _allocGPRtoXMMreg(-1, _Rt_, MODE_READ); + + info |= PROCESS_EE_SETMODES(mmreg1)|PROCESS_EE_SETMODET(mmreg2); + + if( xmminfo & XMMINFO_WRITED ) { + // check for last used, if so don't alloc a new XMM reg + _addNeededGPRtoXMMreg(_Rd_); + mmreg3 = _checkXMMreg(XMMTYPE_GPRREG, _Rd_, moded); + + if( mmreg3 < 0 ) { + if( !(xmminfo&XMMINFO_READD) && ((g_pCurInstInfo->regs[_Rt_] & EEINST_LASTUSE) || !EEINST_ISLIVEXMM(_Rt_)) ) { + _freeXMMreg(mmreg2); + info &= ~PROCESS_EE_MODEWRITET; + _deleteMMXreg(MMX_GPR+_Rd_, 2); + xmmregs[mmreg2].inuse = 1; + xmmregs[mmreg2].reg = _Rd_; + xmmregs[mmreg2].mode = moded; + mmreg3 = mmreg2; + } + else if( !(xmminfo&XMMINFO_READD) && ((g_pCurInstInfo->regs[_Rs_] & EEINST_LASTUSE) || !EEINST_ISLIVEXMM(_Rs_)) ) { + _freeXMMreg(mmreg1); + info &= ~PROCESS_EE_MODEWRITES; + _deleteMMXreg(MMX_GPR+_Rd_, 2); + xmmregs[mmreg1].inuse = 1; + xmmregs[mmreg1].reg = _Rd_; + xmmregs[mmreg1].mode = moded; + mmreg3 = mmreg1; + } + else mmreg3 = _allocGPRtoXMMreg(-1, _Rd_, moded); + } + + info |= PROCESS_EE_SET_D(mmreg3); + } + + if( xmminfo & (XMMINFO_READLO|XMMINFO_WRITELO) ) { + mmtemp = eeProcessHILO(XMMGPR_LO, ((xmminfo&XMMINFO_READLO)?MODE_READ:0)|((xmminfo&XMMINFO_WRITELO)?MODE_WRITE:0), 0); + if( mmtemp >= 0 ) info |= PROCESS_EE_SET_LO(mmtemp); + } + if( xmminfo & (XMMINFO_READHI|XMMINFO_WRITEHI) ) { + mmtemp = eeProcessHILO(XMMGPR_HI, ((xmminfo&XMMINFO_READLO)?MODE_READ:0)|((xmminfo&XMMINFO_WRITELO)?MODE_WRITE:0), 0); + if( mmtemp >= 0 ) info |= PROCESS_EE_SET_HI(mmtemp); + } + + noconstcode(info|PROCESS_EE_SET_S(mmreg1)|PROCESS_EE_SET_T(mmreg2)); + _clearNeededXMMregs(); + if( xmminfo & XMMINFO_WRITED ) GPR_DEL_CONST(_Rd_); + return; + } + } + + _clearNeededXMMregs(); + } + + // regular x86 + _deleteGPRtoXMMreg(_Rs_, 1); + _deleteGPRtoXMMreg(_Rt_, 1); + if( xmminfo&XMMINFO_WRITED ) + _deleteGPRtoXMMreg(_Rd_, (xmminfo&XMMINFO_READD)?0:2); + _deleteMMXreg(MMX_GPR+_Rs_, 1); + _deleteMMXreg(MMX_GPR+_Rt_, 1); + if( xmminfo&XMMINFO_WRITED ) + _deleteMMXreg(MMX_GPR+_Rd_, (xmminfo&XMMINFO_READD)?0:2); + + // don't delete, fn will take care of them +// if( xmminfo & (XMMINFO_READLO|XMMINFO_WRITELO) ) { +// _deleteGPRtoXMMreg(XMMGPR_LO, (xmminfo&XMMINFO_READLO)?1:0); +// _deleteMMXreg(MMX_GPR+MMX_LO, (xmminfo&XMMINFO_READLO)?1:0); +// } +// if( xmminfo & (XMMINFO_READHI|XMMINFO_WRITEHI) ) { +// _deleteGPRtoXMMreg(XMMGPR_HI, (xmminfo&XMMINFO_READHI)?1:0); +// _deleteMMXreg(MMX_GPR+MMX_HI, (xmminfo&XMMINFO_READHI)?1:0); +// } + + if( GPR_IS_CONST1(_Rs_) ) { + constscode(0); + if( xmminfo&XMMINFO_WRITED ) GPR_DEL_CONST(_Rd_); + return; + } + + if( GPR_IS_CONST1(_Rt_) ) { + consttcode(0); + if( xmminfo&XMMINFO_WRITED ) GPR_DEL_CONST(_Rd_); + return; + } + + noconstcode(0); + if( xmminfo&XMMINFO_WRITED ) GPR_DEL_CONST(_Rd_); +} + +// rt = rs op imm16 +void eeRecompileCode1(R5900FNPTR constcode, R5900FNPTR_INFO noconstcode) +{ + int mmreg1, mmreg2; + if ( ! _Rt_ ) return; + + CHECK_SAVE_REG(_Rt_); + _eeProcessHasLive(_Rt_, 0); + EEINST_RESETSIGNEXT(_Rt_); + + if( GPR_IS_CONST1(_Rs_) ) { + _deleteMMXreg(MMX_GPR+_Rt_, 2); + _deleteGPRtoXMMreg(_Rt_, 2); + GPR_SET_CONST(_Rt_); + constcode(); + return; + } + + // test if should write mmx + if( g_pCurInstInfo->info & EEINST_MMX ) { + + // no const regs + mmreg1 = _allocCheckGPRtoMMX(g_pCurInstInfo, _Rs_, MODE_READ); + + if( mmreg1 >= 0 ) { + int info = PROCESS_EE_MMX|PROCESS_EE_SETMODES(mmreg1); + + // check for last used, if so don't alloc a new MMX reg + _addNeededMMXreg(MMX_GPR+_Rt_); + mmreg2 = _checkMMXreg(MMX_GPR+_Rt_, MODE_WRITE); + + if( mmreg2 < 0 ) { + if( (g_pCurInstInfo->regs[_Rs_] & EEINST_LASTUSE) || !EEINST_ISLIVE64(_Rs_) ) { + if( EEINST_ISLIVE64(_Rs_) ) { + _freeMMXreg(mmreg1); + info &= ~PROCESS_EE_MODEWRITES; + } + _deleteGPRtoXMMreg(_Rt_, 2); + mmxregs[mmreg1].inuse = 1; + mmxregs[mmreg1].reg = _Rt_; + mmxregs[mmreg1].mode = MODE_WRITE|MODE_READ; + mmreg2 = mmreg1; + } + else mmreg2 = _allocMMXreg(-1, MMX_GPR+_Rt_, MODE_WRITE); + } + + SetMMXstate(); + noconstcode(info|PROCESS_EE_SET_S(mmreg1)|PROCESS_EE_SET_T(mmreg2)); + _clearNeededMMXregs(); + GPR_DEL_CONST(_Rt_); + return; + } + + _clearNeededMMXregs(); + } + + // test if should write xmm, mirror to mmx code + if( g_pCurInstInfo->info & EEINST_XMM ) { + + // no const regs + mmreg1 = _allocCheckGPRtoXMM(g_pCurInstInfo, _Rs_, MODE_READ); + + if( mmreg1 >= 0 ) { + int info = PROCESS_EE_XMM|PROCESS_EE_SETMODES(mmreg1); + + // check for last used, if so don't alloc a new XMM reg + _addNeededGPRtoXMMreg(_Rt_); + mmreg2 = _checkXMMreg(XMMTYPE_GPRREG, _Rt_, MODE_WRITE); + + if( mmreg2 < 0 ) { + if( (g_pCurInstInfo->regs[_Rs_] & EEINST_LASTUSE) || !EEINST_ISLIVEXMM(_Rs_) ) { + _freeXMMreg(mmreg1); + info &= ~PROCESS_EE_MODEWRITES; + _deleteMMXreg(MMX_GPR+_Rt_, 2); + xmmregs[mmreg1].inuse = 1; + xmmregs[mmreg1].reg = _Rt_; + xmmregs[mmreg1].mode = MODE_WRITE|MODE_READ; + mmreg2 = mmreg1; + } + else mmreg2 = _allocGPRtoXMMreg(-1, _Rt_, MODE_WRITE); + } + + noconstcode(info|PROCESS_EE_SET_S(mmreg1)|PROCESS_EE_SET_T(mmreg2)); + _clearNeededXMMregs(); + GPR_DEL_CONST(_Rt_); + return; + } + + _clearNeededXMMregs(); + } + + // regular x86 + _deleteGPRtoXMMreg(_Rs_, 1); + _deleteGPRtoXMMreg(_Rt_, 2); + _deleteMMXreg(MMX_GPR+_Rs_, 1); + _deleteMMXreg(MMX_GPR+_Rt_, 2); + + noconstcode(0); + GPR_DEL_CONST(_Rt_); +} + +// rd = rt op sa +void eeRecompileCode2(R5900FNPTR constcode, R5900FNPTR_INFO noconstcode) +{ + int mmreg1, mmreg2; + if ( ! _Rd_ ) return; + + CHECK_SAVE_REG(_Rd_); + _eeProcessHasLive(_Rd_, 0); + EEINST_RESETSIGNEXT(_Rd_); + + if( GPR_IS_CONST1(_Rt_) ) { + _deleteMMXreg(MMX_GPR+_Rd_, 2); + _deleteGPRtoXMMreg(_Rd_, 2); + GPR_SET_CONST(_Rd_); + constcode(); + return; + } + + // test if should write mmx + if( g_pCurInstInfo->info & EEINST_MMX ) { + + // no const regs + mmreg1 = _allocCheckGPRtoMMX(g_pCurInstInfo, _Rt_, MODE_READ); + + if( mmreg1 >= 0 ) { + int info = PROCESS_EE_MMX|PROCESS_EE_SETMODET(mmreg1); + + // check for last used, if so don't alloc a new MMX reg + _addNeededMMXreg(MMX_GPR+_Rd_); + mmreg2 = _checkMMXreg(MMX_GPR+_Rd_, MODE_WRITE); + + if( mmreg2 < 0 ) { + if( (g_pCurInstInfo->regs[_Rt_] & EEINST_LASTUSE) || !EEINST_ISLIVE64(_Rt_) ) { + if( EEINST_ISLIVE64(_Rt_) ) { + _freeMMXreg(mmreg1); + info &= ~PROCESS_EE_MODEWRITET; + } + _deleteGPRtoXMMreg(_Rd_, 2); + mmxregs[mmreg1].inuse = 1; + mmxregs[mmreg1].reg = _Rd_; + mmxregs[mmreg1].mode = MODE_WRITE|MODE_READ; + mmreg2 = mmreg1; + } + else mmreg2 = _allocMMXreg(-1, MMX_GPR+_Rd_, MODE_WRITE); + } + + SetMMXstate(); + noconstcode(info|PROCESS_EE_SET_T(mmreg1)|PROCESS_EE_SET_D(mmreg2)); + _clearNeededMMXregs(); + GPR_DEL_CONST(_Rd_); + return; + } + + _clearNeededMMXregs(); + } + + // test if should write xmm, mirror to mmx code + if( g_pCurInstInfo->info & EEINST_XMM ) { + + // no const regs + mmreg1 = _allocCheckGPRtoXMM(g_pCurInstInfo, _Rt_, MODE_READ); + + if( mmreg1 >= 0 ) { + int info = PROCESS_EE_XMM|PROCESS_EE_SETMODET(mmreg1); + + // check for last used, if so don't alloc a new XMM reg + _addNeededGPRtoXMMreg(_Rd_); + mmreg2 = _checkXMMreg(XMMTYPE_GPRREG, _Rd_, MODE_WRITE); + + if( mmreg2 < 0 ) { + if( (g_pCurInstInfo->regs[_Rt_] & EEINST_LASTUSE) || !EEINST_ISLIVE64(_Rt_) ) { + _freeXMMreg(mmreg1); + info &= ~PROCESS_EE_MODEWRITET; + _deleteMMXreg(MMX_GPR+_Rd_, 2); + xmmregs[mmreg1].inuse = 1; + xmmregs[mmreg1].reg = _Rd_; + xmmregs[mmreg1].mode = MODE_WRITE|MODE_READ; + mmreg2 = mmreg1; + } + else mmreg2 = _allocGPRtoXMMreg(-1, _Rd_, MODE_WRITE); + } + + noconstcode(info|PROCESS_EE_SET_T(mmreg1)|PROCESS_EE_SET_D(mmreg2)); + _clearNeededXMMregs(); + GPR_DEL_CONST(_Rd_); + return; + } + + _clearNeededXMMregs(); + } + + // regular x86 + _deleteGPRtoXMMreg(_Rt_, 1); + _deleteGPRtoXMMreg(_Rd_, 2); + _deleteMMXreg(MMX_GPR+_Rt_, 1); + _deleteMMXreg(MMX_GPR+_Rd_, 2); + + noconstcode(0); + GPR_DEL_CONST(_Rd_); +} + +// rt op rs +void eeRecompileCode3(R5900FNPTR constcode, R5900FNPTR_INFO multicode) +{ + assert(0); + // for now, don't support xmm + _deleteEEreg(_Rs_, 1); + _deleteEEreg(_Rt_, 1); + + if( GPR_IS_CONST2(_Rs_, _Rt_) ) { + constcode(); + return; + } + + if( GPR_IS_CONST1(_Rs_) ) { + //multicode(PROCESS_EE_CONSTT); + return; + } + + if( GPR_IS_CONST1(_Rt_) ) { + //multicode(PROCESS_EE_CONSTT); + return; + } + + multicode(0); +} + +// Simple Code Templates // + +// rd = rs op rt +void eeRecompileCodeConst0(R5900FNPTR constcode, R5900FNPTR_INFO constscode, R5900FNPTR_INFO consttcode, R5900FNPTR_INFO noconstcode) +{ + if ( ! _Rd_ ) return; + + // for now, don't support xmm + CHECK_SAVE_REG(_Rd_); + + _deleteGPRtoXMMreg(_Rs_, 1); + _deleteGPRtoXMMreg(_Rt_, 1); + _deleteGPRtoXMMreg(_Rd_, 0); + _deleteMMXreg(MMX_GPR+_Rs_, 1); + _deleteMMXreg(MMX_GPR+_Rt_, 1); + _deleteMMXreg(MMX_GPR+_Rd_, 0); + + if( GPR_IS_CONST2(_Rs_, _Rt_) ) { + GPR_SET_CONST(_Rd_); + constcode(); + return; + } + + if( GPR_IS_CONST1(_Rs_) ) { + constscode(0); + GPR_DEL_CONST(_Rd_); + return; + } + + if( GPR_IS_CONST1(_Rt_) ) { + consttcode(0); + GPR_DEL_CONST(_Rd_); + return; + } + + noconstcode(0); + GPR_DEL_CONST(_Rd_); +} + +// rt = rs op imm16 +void eeRecompileCodeConst1(R5900FNPTR constcode, R5900FNPTR_INFO noconstcode) +{ + if ( ! _Rt_ ) + return; + + // for now, don't support xmm + CHECK_SAVE_REG(_Rt_); + + _deleteGPRtoXMMreg(_Rs_, 1); + _deleteGPRtoXMMreg(_Rt_, 0); + + if( GPR_IS_CONST1(_Rs_) ) { + GPR_SET_CONST(_Rt_); + constcode(); + return; + } + + noconstcode(0); + GPR_DEL_CONST(_Rt_); +} + +// rd = rt op sa +void eeRecompileCodeConst2(R5900FNPTR constcode, R5900FNPTR_INFO noconstcode) +{ + if ( ! _Rd_ ) return; + + // for now, don't support xmm + CHECK_SAVE_REG(_Rd_); + + _deleteGPRtoXMMreg(_Rt_, 1); + _deleteGPRtoXMMreg(_Rd_, 0); + + if( GPR_IS_CONST1(_Rt_) ) { + GPR_SET_CONST(_Rd_); + constcode(); + return; + } + + noconstcode(0); + GPR_DEL_CONST(_Rd_); +} + +// rd = rt MULT rs (SPECIAL) +void eeRecompileCodeConstSPECIAL(R5900FNPTR constcode, R5900FNPTR_INFO multicode, int MULT) +{ + assert(0); + // for now, don't support xmm + if( MULT ) { + CHECK_SAVE_REG(_Rd_); + _deleteGPRtoXMMreg(_Rd_, 0); + } + + _deleteGPRtoXMMreg(_Rs_, 1); + _deleteGPRtoXMMreg(_Rt_, 1); + + if( GPR_IS_CONST2(_Rs_, _Rt_) ) { + if( MULT && _Rd_ ) GPR_SET_CONST(_Rd_); + constcode(); + return; + } + + if( GPR_IS_CONST1(_Rs_) ) { + //multicode(PROCESS_EE_CONSTS); + if( MULT && _Rd_ ) GPR_DEL_CONST(_Rd_); + return; + } + + if( GPR_IS_CONST1(_Rt_) ) { + //multicode(PROCESS_EE_CONSTT); + if( MULT && _Rd_ ) GPR_DEL_CONST(_Rd_); + return; + } + + multicode(0); + if( MULT && _Rd_ ) GPR_DEL_CONST(_Rd_); +} + +// EE XMM allocation code +int eeRecompileCodeXMM(int xmminfo) +{ + int info = PROCESS_EE_XMM; + + // save state + if( xmminfo & XMMINFO_WRITED ) { + CHECK_SAVE_REG(_Rd_); + _eeProcessHasLive(_Rd_, 0); + EEINST_RESETSIGNEXT(_Rd_); + } + + // flush consts + if( xmminfo & XMMINFO_READT ) { + if( GPR_IS_CONST1( _Rt_ ) && !(g_cpuFlushedConstReg&(1<<_Rt_)) ) { + MOV32ItoM((int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ], g_cpuConstRegs[_Rt_].UL[0]); + MOV32ItoM((int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 1 ], g_cpuConstRegs[_Rt_].UL[1]); + g_cpuFlushedConstReg |= (1<<_Rt_); + } + } + if( xmminfo & XMMINFO_READS) { + if( GPR_IS_CONST1( _Rs_ ) && !(g_cpuFlushedConstReg&(1<<_Rs_)) ) { + MOV32ItoM((int)&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ], g_cpuConstRegs[_Rs_].UL[0]); + MOV32ItoM((int)&cpuRegs.GPR.r[ _Rs_ ].UL[ 1 ], g_cpuConstRegs[_Rs_].UL[1]); + g_cpuFlushedConstReg |= (1<<_Rs_); + } + } + + if( xmminfo & XMMINFO_WRITED ) { + GPR_DEL_CONST(_Rd_); + } + + // add needed + if( xmminfo & (XMMINFO_READLO|XMMINFO_WRITELO) ) { + _addNeededGPRtoXMMreg(XMMGPR_LO); + } + if( xmminfo & (XMMINFO_READHI|XMMINFO_WRITEHI) ) { + _addNeededGPRtoXMMreg(XMMGPR_HI); + } + if( xmminfo & XMMINFO_READS) _addNeededGPRtoXMMreg(_Rs_); + if( xmminfo & XMMINFO_READT) _addNeededGPRtoXMMreg(_Rt_); + if( xmminfo & XMMINFO_WRITED ) _addNeededGPRtoXMMreg(_Rd_); + + // allocate + if( xmminfo & XMMINFO_READS) { + int reg = _allocGPRtoXMMreg(-1, _Rs_, MODE_READ); + info |= PROCESS_EE_SET_S(reg)|PROCESS_EE_SETMODES(reg); + } + if( xmminfo & XMMINFO_READT) { + int reg = _allocGPRtoXMMreg(-1, _Rt_, MODE_READ); + info |= PROCESS_EE_SET_T(reg)|PROCESS_EE_SETMODET(reg); + } + + if( xmminfo & XMMINFO_WRITED ) { + int readd = MODE_WRITE|((xmminfo&XMMINFO_READD)?((xmminfo&XMMINFO_READD_LO)?(MODE_READ|MODE_READHALF):MODE_READ):0); + + int regd = _checkXMMreg(XMMTYPE_GPRREG, _Rd_, readd); + + if( regd < 0 ) { + if( !(xmminfo&XMMINFO_READD) && (xmminfo & XMMINFO_READT) && (_Rt_ == 0 || (g_pCurInstInfo->regs[_Rt_] & EEINST_LASTUSE) || !EEINST_ISLIVEXMM(_Rt_)) ) { + _freeXMMreg(EEREC_T); + _deleteMMXreg(MMX_GPR+_Rd_, 2); + xmmregs[EEREC_T].inuse = 1; + xmmregs[EEREC_T].reg = _Rd_; + xmmregs[EEREC_T].mode = readd; + regd = EEREC_T; + } + else if( !(xmminfo&XMMINFO_READD) && (xmminfo & XMMINFO_READS) && (_Rs_ == 0 || (g_pCurInstInfo->regs[_Rs_] & EEINST_LASTUSE) || !EEINST_ISLIVEXMM(_Rs_)) ) { + _freeXMMreg(EEREC_S); + _deleteMMXreg(MMX_GPR+_Rd_, 2); + xmmregs[EEREC_S].inuse = 1; + xmmregs[EEREC_S].reg = _Rd_; + xmmregs[EEREC_S].mode = readd; + regd = EEREC_S; + } + else regd = _allocGPRtoXMMreg(-1, _Rd_, readd); + } + + info |= PROCESS_EE_SET_D(regd); + } + if( xmminfo & (XMMINFO_READLO|XMMINFO_WRITELO) ) { + info |= PROCESS_EE_SET_LO(_allocGPRtoXMMreg(-1, XMMGPR_LO, ((xmminfo&XMMINFO_READLO)?MODE_READ:0)|((xmminfo&XMMINFO_WRITELO)?MODE_WRITE:0))); + info |= PROCESS_EE_LO; + } + if( xmminfo & (XMMINFO_READHI|XMMINFO_WRITEHI) ) { + info |= PROCESS_EE_SET_HI(_allocGPRtoXMMreg(-1, XMMGPR_HI, ((xmminfo&XMMINFO_READHI)?MODE_READ:0)|((xmminfo&XMMINFO_WRITEHI)?MODE_WRITE:0))); + info |= PROCESS_EE_HI; + } + return info; +} + +// EE COP1(FPU) XMM allocation code +#define _Ft_ _Rt_ +#define _Fs_ _Rd_ +#define _Fd_ _Sa_ + +#define PROCESS_EE_SETMODES_XMM(mmreg) ((xmmregs[mmreg].mode&MODE_WRITE)?PROCESS_EE_MODEWRITES:0) +#define PROCESS_EE_SETMODET_XMM(mmreg) ((xmmregs[mmreg].mode&MODE_WRITE)?PROCESS_EE_MODEWRITET:0) + +// rd = rs op rt +void eeFPURecompileCode(R5900FNPTR_INFO xmmcode, R5900FNPTR fpucode, int xmminfo) +{ + int mmregs=-1, mmregt=-1, mmregd=-1, mmregacc=-1; + int info = PROCESS_EE_XMM; + + if( xmminfo & XMMINFO_READS ) _addNeededFPtoXMMreg(_Fs_); + if( xmminfo & XMMINFO_READT ) _addNeededFPtoXMMreg(_Ft_); + if( xmminfo & (XMMINFO_WRITED|XMMINFO_READD) ) _addNeededFPtoXMMreg(_Fd_); + if( xmminfo & (XMMINFO_WRITEACC|XMMINFO_READACC) ) _addNeededFPACCtoXMMreg(); + + if( xmminfo & XMMINFO_READT ) { + if( g_pCurInstInfo->fpuregs[_Ft_] & EEINST_LASTUSE ) mmregt = _checkXMMreg(XMMTYPE_FPREG, _Ft_, MODE_READ); + else mmregt = _allocFPtoXMMreg(-1, _Ft_, MODE_READ); + } + + if( xmminfo & XMMINFO_READS ) { + if( ( !(xmminfo & XMMINFO_READT) || (mmregt >= 0) ) && (g_pCurInstInfo->fpuregs[_Fs_] & EEINST_LASTUSE) ) { + mmregs = _checkXMMreg(XMMTYPE_FPREG, _Fs_, MODE_READ); + } + else mmregs = _allocFPtoXMMreg(-1, _Fs_, MODE_READ); + } + + if( mmregs >= 0 ) info |= PROCESS_EE_SETMODES_XMM(mmregs); + if( mmregt >= 0 ) info |= PROCESS_EE_SETMODET_XMM(mmregt); + + if( xmminfo & XMMINFO_READD ) { + assert( xmminfo & XMMINFO_WRITED ); + mmregd = _allocFPtoXMMreg(-1, _Fd_, MODE_READ); + } + + if( xmminfo & XMMINFO_READACC ) { + if( !(xmminfo&XMMINFO_WRITEACC) && (g_pCurInstInfo->fpuregs[_Ft_] & EEINST_LASTUSE) ) + mmregacc = _checkXMMreg(XMMTYPE_FPACC, 0, MODE_READ); + else mmregacc = _allocFPACCtoXMMreg(-1, MODE_READ); + } + + if( xmminfo & XMMINFO_WRITEACC ) { + + // check for last used, if so don't alloc a new XMM reg + int readacc = MODE_WRITE|((xmminfo&XMMINFO_READACC)?MODE_READ:0); + + mmregacc = _checkXMMreg(XMMTYPE_FPACC, 0, readacc); + + if( mmregacc < 0 ) { + if( (xmminfo&XMMINFO_READT) && mmregt >= 0 && (FPUINST_LASTUSE(_Ft_) || !FPUINST_ISLIVE(_Ft_)) ) { + if( FPUINST_ISLIVE(_Ft_) ) { + _freeXMMreg(mmregt); + info &= ~PROCESS_EE_MODEWRITET; + } + _deleteMMXreg(MMX_FPU+XMMFPU_ACC, 2); + xmmregs[mmregt].inuse = 1; + xmmregs[mmregt].reg = 0; + xmmregs[mmregt].mode = readacc; + xmmregs[mmregt].type = XMMTYPE_FPACC; + mmregacc = mmregt; + } + else if( (xmminfo&XMMINFO_READS) && mmregs >= 0 && (FPUINST_LASTUSE(_Fs_) || !FPUINST_ISLIVE(_Fs_)) ) { + if( FPUINST_ISLIVE(_Fs_) ) { + _freeXMMreg(mmregs); + info &= ~PROCESS_EE_MODEWRITES; + } + _deleteMMXreg(MMX_FPU+XMMFPU_ACC, 2); + xmmregs[mmregs].inuse = 1; + xmmregs[mmregs].reg = 0; + xmmregs[mmregs].mode = readacc; + xmmregs[mmregs].type = XMMTYPE_FPACC; + mmregacc = mmregs; + } + else mmregacc = _allocFPACCtoXMMreg(-1, readacc); + } + + xmmregs[mmregacc].mode |= MODE_WRITE; + } + else if( xmminfo & XMMINFO_WRITED ) { + // check for last used, if so don't alloc a new XMM reg + int readd = MODE_WRITE|((xmminfo&XMMINFO_READD)?MODE_READ:0); + if( xmminfo&XMMINFO_READD ) mmregd = _allocFPtoXMMreg(-1, _Fd_, readd); + else mmregd = _checkXMMreg(XMMTYPE_FPREG, _Fd_, readd); + + if( mmregd < 0 ) { + if( (xmminfo&XMMINFO_READT) && mmregt >= 0 && (FPUINST_LASTUSE(_Ft_) || !FPUINST_ISLIVE(_Ft_)) ) { + if( FPUINST_ISLIVE(_Ft_) ) { + _freeXMMreg(mmregt); + info &= ~PROCESS_EE_MODEWRITET; + } + _deleteMMXreg(MMX_FPU+_Fd_, 2); + xmmregs[mmregt].inuse = 1; + xmmregs[mmregt].reg = _Fd_; + xmmregs[mmregt].mode = readd; + mmregd = mmregt; + } + else if( (xmminfo&XMMINFO_READS) && mmregs >= 0 && (FPUINST_LASTUSE(_Fs_) || !FPUINST_ISLIVE(_Fs_)) ) { + if( FPUINST_ISLIVE(_Fs_) ) { + _freeXMMreg(mmregs); + info &= ~PROCESS_EE_MODEWRITES; + } + _deleteMMXreg(MMX_FPU+_Fd_, 2); + xmmregs[mmregs].inuse = 1; + xmmregs[mmregs].reg = _Fd_; + xmmregs[mmregs].mode = readd; + mmregd = mmregs; + } + else if( (xmminfo&XMMINFO_READACC) && mmregacc >= 0 && (FPUINST_LASTUSE(XMMFPU_ACC) || !FPUINST_ISLIVE(XMMFPU_ACC)) ) { + if( FPUINST_ISLIVE(XMMFPU_ACC) ) + _freeXMMreg(mmregacc); + _deleteMMXreg(MMX_FPU+_Fd_, 2); + xmmregs[mmregacc].inuse = 1; + xmmregs[mmregacc].reg = _Fd_; + xmmregs[mmregacc].mode = readd; + xmmregs[mmregacc].type = XMMTYPE_FPREG; + mmregd = mmregacc; + } + else mmregd = _allocFPtoXMMreg(-1, _Fd_, readd); + } + } + + assert( mmregs >= 0 || mmregt >= 0 || mmregd >= 0 || mmregacc >= 0 ); + + if( xmminfo & XMMINFO_WRITED ) { + assert( mmregd >= 0 ); + info |= PROCESS_EE_SET_D(mmregd); + } + if( xmminfo & (XMMINFO_WRITEACC|XMMINFO_READACC) ) { + if( mmregacc >= 0 ) info |= PROCESS_EE_SET_ACC(mmregacc)|PROCESS_EE_ACC; + else assert( !(xmminfo&XMMINFO_WRITEACC)); + } + + if( xmminfo & XMMINFO_READS ) { + if( mmregs >= 0 ) info |= PROCESS_EE_SET_S(mmregs)|PROCESS_EE_S; + } + if( xmminfo & XMMINFO_READT ) { + if( mmregt >= 0 ) info |= PROCESS_EE_SET_T(mmregt)|PROCESS_EE_T; + } + + // at least one must be in xmm + if( (xmminfo & (XMMINFO_READS|XMMINFO_READT)) == (XMMINFO_READS|XMMINFO_READT) ) { + assert( mmregs >= 0 || mmregt >= 0 ); + } + + xmmcode(info); + _clearNeededXMMregs(); +} + +} } \ No newline at end of file diff --git a/pcsx2/x86/ix86/ix86.h b/pcsx2/x86/ix86/ix86.h index dd39f53254..ab74a17809 100644 --- a/pcsx2/x86/ix86/ix86.h +++ b/pcsx2/x86/ix86/ix86.h @@ -170,6 +170,16 @@ extern u32 *j32Ptr[32]; #define RexRB(w, reg, base) if( w||(reg) >= 8 || (base)>=8 ) assert(0); #define RexRXB(w, reg, index, base) if( w||(reg) >= 8 || (index) >= 8 || (base) >= 8 ) assert(0); +// perf counters +#ifdef PCSX2_DEVBUILD +extern void StartPerfCounter(); +extern void StopPerfCounter(); +#else +#define StartPerfCounter() +#define StopPerfCounter() +#endif + + extern __forceinline void write8( u8 val ); extern __forceinline void write16( u16 val ); extern __forceinline void write32( u32 val ); diff --git a/pcsx2/x86/ix86/ix86_tools.cpp b/pcsx2/x86/ix86/ix86_tools.cpp new file mode 100644 index 0000000000..f8fb7903e6 --- /dev/null +++ b/pcsx2/x86/ix86/ix86_tools.cpp @@ -0,0 +1,274 @@ +/* Pcsx2 - Pc Ps2 Emulator + * Copyright (C) 2002-2008 Pcsx2 Team + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA + */ + +#include "PrecompiledHeader.h" + +#include "Misc.h" +#include "ix86/ix86.h" + +// used to make sure regs don't get changed while in recompiler +// use FreezeMMXRegs, FreezeXMMRegs + +u8 g_globalMMXSaved = 0; +u8 g_globalXMMSaved = 0; + +PCSX2_ALIGNED16( static u64 g_globalMMXData[8] ); +PCSX2_ALIGNED16( static u64 g_globalXMMData[2*XMMREGS] ); + +// performance counter vars. +static LARGE_INTEGER lbase = {0}, lfinal = {0}; +static u32 s_pCurBlock_ltime; + + +///////////////////////////////////////////////////////////////////// +// SetCPUState -- for assugnment of SSE roundmodes and clampmodes. + +u32 g_sseMXCSR = DEFAULT_sseMXCSR; +u32 g_sseVUMXCSR = DEFAULT_sseVUMXCSR; + +void SetCPUState(u32 sseMXCSR, u32 sseVUMXCSR) +{ + //Msgbox::Alert("SetCPUState: Config.sseMXCSR = %x; Config.sseVUMXCSR = %x \n", Config.sseMXCSR, Config.sseVUMXCSR); + // SSE STATE // + // WARNING: do not touch unless you know what you are doing + + sseMXCSR &= 0xffff; // clear the upper 16 bits since they shouldn't be set + sseVUMXCSR &= 0xffff; + + if( !cpucaps.hasStreamingSIMD2Extensions ) + { + // SSE1 cpus do not support Denormals Are Zero flag (throws an exception + // if we don't mask them off) + + sseMXCSR &= ~0x0040; + sseVUMXCSR &= ~0x0040; + } + + g_sseMXCSR = sseMXCSR; + g_sseVUMXCSR = sseVUMXCSR; + +#ifdef _MSC_VER + __asm ldmxcsr g_sseMXCSR; // set the new sse control +#else + __asm__("ldmxcsr %0" : : "m"(g_sseMXCSR) ); +#endif + //g_sseVUMXCSR = g_sseMXCSR|0x6000; +} + +///////////////////////////////////////////////////////////////////// +// +__forceinline void FreezeMMXRegs_(int save) +{ + assert( g_EEFreezeRegs ); + + if( save ) { + g_globalMMXSaved++; + if( g_globalMMXSaved>1 ) + { + //SysPrintf("MMX Already Saved!\n"); + return; + } + +#ifdef _MSC_VER + __asm { + movntq mmword ptr [g_globalMMXData + 0], mm0 + movntq mmword ptr [g_globalMMXData + 8], mm1 + movntq mmword ptr [g_globalMMXData + 16], mm2 + movntq mmword ptr [g_globalMMXData + 24], mm3 + movntq mmword ptr [g_globalMMXData + 32], mm4 + movntq mmword ptr [g_globalMMXData + 40], mm5 + movntq mmword ptr [g_globalMMXData + 48], mm6 + movntq mmword ptr [g_globalMMXData + 56], mm7 + emms + } +#else + __asm__(".intel_syntax\n" + "movq [%0+0x00], %%mm0\n" + "movq [%0+0x08], %%mm1\n" + "movq [%0+0x10], %%mm2\n" + "movq [%0+0x18], %%mm3\n" + "movq [%0+0x20], %%mm4\n" + "movq [%0+0x28], %%mm5\n" + "movq [%0+0x30], %%mm6\n" + "movq [%0+0x38], %%mm7\n" + "emms\n" + ".att_syntax\n" : : "r"(g_globalMMXData) ); +#endif + + } + else { + if( g_globalMMXSaved==0 ) + { + //SysPrintf("MMX Not Saved!\n"); + return; + } + g_globalMMXSaved--; + + if( g_globalMMXSaved > 0 ) return; + +#ifdef _MSC_VER + __asm { + movq mm0, mmword ptr [g_globalMMXData + 0] + movq mm1, mmword ptr [g_globalMMXData + 8] + movq mm2, mmword ptr [g_globalMMXData + 16] + movq mm3, mmword ptr [g_globalMMXData + 24] + movq mm4, mmword ptr [g_globalMMXData + 32] + movq mm5, mmword ptr [g_globalMMXData + 40] + movq mm6, mmword ptr [g_globalMMXData + 48] + movq mm7, mmword ptr [g_globalMMXData + 56] + emms + } +#else + __asm__(".intel_syntax\n" + "movq %%mm0, [%0+0x00]\n" + "movq %%mm1, [%0+0x08]\n" + "movq %%mm2, [%0+0x10]\n" + "movq %%mm3, [%0+0x18]\n" + "movq %%mm4, [%0+0x20]\n" + "movq %%mm5, [%0+0x28]\n" + "movq %%mm6, [%0+0x30]\n" + "movq %%mm7, [%0+0x38]\n" + "emms\n" + ".att_syntax\n" : : "r"(g_globalMMXData) ); +#endif + } +} + +////////////////////////////////////////////////////////////////////// + +__forceinline void FreezeXMMRegs_(int save) +{ + //SysPrintf("FreezeXMMRegs_(%d); [%d]\n", save, g_globalXMMSaved); + assert( g_EEFreezeRegs ); + + if( save ) { + g_globalXMMSaved++; + if( g_globalXMMSaved > 1 ){ + //SysPrintf("XMM Already saved\n"); + return; + } + + +#ifdef _MSC_VER + __asm { + movaps xmmword ptr [g_globalXMMData + 0x00], xmm0 + movaps xmmword ptr [g_globalXMMData + 0x10], xmm1 + movaps xmmword ptr [g_globalXMMData + 0x20], xmm2 + movaps xmmword ptr [g_globalXMMData + 0x30], xmm3 + movaps xmmword ptr [g_globalXMMData + 0x40], xmm4 + movaps xmmword ptr [g_globalXMMData + 0x50], xmm5 + movaps xmmword ptr [g_globalXMMData + 0x60], xmm6 + movaps xmmword ptr [g_globalXMMData + 0x70], xmm7 + } + +#else + __asm__(".intel_syntax\n" + "movaps [%0+0x00], %%xmm0\n" + "movaps [%0+0x10], %%xmm1\n" + "movaps [%0+0x20], %%xmm2\n" + "movaps [%0+0x30], %%xmm3\n" + "movaps [%0+0x40], %%xmm4\n" + "movaps [%0+0x50], %%xmm5\n" + "movaps [%0+0x60], %%xmm6\n" + "movaps [%0+0x70], %%xmm7\n" + ".att_syntax\n" : : "r"(g_globalXMMData) ); + +#endif // _MSC_VER + } + else { + if( g_globalXMMSaved==0 ) + { + //SysPrintf("XMM Regs not saved!\n"); + return; + } + + // TODO: really need to backup all regs? + g_globalXMMSaved--; + if( g_globalXMMSaved > 0 ) return; + +#ifdef _MSC_VER + __asm { + movaps xmm0, xmmword ptr [g_globalXMMData + 0x00] + movaps xmm1, xmmword ptr [g_globalXMMData + 0x10] + movaps xmm2, xmmword ptr [g_globalXMMData + 0x20] + movaps xmm3, xmmword ptr [g_globalXMMData + 0x30] + movaps xmm4, xmmword ptr [g_globalXMMData + 0x40] + movaps xmm5, xmmword ptr [g_globalXMMData + 0x50] + movaps xmm6, xmmword ptr [g_globalXMMData + 0x60] + movaps xmm7, xmmword ptr [g_globalXMMData + 0x70] + } + +#else + __asm__(".intel_syntax\n" + "movaps %%xmm0, [%0+0x00]\n" + "movaps %%xmm1, [%0+0x10]\n" + "movaps %%xmm2, [%0+0x20]\n" + "movaps %%xmm3, [%0+0x30]\n" + "movaps %%xmm4, [%0+0x40]\n" + "movaps %%xmm5, [%0+0x50]\n" + "movaps %%xmm6, [%0+0x60]\n" + "movaps %%xmm7, [%0+0x70]\n" + ".att_syntax\n" : : "r"(g_globalXMMData) ); + +#endif // _MSC_VER + } +} + +#ifdef PCSX2_DEVBUILD +__declspec(naked) void _StartPerfCounter() +{ + __asm { + push eax + push ebx + push ecx + + rdtsc + mov dword ptr [offset lbase], eax + mov dword ptr [offset lbase + 4], edx + + pop ecx + pop ebx + pop eax + ret + } +} + +__declspec(naked) void _StopPerfCounter() +{ + __asm { + push eax + push ebx + push ecx + + rdtsc + + sub eax, dword ptr [offset lbase] + sbb edx, dword ptr [offset lbase + 4] + mov ecx, s_pCurBlock_ltime + add eax, dword ptr [ecx] + adc edx, dword ptr [ecx + 4] + mov dword ptr [ecx], eax + mov dword ptr [ecx + 4], edx + pop ecx + pop ebx + pop eax + ret + } +} + +#endif // PCSX2_DEVBUILD \ No newline at end of file diff --git a/pcsx2/xmlpatchloader.cpp b/pcsx2/xmlpatchloader.cpp index 06727c626e..76900e7310 100644 --- a/pcsx2/xmlpatchloader.cpp +++ b/pcsx2/xmlpatchloader.cpp @@ -78,7 +78,7 @@ vector patches; int LoadPatch( const string& crc) { char pfile[256]; - sprintf(pfile,"patches\\%S.xml",&crc); + sprintf(pfile,"patches\\%hs.xml",&crc); patchnumber=0; @@ -159,7 +159,7 @@ int LoadGroup(TiXmlNode *group,int gParent) // only valid for recompilers TiXmlNode *fastmemory=group->FirstChild("FASTMEMORY"); if(fastmemory!=NULL) - EE::Dynarec::SetFastMemory(1); + Dynarec::SetFastMemory(1); TiXmlNode *zerogs=group->FirstChild("ZEROGS"); if(zerogs!=NULL) diff --git a/plugins/spu2ghz/SPU2ghz_vs2008.vcproj b/plugins/spu2ghz/SPU2ghz_vs2008.vcproj index 3ec5910110..5b24d44776 100644 --- a/plugins/spu2ghz/SPU2ghz_vs2008.vcproj +++ b/plugins/spu2ghz/SPU2ghz_vs2008.vcproj @@ -292,7 +292,7 @@