COP2: Mask R register on CFC2 reads

This commit is contained in:
refractionpcsx2 2023-03-16 20:26:42 +00:00
parent 6e14680ac7
commit ac113b48e7
2 changed files with 16 additions and 5 deletions

View File

@ -137,12 +137,18 @@ void CFC2() {
}
if (_Rt_ == 0) return;
cpuRegs.GPR.r[_Rt_].UL[0] = VU0.VI[_Fs_].UL;
if(VU0.VI[_Fs_].UL & 0x80000000)
cpuRegs.GPR.r[_Rt_].UL[1] = 0xffffffff;
if (_Fs_ == REG_R)
cpuRegs.GPR.r[_Rt_].UL[0] = VU0.VI[REG_R].UL & 0x7FFFFF;
else
cpuRegs.GPR.r[_Rt_].UL[1] = 0;
{
cpuRegs.GPR.r[_Rt_].UL[0] = VU0.VI[_Fs_].UL;
if (VU0.VI[_Fs_].UL & 0x80000000)
cpuRegs.GPR.r[_Rt_].UL[1] = 0xffffffff;
else
cpuRegs.GPR.r[_Rt_].UL[1] = 0;
}
}
void CTC2() {

View File

@ -450,6 +450,11 @@ static void recCFC2()
xMOVSX(xRegister64(regt), ptr32[&vu0Regs.VI[_Rd_].UL]);
}
}
else if (_Rd_ == REG_R)
{
xMOVSX(xRegister64(regt), ptr32[&vu0Regs.VI[REG_R].UL]);
xAND(xRegister64(regt), 0x7FFFFF);
}
else if (_Rd_ >= REG_STATUS_FLAG) // FixMe: Should R-Reg have upper 9 bits 0?
{
xMOVSX(xRegister64(regt), ptr32[&vu0Regs.VI[_Rd_].UL]);