From ac113b48e7b1644a4f219a5e9fecb9b6838ee0d6 Mon Sep 17 00:00:00 2001 From: refractionpcsx2 Date: Thu, 16 Mar 2023 20:26:42 +0000 Subject: [PATCH] COP2: Mask R register on CFC2 reads --- pcsx2/VU0.cpp | 16 +++++++++++----- pcsx2/x86/microVU_Macro.inl | 5 +++++ 2 files changed, 16 insertions(+), 5 deletions(-) diff --git a/pcsx2/VU0.cpp b/pcsx2/VU0.cpp index 53d539cdb9..39f5635423 100644 --- a/pcsx2/VU0.cpp +++ b/pcsx2/VU0.cpp @@ -137,12 +137,18 @@ void CFC2() { } if (_Rt_ == 0) return; - cpuRegs.GPR.r[_Rt_].UL[0] = VU0.VI[_Fs_].UL; - - if(VU0.VI[_Fs_].UL & 0x80000000) - cpuRegs.GPR.r[_Rt_].UL[1] = 0xffffffff; + if (_Fs_ == REG_R) + cpuRegs.GPR.r[_Rt_].UL[0] = VU0.VI[REG_R].UL & 0x7FFFFF; else - cpuRegs.GPR.r[_Rt_].UL[1] = 0; + { + cpuRegs.GPR.r[_Rt_].UL[0] = VU0.VI[_Fs_].UL; + + if (VU0.VI[_Fs_].UL & 0x80000000) + cpuRegs.GPR.r[_Rt_].UL[1] = 0xffffffff; + else + cpuRegs.GPR.r[_Rt_].UL[1] = 0; + } + } void CTC2() { diff --git a/pcsx2/x86/microVU_Macro.inl b/pcsx2/x86/microVU_Macro.inl index 10dae6b82a..9e506667ea 100644 --- a/pcsx2/x86/microVU_Macro.inl +++ b/pcsx2/x86/microVU_Macro.inl @@ -450,6 +450,11 @@ static void recCFC2() xMOVSX(xRegister64(regt), ptr32[&vu0Regs.VI[_Rd_].UL]); } } + else if (_Rd_ == REG_R) + { + xMOVSX(xRegister64(regt), ptr32[&vu0Regs.VI[REG_R].UL]); + xAND(xRegister64(regt), 0x7FFFFF); + } else if (_Rd_ >= REG_STATUS_FLAG) // FixMe: Should R-Reg have upper 9 bits 0? { xMOVSX(xRegister64(regt), ptr32[&vu0Regs.VI[_Rd_].UL]);