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Removed some redundant conditionals from the testINTC and testDMAC calls in the eeRecs. 

git-svn-id: http://pcsx2-playground.googlecode.com/svn/trunk@335 a6443dda-0b58-4228-96e9-037be469359c
This commit is contained in:
Jake.Stine 2008-11-17 22:02:07 +00:00 committed by Gregory Hainaut
parent 96560444ea
commit a9e06593ba
2 changed files with 44 additions and 38 deletions
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12
pcsx2/Hw.c
View File

@ -938,16 +938,14 @@ void hwWrite32(u32 mem, u32 value) {
case 0x1000f000: // INTC_STAT
HW_LOG("INTC_STAT Write 32bit %x\n", value);
psHu32(0xf000)&=~value;
if ((cpuRegs.CP0.n.Status.val & 0x10407) == 0x10401)
cpuTestINTCInts();
cpuTestINTCInts();
break;
case 0x1000f010: // INTC_MASK
HW_LOG("INTC_MASK Write 32bit %x\n", value);
psHu32(0xf010) ^= (u16)value;
if ((cpuRegs.CP0.n.Status.val & 0x10407) == 0x10401)
cpuTestINTCInts();
cpuTestINTCInts();
break;
//------------------------------------------------------------------
case 0x1000f430://MCH_RICM: x:4|SA:12|x:5|SDEV:1|SOP:4|SBC:1|SDEV:5
@ -1086,8 +1084,7 @@ void hwWrite64(u32 mem, u64 value) {
case 0x1000f000: // INTC_STAT
HW_LOG("INTC_STAT Write 64bit %x\n", value);
psHu32(0xf000)&=~value;
if ((cpuRegs.CP0.n.Status.val & 0x10407) == 0x10401)
cpuTestINTCInts();
cpuTestINTCInts();
break;
case 0x1000f010: // INTC_MASK
@ -1099,8 +1096,7 @@ void hwWrite64(u32 mem, u64 value) {
else psHu32(0xf010)|= 1<<i;
}
}
if ((cpuRegs.CP0.n.Status.val & 0x10407) == 0x10401)
cpuTestINTCInts();
cpuTestINTCInts();
break;
case 0x1000f130:

70
pcsx2/x86/iHw.c
View File

@ -343,6 +343,8 @@ int hwConstRead32(u32 x86reg, u32 mem)
EECNT_LOG("Counter 2 target read = %x\n", counters[2].target);
return 0;
case 0x10001030:
// fixme: Counters[2].hold and Counters[3].hold are never assigned values
// anywhere in Pcsx2.
_eeReadConstMem32(x86reg, (uptr)&counters[2].hold);
return 0;
@ -362,6 +364,8 @@ int hwConstRead32(u32 x86reg, u32 mem)
EECNT_LOG("Counter 3 target read = %x\n", counters[3].target);
return 0;
case 0x10001830:
// fixme: Counters[2].hold and Counters[3].hold are never assigned values
// anywhere in Pcsx2.
_eeReadConstMem32(x86reg, (uptr)&counters[3].hold);
return 0;
@ -969,24 +973,26 @@ void hwConstWrite32(u32 mem, int mmreg)
SHR32ItoR(EAX, 16);
XOR16RtoM((uptr)&PS2MEM_HW[0xe012], EAX);
MOV32MtoR(EAX, (uptr)&cpuRegs.CP0.n.Status.val);
AND32ItoR(EAX, 0x10807);
CMP32ItoR(EAX, 0x10801);
j8Ptr[5] = JNE8(0);
// cpuRegs.CP0.n.Status.val is checked by cpuTestDMACInts.
//MOV32MtoR(EAX, (uptr)&cpuRegs.CP0.n.Status.val);
//AND32ItoR(EAX, 0x10807);
//CMP32ItoR(EAX, 0x10801);
//j8Ptr[5] = JNE8(0);
CALLFunc((uptr)cpuTestDMACInts);
x86SetJ8( j8Ptr[5] );
//x86SetJ8( j8Ptr[5] );
break;
case 0x1000f000: // INTC_STAT
_eeWriteConstMem32OP((uptr)&PS2MEM_HW[0xf000], mmreg, 2);
MOV32MtoR(EAX, (uptr)&cpuRegs.CP0.n.Status.val);
AND32ItoR(EAX, 0x10407);
CMP32ItoR(EAX, 0x10401);
j8Ptr[5] = JNE8(0);
// note: cpuRegs.CP0.n.Status.val conditional is done by cpuTestINTCInts.
//MOV32MtoR(EAX, (uptr)&cpuRegs.CP0.n.Status.val);
//AND32ItoR(EAX, 0x10407);
//CMP32ItoR(EAX, 0x10401);
//j8Ptr[5] = JNE8(0);
CALLFunc((uptr)cpuTestINTCInts);
x86SetJ8( j8Ptr[5] );
//x86SetJ8( j8Ptr[5] );
break;
case 0x1000f010: // INTC_MASK
@ -994,13 +1000,14 @@ void hwConstWrite32(u32 mem, int mmreg)
iFlushCall(0);
XOR16RtoM((uptr)&PS2MEM_HW[0xf010], EAX);
MOV32MtoR(EAX, (uptr)&cpuRegs.CP0.n.Status.val);
AND32ItoR(EAX, 0x10407);
CMP32ItoR(EAX, 0x10401);
j8Ptr[5] = JNE8(0);
// note: cpuRegs.CP0.n.Status.val conditional is done by cpuTestINTCInts.
//MOV32MtoR(EAX, (uptr)&cpuRegs.CP0.n.Status.val);
//AND32ItoR(EAX, 0x10407);
//CMP32ItoR(EAX, 0x10401);
//j8Ptr[5] = JNE8(0);
CALLFunc((uptr)cpuTestINTCInts);
x86SetJ8( j8Ptr[5] );
//x86SetJ8( j8Ptr[5] );
break;
case 0x1000f130:
@ -1181,13 +1188,14 @@ void hwConstWrite64(u32 mem, int mmreg)
SHR32ItoR(EAX, 16);
XOR16RtoM((uptr)&PS2MEM_HW[0xe012], EAX);
MOV32MtoR(EAX, (uptr)&cpuRegs.CP0.n.Status.val);
AND32ItoR(EAX, 0x10807);
CMP32ItoR(EAX, 0x10801);
j8Ptr[5] = JNE8(0);
// cpuRegs.CP0.n.Status.val is checked by cpuTestDMACInts.
//MOV32MtoR(EAX, (uptr)&cpuRegs.CP0.n.Status.val);
//AND32ItoR(EAX, 0x10807);
//CMP32ItoR(EAX, 0x10801);
//j8Ptr[5] = JNE8(0);
CALLFunc((uptr)cpuTestDMACInts);
x86SetJ8( j8Ptr[5] );
//x86SetJ8( j8Ptr[5] );
break;
case 0x1000f590: // DMAC_ENABLEW
@ -1197,13 +1205,14 @@ void hwConstWrite64(u32 mem, int mmreg)
case 0x1000f000: // INTC_STAT
_eeWriteConstMem32OP((uptr)&PS2MEM_HW[mem&0xffff], mmreg, 2);
MOV32MtoR(EAX, (uptr)&cpuRegs.CP0.n.Status.val);
AND32ItoR(EAX, 0x10407);
CMP32ItoR(EAX, 0x10401);
j8Ptr[5] = JNE8(0);
// note: cpuRegs.CP0.n.Status.val conditional is done by cpuTestINTCInts.
//MOV32MtoR(EAX, (uptr)&cpuRegs.CP0.n.Status.val);
//AND32ItoR(EAX, 0x10407);
//CMP32ItoR(EAX, 0x10401);
//j8Ptr[5] = JNE8(0);
CALLFunc((uptr)cpuTestINTCInts);
x86SetJ8( j8Ptr[5] );
//x86SetJ8( j8Ptr[5] );
break;
case 0x1000f010: // INTC_MASK
@ -1213,13 +1222,14 @@ void hwConstWrite64(u32 mem, int mmreg)
iFlushCall(0);
XOR16RtoM((uptr)&PS2MEM_HW[0xf010], EAX);
MOV32MtoR(EAX, (uptr)&cpuRegs.CP0.n.Status.val);
AND32ItoR(EAX, 0x10407);
CMP32ItoR(EAX, 0x10401);
j8Ptr[5] = JNE8(0);
// note: cpuRegs.CP0.n.Status.val conditional is done by cpuTestINTCInts.
//MOV32MtoR(EAX, (uptr)&cpuRegs.CP0.n.Status.val);
//AND32ItoR(EAX, 0x10407);
//CMP32ItoR(EAX, 0x10401);
//j8Ptr[5] = JNE8(0);
CALLFunc((uptr)cpuTestINTCInts);
x86SetJ8( j8Ptr[5] );
//x86SetJ8( j8Ptr[5] );
break;