mirror of https://github.com/PCSX2/pcsx2.git
SPU2ghz: Fixed a memory corruption bug in the rolled back DMA write code. Hopefully this DMA write code will fix that bug without breaking Arc the Lad and similar games.
git-svn-id: http://pcsx2-playground.googlecode.com/svn/trunk@334 a6443dda-0b58-4228-96e9-037be469359c
This commit is contained in:
Jake.Stine
Gregory Hainaut
parent
7e828a69ee
commit
96560444ea
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@ -492,7 +492,7 @@ BOOL CALLBACK ConfigProc(HWND hWnd,UINT uMsg,WPARAM wParam,LPARAM lParam)
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// Debugging / Logging Flags:
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SET_CHECK(IDC_EFFECTS, EffectsEnabled);
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SET_CHECK(IDC_DEBUG, DebugEnabled);
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SET_CHECK(IDC_MSGKEY, _MsgToConsole);
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SET_CHECK(IDC_MSGSHOW, _MsgToConsole);
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SET_CHECK(IDC_MSGKEY, _MsgKeyOnOff);
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SET_CHECK(IDC_MSGVOICE,_MsgVoiceOff);
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SET_CHECK(IDC_MSGDMA, _MsgDMA);
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@ -92,9 +92,9 @@ void DMALogClose() {
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__forceinline u16 DmaRead(u32 core)
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{
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Cores[core].TDA&=0xfffff;
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const u16 ret = (u16)spu2M_Read(Cores[core].TDA);
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Cores[core].TDA++;
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Cores[core].TDA&=0xfffff;
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return ret;
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}
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@ -189,27 +189,24 @@ void StartADMAWrite(int core,u16 *pMem, u32 sz)
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void DoDMAWrite(int core,u16 *pMem,u32 size)
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{
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u32 i;
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// Perform an alignment check.
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// Not really important. Everything should work regardless,
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// but it could be indicative of an emulation foopah elsewhere.
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#ifndef PUBLIC
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uptr pa = ((uptr)pMem)&7;
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uptr pm = Cores[core].TSA&0x7;
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if( pa )
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{
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// Perform an alignment check.
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// Not really important. Everything should work regardless,
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// but it could be indicative of an emulation foopah elsewhere.
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uptr pa = ((uptr)pMem)&7;
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uptr pm = Cores[core].TSA&0x7;
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if( pa )
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{
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fprintf(stderr, "* SPU2 DMA Write > Missaligned SOURCE! Core: %d TSA: 0x%x TDA: 0x%x Size: 0x%x\n", core, Cores[core].TSA, Cores[core].TDA, size);
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}
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if( pm )
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{
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fprintf(stderr, "* SPU2 DMA Write > Missaligned TARGET! Core: %d TSA: 0x%x TDA: 0x%x Size: 0x%x\n", core, Cores[core].TSA, Cores[core].TDA, size );
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}
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fprintf(stderr, "* SPU2 DMA Write > Missaligned SOURCE! Core: %d TSA: 0x%x TDA: 0x%x Size: 0x%x\n", core, Cores[core].TSA, Cores[core].TDA, size);
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}
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if( pm )
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{
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fprintf(stderr, "* SPU2 DMA Write > Missaligned TARGET! Core: %d TSA: 0x%x TDA: 0x%x Size: 0x%x\n", core, Cores[core].TSA, Cores[core].TDA, size );
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}
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#endif
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if(core==0)
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DMA4LogWrite(pMem,size<<1);
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@ -218,49 +215,91 @@ void DoDMAWrite(int core,u16 *pMem,u32 size)
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if(MsgDMA()) ConLog(" * SPU2: DMA%c Transfer of %d bytes to %x (%02x %x %04x).\n",(core==0)?'4':'7',size<<1,Cores[core].TSA,Cores[core].DMABits,Cores[core].AutoDMACtrl,(~Cores[core].Regs.ATTR)&0x7fff);
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// Optimized!
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// Instead of checking the adpcm cache for every word, we check for every block.
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// split the DMA copy into two chunks if needed.
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// Instead of checking the adpcm cache for every word, we check for every ADPCM block.
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// That way we can use the optimized fast write instruction to commit the memory.
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Cores[core].TDA = Cores[core].TSA & 0xfffff;
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Cores[core].TSA &= 0xfffff;
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u32 buff1end = Cores[core].TSA + size;
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u32 buff2end=0;
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if( buff1end > 0xfffff )
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{
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u32 nexta = Cores[core].TDA >> 3;
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u32 flagbitmask = 1ul << ( nexta & 31 );
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nexta >>= 5;
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buff2end = buff1end - 0xfffff;
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buff1end = 0xfffff;
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}
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// Traverse from start to finish in 8 word blocks,
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// and clear the pcm cache flag for each block.
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u32 stmp = ( size + 7 ) >> 3; // round up
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for( i=0; i<stmp; i++ )
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// Ideally we would only mask bits actually written to, but it's a complex algorithm
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// that is way more work than it's worth. Instead we just mask out entire bytes, which
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// means that in rare cases some games may end up having to re-decode some blocks
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// unnecessarily. To minimize the chance of that, I mask at the byte level instead
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// of the dword level, so at worst there are only 7 extra blocks to the front or back
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// of the DMA transfer that get cleared when they shouldn't be.
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// First Branch needs cleared:
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// It starts at TSA and goes to buff1end.
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const u32 buff1size = (buff1end-Cores[core].TSA);
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memcpy( GetMemPtr( Cores[core].TSA ), pMem, buff1size*2 );
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// Note: When clearing cache flags, the *endpoint* needs to be rounded upward.
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// just rounding the count upward could cause problems if both start and end
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// points are mis-aligned.
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const u32 roundUp = (1<<(3+3))-1;
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const u32 flagTSA = Cores[core].TSA >> (3+3);
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const u32 flagTDA = (buff1end + roundUp) >> (3 + 3); // endpoint, rounded up
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u8* cache = (u8*)pcm_cache_flags;
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memset( &cache[flagTSA], 0, flagTDA - flagTSA );
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if( buff2end > 0 )
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{
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// second branch needs cleared:
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// It starts at the beginning of memory and moves forward to buff2end
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const u32 endpt2 = (buff2end + roundUp) >> (3+3);
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memcpy( GetMemPtr( 0 ), &pMem[buff1size], buff2end*2 );
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memset( pcm_cache_flags, 0, endpt2 );
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Cores[core].TDA = buff2end;
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if(Cores[core].IRQEnable)
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{
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pcm_cache_flags[nexta] &= ~flagbitmask;
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flagbitmask <<= 1;
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if( flagbitmask == 0 )
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// Flag interrupt?
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// If IRQA occurs between start and dest, flag it.
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// Since the buffer wraps, the conditional might seem odd, but it works.
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if( ( Cores[core].IRQA >= Cores[core].TSA ) ||
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( Cores[core].IRQA <= Cores[core].TDA ) )
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{
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nexta++;
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flagbitmask = 1;
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Spdif.Info=4<<core;
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SetIrqCall();
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}
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}
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}
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else
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{
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// Buffer doesn't wrap/overflow!
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// Just set the TDA and check for an IRQ...
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Cores[core].TDA = buff1end;
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if(Cores[core].IRQEnable)
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{
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// Flag interrupt?
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// If IRQA occurs between start and dest, flag it:
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if( ( Cores[core].IRQA >= Cores[core].TSA ) &&
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( Cores[core].IRQA <= Cores[core].TDA ) )
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{
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Spdif.Info=4<<core;
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SetIrqCall();
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}
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}
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}
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for(i=0;i<size;i++)
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{
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*GetMemPtr( Cores[core].TDA ) = pMem[i];
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//spu2M_Write( Cores[core].TDA, pMem[i] );
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Cores[core].TDA++;
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Cores[core].TDA&=0xfffff;
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}
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i=Cores[core].TSA;
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Cores[core].TDA=Cores[core].TSA+size;
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if((Cores[core].TDA>0xFFFFF)||((Cores[core].TDA>=Cores[core].IRQA)&&(i<=Cores[core].IRQA))) {
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if(Cores[core].IRQEnable)
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{
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Spdif.Info=4<<core;
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SetIrqCall();
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}
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}
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Cores[core].TSA=Cores[core].TDA&0xFFFF0;
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Cores[core].DMAICounter=size;
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Cores[core].TADR=Cores[core].MADR+(size<<1);
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@ -321,7 +360,6 @@ void SPU2writeDMA(int core, u16* pMem, u32 size)
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}
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else
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{
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DoDMAWrite(core,pMem,size);
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}
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Cores[core].Regs.STATX &= ~0x80;
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@ -382,3 +420,4 @@ void CALLBACK SPU2interruptDMA7() {
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Cores[1].Regs.STATX |= 0x80;
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//Cores[1].Regs.ATTR &= ~0x30;
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}
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@ -22,9 +22,6 @@
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#include "regtable.h"
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#include "svnrev.h"
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// DLL Interface exportation:
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void StartVoices(int core, u32 value);
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void StopVoices(int core, u32 value);
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@ -456,7 +453,8 @@ EXPORT_C_(s32) SPU2open(void *pDsp)
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FileLog("[%10d] SPU2 Open\n",Cycles);
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/*if(debugDialogOpen==0)
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/*
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if(debugDialogOpen==0)
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{
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hDebugDialog = CreateDialogParam(hInstance,MAKEINTRESOURCE(IDD_DEBUG),0,DebugProc,0);
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ShowWindow(hDebugDialog,SW_SHOWNORMAL);
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@ -656,7 +654,7 @@ void UpdateDebugDialog()
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{
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printf(" *** Warning! Core %d Voice %d: StartA should be %06x, and is %06x.\n",
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c,v,vcd.lastSetStartA,vc.StartA);
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vcd.lastSetStartA = vcd.lastSetStartA;
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vcd.lastSetStartA = vc.StartA;
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}
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}
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}
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@ -715,12 +713,11 @@ void __fastcall TimeUpdate(u32 cClocks)
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lClocks = cClocks-dClocks;
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}
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//UpdateDebugDialog();
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//Update Mixing Progress
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while(dClocks>=TickInterval)
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{
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//UpdateDebugDialog();
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if(has_to_call_irq)
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{
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ConLog(" * SPU2: Irq Called (%04x).\n",Spdif.Info);
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@ -889,7 +886,7 @@ void UpdateSpdifMode()
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__forceinline void RegLog(int level, char *RName,u32 mem,u32 core,u16 value)
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{
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if(level>1)
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if( level > 1 )
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FileLog("[%10d] SPU2 write mem %08x (core %d, register %s) value %04x\n",Cycles,mem,core,RName,value);
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}
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@ -1601,12 +1598,11 @@ static __forceinline void SPU2_FastWrite( u32 rmem, u16 value )
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break;
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default:
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SPU2writeLog(mem,value);
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*(regtable[mem>>1])=value;
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break;
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}
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SPU2writeLog(mem,value);
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if ((mem>=0x07C0) && (mem<0x07CE))
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{
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UpdateSpdifMode();
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@ -1932,7 +1928,7 @@ void VoiceStart(int core,int vc)
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{
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if(Cores[core].Voices[vc].StartA&7)
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{
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printf(" *** Missaligned StartA %05x!\n",Cores[core].Voices[vc].StartA);
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fprintf( stderr, " *** Missaligned StartA %05x!\n",Cores[core].Voices[vc].StartA);
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Cores[core].Voices[vc].StartA=(Cores[core].Voices[vc].StartA+0xFFFF8)+0x8;
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}
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