mirror of https://github.com/PCSX2/pcsx2.git
microVU:
-fixed problems with branches jumping to incorrect addresses -finished implementing clip flag instances -started adding operand info to logging (also logs branch jump-to addresses) git-svn-id: http://pcsx2.googlecode.com/svn/trunk@1059 96395faa-99c1-11dd-bbfe-3dabce05a288
This commit is contained in:
cottonvibes
parent
7f096c63ad
commit
a6cbab677f
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@ -84,7 +84,7 @@ namespace VU0micro
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FreezeXMMRegs(1);
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FreezeMMXRegs(1);
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runVUrec(VU0.VI[REG_TPC].UL, 0x20000, 0);
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runVUrec(VU0.VI[REG_TPC].UL, 5000, 0);
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FreezeXMMRegs(0);
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FreezeMMXRegs(0);
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}
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@ -143,7 +143,7 @@ namespace VU1micro
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FreezeXMMRegs(1);
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FreezeMMXRegs(1);
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runVUrec(VU1.VI[REG_TPC].UL, 20000, 1);
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runVUrec(VU1.VI[REG_TPC].UL, 5000, 1);
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FreezeXMMRegs(0);
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FreezeMMXRegs(0);
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}
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@ -69,12 +69,8 @@ microVUt(void) mVUreset() {
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mVUdispatcherA<vuIndex>();
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mVUdispatcherB<vuIndex>();
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// Program Variables
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// Clear All Program Data
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memset(&mVU->prog, 0, sizeof(mVU->prog));
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mVU->prog.finished = 1;
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mVU->prog.cleared = 1;
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mVU->prog.cur = -1;
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mVU->prog.total = -1;
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// Create Block Managers
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for (int i = 0; i <= mVU->prog.max; i++) {
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@ -83,6 +79,13 @@ microVUt(void) mVUreset() {
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}
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}
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// Program Variables
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mVU->prog.finished = 1;
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mVU->prog.cleared = 1;
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mVU->prog.cur = -1;
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mVU->prog.total = -1;
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//mVU->prog.lpState = &mVU->prog.prog[15].allocInfo.block.pState; // Blank Pipeline State (ToDo: finish implementation)
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// Setup Dynarec Cache Limits for Each Program
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u8* z = (mVU->cache + 512); // Dispatcher Code is in first 512 bytes
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for (int i = 0; i <= mVU->prog.max; i++) {
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@ -18,7 +18,7 @@
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#pragma once
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#define mVUdebug // Prints Extra Info to Console
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//#define mVUlogProg // Dumps MicroPrograms into microVU0.txt/microVU1.txt
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#define mVUlogProg // Dumps MicroPrograms into microVU0.txt/microVU1.txt
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#include "Common.h"
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#include "VU.h"
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#include "GS.h"
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@ -51,7 +51,7 @@ public:
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if (listSize < 0) return NULL;
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//if (blockList[0].pState.needExactMatch) { // Needs Detailed Search (Exact Match of Pipeline State)
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for (int i = 0; i <= listSize; i++) {
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if (!memcmp(pState, &blockList[i].pState, sizeof(microRegInfo))) return &blockList[i];
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if (!memcmp(pState, &blockList[i].pState, sizeof(microRegInfo) - 1)) return &blockList[i];
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}
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/*}
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else { // Can do Simple Search (Only Matches the Important Pipeline Stuff)
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@ -36,7 +36,8 @@ struct microRegInfo {
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u8 p;
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u8 r;
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u8 xgkick;
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u8 needExactMatch; // If set, block needs an exact match of pipeline state
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u8 clip;
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u8 needExactMatch; // If set, block needs an exact match of pipeline state (needs to be last byte in struct)
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};
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struct microTempRegInfo {
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@ -101,6 +101,7 @@ microVUt(void) mVUanalyzeFMAC3(int Fd, int Fs, int Ft) {
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microVUt(void) mVUanalyzeFMAC4(int Fs, int Ft) {
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microVU* mVU = mVUx;
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mVUinfo |= doClip;
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analyzeReg1(Fs);
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analyzeReg4(Ft);
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}
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@ -28,9 +28,9 @@
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mVUprint("mVUcompile branchCase"); \
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CMP16ItoM((uptr)&mVU->branch, 0); \
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incPC2(1); \
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pBlock = mVUblocks[iPC/2]->search((microRegInfo*)&mVUregs); \
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bBlock = mVUblocks[iPC/2]->search((microRegInfo*)&mVUregs); \
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incPC2(-1); \
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if (pBlock) { nJMPcc((uptr)pBlock->x86ptrStart - ((uptr)x86Ptr + 6)); } \
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if (bBlock) { nJMPcc((uptr)pBlock->x86ptrStart - ((uptr)x86Ptr + 6)); } \
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else { ajmp = JMPcc((uptr)0); } \
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break
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@ -94,8 +94,9 @@ microVUt(void) mVUsetFlags(int* bStatus, int* bMac) {
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}
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// Status/Mac Flags Setup Code
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int xStatus = 8, xMac = 8, xClip = 8; // Flag Instances start at #0 on every block ((8&3) == 0)
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int pStatus = 3, pMac = 3, pClip = 3;
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int xStatus = 8, xMac = 8; // Flag Instances start at #0 on every block ((8&3) == 0)
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int pStatus = 3, pMac = 3;
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int xClip = mVUregs.clip + 8, pClip = mVUregs.clip + 7; // Clip Instance starts from where it left off
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int xS = 0, yS = 1, zS = 0;
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int xM = 0, yM = 1, zM = 0;
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int xC = 0, yC = 1, zC = 0;
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@ -122,6 +123,7 @@ microVUt(void) mVUsetFlags(int* bStatus, int* bMac) {
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incPC2(2);
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}
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mVUcount = xCount; // Restore count
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mVUregs.clip = xClip&3; // Note: Clip timing isn't cycle-accurate between block linking; but hopefully doesn't matter
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// Setup Last 4 instances of Status/Mac flags (needed for accurate block linking)
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iPC = endPC;
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@ -238,13 +240,15 @@ microVUt(void) mVUdivSet() {
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microVUt(void) mVUendProgram() {
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microVU* mVU = mVUx;
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incCycles(55); // Ensures Valid P/Q instances
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mVUcycles -= 55;
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incCycles(100); // Ensures Valid P/Q instances (And sets all cycle data to 0)
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mVUcycles -= 100;
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if (mVU->q) { SSE2_PSHUFD_XMM_to_XMM(xmmPQ, xmmPQ, 0xe5); }
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SSE_MOVSS_XMM_to_M32((uptr)&mVU->regs->VI[REG_Q].UL, xmmPQ);
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SSE2_PSHUFD_XMM_to_XMM(xmmPQ, xmmPQ, mVU->p ? 3 : 2);
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SSE_MOVSS_XMM_to_M32((uptr)&mVU->regs->VI[REG_P].UL, xmmPQ);
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//memcpy_fast(&pBlock->pStateEnd, &mVUregs, sizeof(microRegInfo));
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//MOV32ItoM((uptr)&mVU->prog.lpState, (int)&mVUblock.pState); // Save pipeline state (clipflag instance)
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AND32ItoM((uptr)µVU0.regs->VI[REG_VPU_STAT].UL, (vuIndex ? ~0x100 : ~0x001)); // VBS0/VBS1 flag
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AND32ItoM((uptr)&mVU->regs->vifRegs->stat, ~0x4); // Clear VU 'is busy' signal for vif
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MOV32ItoM((uptr)&mVU->regs->VI[REG_TPC].UL, xPC);
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@ -290,6 +294,7 @@ microVUt(void*) __fastcall mVUcompile(u32 startPC, uptr pState) {
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for (int branch = 0;; ) {
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incPC(1);
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mVUinfo = 0;
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incCycles(1);
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startLoop();
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mVUopU<vuIndex, 0>();
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@ -326,6 +331,7 @@ microVUt(void*) __fastcall mVUcompile(u32 startPC, uptr pState) {
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if (!isBdelay) { incPC(1); }
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else {
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microBlock* bBlock = NULL;
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u32* ajmp = 0;
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switch (mVUbranch) {
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case 3: branchCase(JZ32, JNZ32); // IBEQ
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@ -365,7 +371,7 @@ microVUt(void*) __fastcall mVUcompile(u32 startPC, uptr pState) {
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}
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// Conditional Branches
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mVUprint("mVUcompile conditional branch");
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if (pBlock) { // Branch non-taken has already been compiled
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if (bBlock) { // Branch non-taken has already been compiled
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incPC(-3); // Go back to branch opcode (to get branch imm addr)
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// Check if branch-block has already been compiled
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pBlock = mVUblocks[branchAddr/8]->search((microRegInfo*)&mVUregs);
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@ -375,12 +381,17 @@ microVUt(void*) __fastcall mVUcompile(u32 startPC, uptr pState) {
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}
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else {
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uptr jumpAddr;
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incPC(1); // Get PC for branch not-taken
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u32 bPC = iPC; // mVUcompile can modify iPC and mVUregs, so back them up
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memcpy_fast(&pBlock->pStateEnd, &mVUregs, sizeof(microRegInfo));
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incPC2(1); // Get PC for branch not-taken
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if (!vuIndex) mVUcompileVU0(xPC, (uptr)&mVUregs);
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else mVUcompileVU1(xPC, (uptr)&mVUregs);
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incPC(-4); // Go back to branch opcode (to get branch imm addr)
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if (!vuIndex) jumpAddr = (uptr)mVUcompileVU0(branchAddr, (uptr)&mVUregs);
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else jumpAddr = (uptr)mVUcompileVU1(branchAddr, (uptr)&mVUregs);
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iPC = bPC;
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incPC(-3); // Go back to branch opcode (to get branch imm addr)
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if (!vuIndex) jumpAddr = (uptr)mVUcompileVU0(branchAddr, (uptr)&pBlock->pStateEnd);
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else jumpAddr = (uptr)mVUcompileVU1(branchAddr, (uptr)&pBlock->pStateEnd);
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*ajmp = (jumpAddr - ((uptr)ajmp + 4));
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}
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return thisPtr;
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@ -391,8 +402,8 @@ microVUt(void*) __fastcall mVUcompile(u32 startPC, uptr pState) {
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// Do E-bit end stuff here
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mVUendProgram<vuIndex>();
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//ToDo: Save pipeline state?
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return thisPtr;
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return thisPtr; //ToDo: Save pipeline state?
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}
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void* __fastcall mVUcompileVU0(u32 startPC, uptr pState) { return mVUcompile<0>(startPC, pState); }
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@ -103,9 +103,6 @@ microVUt(void) mVUdispatcherB() {
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}
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SSE_MOVAPS_XMM_to_M128((uptr)&mVU->regs->ACC.UL[0], xmmACC);
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//SSE_MOVSS_XMM_to_M32((uptr)&mVU->regs->VI[REG_Q].UL, xmmPQ); // ToDo: Ensure Correct Q/P instances
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//SSE2_PSHUFD_XMM_to_XMM(xmmPQ, xmmPQ, 0); // wzyx = PPPP
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//SSE_MOVSS_XMM_to_M32((uptr)&mVU->regs->VI[REG_P].UL, xmmPQ);
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// Restore cpu state
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POP32R(EDI);
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@ -47,6 +47,7 @@ microVUx(void) __mVULog(const char* fmt, ...) {
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microVUt(void) __mVUdumpProgram(int progIndex) {
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microVU* mVU = mVUx;
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bool bitX[7];
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//mVU->prog.cur = progIndex; // Needed in order to set iPC
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mVUlog("*********************\n", progIndex);
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mVUlog("* Micro-Program #%02d *\n", progIndex);
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mVUlog("*********************\n\n", progIndex);
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@ -69,6 +70,7 @@ microVUt(void) __mVUdumpProgram(int progIndex) {
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if (mVU->code & _Dbit_) {bitX[3] = 1; bitX[5] = 1;}
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if (mVU->code & _Tbit_) {bitX[4] = 1; bitX[5] = 1;}
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iPC = (i+1)/4;
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mVUopU<vuIndex, 2>();
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if (bitX[5]) {
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@ -81,6 +83,7 @@ microVUt(void) __mVUdumpProgram(int progIndex) {
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mVUlog(")");
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}
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iPC = i/4;
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mVU->code = mVU->prog.prog[progIndex].data[i];
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mVUlog("\n[%04x] (%08x) ", i*4, mVU->code);
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mVUopL<vuIndex, 2>();
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@ -431,7 +431,6 @@ microVUf(void) mVU_ESUM() {
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microVUf(void) mVU_FCAND() {
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microVU* mVU = mVUx;
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pass1 { mVUprint("clip broken"); }
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pass2 {
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mVUallocCFLAGa<vuIndex>(gprT1, fvcInstance);
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AND32ItoR(gprT1, _Imm24_);
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@ -444,7 +443,6 @@ microVUf(void) mVU_FCAND() {
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microVUf(void) mVU_FCEQ() {
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microVU* mVU = mVUx;
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pass1 { mVUprint("clip broken"); }
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pass2 {
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mVUallocCFLAGa<vuIndex>(gprT1, fvcInstance);
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XOR32ItoR(gprT1, _Imm24_);
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@ -457,7 +455,6 @@ microVUf(void) mVU_FCEQ() {
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microVUf(void) mVU_FCGET() {
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microVU* mVU = mVUx;
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pass1 { mVUprint("clip broken"); }
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pass2 {
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mVUallocCFLAGa<vuIndex>(gprT1, fvcInstance);
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AND32ItoR(gprT1, 0xfff);
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@ -468,7 +465,6 @@ microVUf(void) mVU_FCGET() {
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microVUf(void) mVU_FCOR() {
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microVU* mVU = mVUx;
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pass1 { mVUprint("clip broken"); }
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pass2 {
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mVUallocCFLAGa<vuIndex>(gprT1, fvcInstance);
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OR32ItoR(gprT1, _Imm24_);
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@ -481,7 +477,7 @@ microVUf(void) mVU_FCOR() {
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microVUf(void) mVU_FCSET() {
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microVU* mVU = mVUx;
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pass1 { mVUprint("clip broken"); }
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pass1 { mVUinfo |= doClip; }
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pass2 {
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MOV32ItoR(gprT1, _Imm24_);
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mVUallocCFLAGb<vuIndex>(gprT1, fcInstance);
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@ -660,6 +656,7 @@ microVUf(void) mVU_ISUB() {
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mVUallocVIa<vuIndex>(gprT1, _Fs_);
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mVUallocVIa<vuIndex>(gprT2, _Ft_);
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SUB16RtoR(gprT1, gprT2);
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mVUallocVIb<vuIndex>(gprT1, _Fd_);
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}
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else if (!isMMX(_Fd_)) {
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XOR32RtoR(gprT1, gprT1);
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@ -856,7 +853,7 @@ microVUf(void) mVU_LQ() {
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mVUsaveReg<vuIndex>(xmmFt, (uptr)&mVU->regs->VF[_Ft_].UL[0], _X_Y_Z_W, 1);
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}
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}
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pass3 { mVUlog("LQ"); }
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pass3 { mVUlog("LQ.%s vf%02d, vi%02d + %d", _XYZW_String, _Ft_, _Fs_, _Imm11_); }
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}
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microVUf(void) mVU_LQD() {
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@ -878,7 +875,7 @@ microVUf(void) mVU_LQD() {
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}
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}
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}
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pass3 { mVUlog("LQD"); }
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pass3 { mVUlog("LQD.%s vf%02d, --vi%02d", _XYZW_String, _Ft_, _Fs_); }
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}
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microVUf(void) mVU_LQI() {
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@ -901,7 +898,7 @@ microVUf(void) mVU_LQI() {
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mVUallocVIb<vuIndex>(gprT2, _Fs_);
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}
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}
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pass3 { mVUlog("LQI"); }
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pass3 { mVUlog("LQI.%s vf%02d, vi%02d++", _XYZW_String, _Ft_, _Fs_); }
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}
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//------------------------------------------------------------------
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@ -924,7 +921,7 @@ microVUf(void) mVU_SQ() {
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mVUsaveReg2<vuIndex>(xmmFs, gprT1, (uptr)mVU->regs->Mem, _X_Y_Z_W);
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}
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}
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pass3 { mVUlog("SQ"); }
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pass3 { mVUlog("SQ.%s vf%02d, vi%02d + %d", _XYZW_String, _Fs_, _Ft_, _Imm11_); }
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}
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microVUf(void) mVU_SQD() {
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@ -944,7 +941,7 @@ microVUf(void) mVU_SQD() {
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mVUsaveReg2<vuIndex>(xmmFs, gprT1, (uptr)mVU->regs->Mem, _X_Y_Z_W);
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}
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}
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pass3 { mVUlog("SQD"); }
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pass3 { mVUlog("SQD.%s vf%02d, --vi%02d", _XYZW_String, _Fs_, _Ft_); }
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}
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microVUf(void) mVU_SQI() {
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@ -962,10 +959,10 @@ microVUf(void) mVU_SQI() {
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getReg7(xmmFs, _Fs_);
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mVUsaveReg2<vuIndex>(xmmFs, gprT1, (uptr)mVU->regs->Mem, _X_Y_Z_W);
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ADD16ItoR(gprT2, 1);
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mVUallocVIb<vuIndex>(gprT2, _Ft_); // ToDo: Backup to memory check.
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mVUallocVIb<vuIndex>(gprT2, _Ft_);
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}
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}
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pass3 { mVUlog("SQI"); }
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pass3 { mVUlog("SQI.%s vf%02d, vi%02d++", _XYZW_String, _Fs_, _Ft_); }
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}
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//------------------------------------------------------------------
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@ -983,7 +980,7 @@ microVUf(void) mVU_RINIT() {
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}
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else MOV32ItoR(gprR, 0x3f800000);
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}
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pass3 { mVUlog("RINIT"); }
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pass3 { mVUlog("RINIT R, vf%02d%s", _Fs_, _Fsf_String); }
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}
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microVUt(void) mVU_RGET_() {
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@ -1000,7 +997,7 @@ microVUf(void) mVU_RGET() {
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microVU* mVU = mVUx;
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pass1 { mVUanalyzeR2<vuIndex>(_Ft_, 1); }
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pass2 { mVU_RGET_<vuIndex>(); }
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pass3 { mVUlog("RGET"); }
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pass3 { mVUlog("RGET.%s vf%02d, R", _XYZW_String, _Ft_); }
|
||||
}
|
||||
|
||||
microVUf(void) mVU_RNEXT() {
|
||||
|
|
@ -1023,7 +1020,7 @@ microVUf(void) mVU_RNEXT() {
|
|||
OR32ItoR (gprR, 0x3f800000);
|
||||
mVU_RGET_<vuIndex>();
|
||||
}
|
||||
pass3 { mVUlog("RNEXT"); }
|
||||
pass3 { mVUlog("RNEXT.%s vf%02d, R", _XYZW_String, _Ft_); }
|
||||
}
|
||||
|
||||
microVUf(void) mVU_RXOR() {
|
||||
|
|
@ -1036,7 +1033,7 @@ microVUf(void) mVU_RXOR() {
|
|||
XOR32RtoR(gprR, gprT1);
|
||||
}
|
||||
}
|
||||
pass3 { mVUlog("RXOR"); }
|
||||
pass3 { mVUlog("RXOR R, vf%02d%s", _Fs_, _Fsf_String); }
|
||||
}
|
||||
|
||||
//------------------------------------------------------------------
|
||||
|
|
@ -1066,7 +1063,7 @@ microVUf(void) mVU_XTOP() {
|
|||
MOVZX32M16toR(gprT1, (uptr)&mVU->regs->vifRegs->top);
|
||||
mVUallocVIb<vuIndex>(gprT1, _Ft_);
|
||||
}
|
||||
pass3 { mVUlog("XTOP"); }
|
||||
pass3 { mVUlog("XTOP vi%02d", _Ft_); }
|
||||
}
|
||||
|
||||
microVUf(void) mVU_XITOP() {
|
||||
|
|
@ -1076,7 +1073,7 @@ microVUf(void) mVU_XITOP() {
|
|||
MOVZX32M16toR(gprT1, (uptr)&mVU->regs->vifRegs->itop);
|
||||
mVUallocVIb<vuIndex>(gprT1, _Ft_);
|
||||
}
|
||||
pass3 { mVUlog("XITOP"); }
|
||||
pass3 { mVUlog("XITOP vi%02d", _Ft_); }
|
||||
}
|
||||
|
||||
//------------------------------------------------------------------
|
||||
|
|
@ -1101,7 +1098,7 @@ microVUf(void) mVU_XGKICK() {
|
|||
CALLFunc((uptr)mVU_XGKICK_);
|
||||
POP32R(gprR); // Restore
|
||||
}
|
||||
pass3 { mVUlog("XGKICK"); }
|
||||
pass3 { mVUlog("XGKICK vi%02d", _Fs_); }
|
||||
}
|
||||
|
||||
//------------------------------------------------------------------
|
||||
|
|
@ -1111,7 +1108,7 @@ microVUf(void) mVU_XGKICK() {
|
|||
microVUf(void) mVU_B() {
|
||||
microVU* mVU = mVUx;
|
||||
mVUbranch = 1;
|
||||
pass3 { mVUlog("B"); }
|
||||
pass3 { mVUlog("B [%04x]", branchAddr); }
|
||||
}
|
||||
microVUf(void) mVU_BAL() {
|
||||
microVU* mVU = mVUx;
|
||||
|
|
@ -1120,11 +1117,8 @@ microVUf(void) mVU_BAL() {
|
|||
pass2 {
|
||||
MOV32ItoR(gprT1, bSaveAddr);
|
||||
mVUallocVIb<vuIndex>(gprT1, _Ft_);
|
||||
// Note: Not sure if the lower instruction in the branch-delay slot
|
||||
// should read the previous VI-value or the VI-value resulting from this branch.
|
||||
// This code does the latter...
|
||||
}
|
||||
pass3 { mVUlog("BAL"); }
|
||||
pass3 { mVUlog("BAL vi%02d [%04x]", _Ft_, branchAddr); }
|
||||
}
|
||||
microVUf(void) mVU_IBEQ() {
|
||||
microVU* mVU = mVUx;
|
||||
|
|
@ -1137,7 +1131,7 @@ microVUf(void) mVU_IBEQ() {
|
|||
else { mVUallocVIa<vuIndex>(gprT2, _Ft_); XOR32RtoR(gprT1, gprT2); }
|
||||
MOV32RtoM((uptr)&mVU->branch, gprT1);
|
||||
}
|
||||
pass3 { mVUlog("IBEQ"); }
|
||||
pass3 { mVUlog("IBEQ vi%02d, vi%02d [%04x]", _Ft_, _Fs_, branchAddr); }
|
||||
}
|
||||
microVUf(void) mVU_IBGEZ() {
|
||||
microVU* mVU = mVUx;
|
||||
|
|
@ -1148,7 +1142,7 @@ microVUf(void) mVU_IBGEZ() {
|
|||
else mVUallocVIa<vuIndex>(gprT1, _Fs_);
|
||||
MOV32RtoM((uptr)&mVU->branch, gprT1);
|
||||
}
|
||||
pass3 { mVUlog("IBGEZ"); }
|
||||
pass3 { mVUlog("IBGEZ vi%02d [%04x]", _Fs_, branchAddr); }
|
||||
}
|
||||
microVUf(void) mVU_IBGTZ() {
|
||||
microVU* mVU = mVUx;
|
||||
|
|
@ -1159,7 +1153,7 @@ microVUf(void) mVU_IBGTZ() {
|
|||
else mVUallocVIa<vuIndex>(gprT1, _Fs_);
|
||||
MOV32RtoM((uptr)&mVU->branch, gprT1);
|
||||
}
|
||||
pass3 { mVUlog("IBGTZ"); }
|
||||
pass3 { mVUlog("IBGTZ vi%02d [%04x]", _Fs_, branchAddr); }
|
||||
}
|
||||
microVUf(void) mVU_IBLEZ() {
|
||||
microVU* mVU = mVUx;
|
||||
|
|
@ -1170,7 +1164,7 @@ microVUf(void) mVU_IBLEZ() {
|
|||
else mVUallocVIa<vuIndex>(gprT1, _Fs_);
|
||||
MOV32RtoM((uptr)&mVU->branch, gprT1);
|
||||
}
|
||||
pass3 { mVUlog("IBLEZ"); }
|
||||
pass3 { mVUlog("IBLEZ vi%02d [%04x]", _Fs_, branchAddr); }
|
||||
}
|
||||
microVUf(void) mVU_IBLTZ() {
|
||||
microVU* mVU = mVUx;
|
||||
|
|
@ -1181,7 +1175,7 @@ microVUf(void) mVU_IBLTZ() {
|
|||
else mVUallocVIa<vuIndex>(gprT1, _Fs_);
|
||||
MOV32RtoM((uptr)&mVU->branch, gprT1);
|
||||
}
|
||||
pass3 { mVUlog("IBLTZ"); }
|
||||
pass3 { mVUlog("IBLTZ vi%02d [%04x]", _Fs_, branchAddr); }
|
||||
}
|
||||
microVUf(void) mVU_IBNE() {
|
||||
microVU* mVU = mVUx;
|
||||
|
|
@ -1194,7 +1188,7 @@ microVUf(void) mVU_IBNE() {
|
|||
else { mVUallocVIa<vuIndex>(gprT2, _Ft_); XOR32RtoR(gprT1, gprT2); }
|
||||
MOV32RtoM((uptr)&mVU->branch, gprT1);
|
||||
}
|
||||
pass3 { mVUlog("IBNE"); }
|
||||
pass3 { mVUlog("IBNE vi%02d, vi%02d [%04x]", _Ft_, _Fs_, branchAddr); }
|
||||
}
|
||||
microVUf(void) mVU_JR() {
|
||||
microVU* mVU = mVUx;
|
||||
|
|
@ -1205,7 +1199,7 @@ microVUf(void) mVU_JR() {
|
|||
else mVUallocVIa<vuIndex>(gprT1, _Fs_);
|
||||
MOV32RtoM((uptr)&mVU->branch, gprT1);
|
||||
}
|
||||
pass3 { mVUlog("JR"); }
|
||||
pass3 { mVUlog("JR [vi%02d]", _Fs_); }
|
||||
}
|
||||
microVUf(void) mVU_JALR() {
|
||||
microVU* mVU = mVUx;
|
||||
|
|
@ -1217,11 +1211,8 @@ microVUf(void) mVU_JALR() {
|
|||
MOV32RtoM((uptr)&mVU->branch, gprT1);
|
||||
MOV32ItoR(gprT1, bSaveAddr);
|
||||
mVUallocVIb<vuIndex>(gprT1, _Ft_);
|
||||
// Note: Not sure if the lower instruction in the branch-delay slot
|
||||
// should read the previous VI-value or the VI-value resulting from this branch.
|
||||
// This code does the latter...
|
||||
}
|
||||
pass3 { mVUlog("JALR"); }
|
||||
pass3 { mVUlog("JALR vi%02d, [vi%02d]", _Ft_, _Fs_); }
|
||||
}
|
||||
|
||||
#endif //PCSX2_MICROVU
|
||||
|
|
|
|||
|
|
@ -89,8 +89,8 @@ declareAllVariables
|
|||
#define _Ftf_ ((mVU->code >> 23) & 0x03)
|
||||
|
||||
#define _Imm5_ (((mVU->code & 0x400) ? 0xfff0 : 0) | ((mVU->code >> 6) & 0xf))
|
||||
#define _Imm11_ (s32)(mVU->code & 0x400 ? 0xfffffc00 | (mVU->code & 0x3ff) : mVU->code & 0x3ff)
|
||||
#define _Imm12_ (((mVU->code >> 21 ) & 0x1) << 11) | (mVU->code & 0x7ff)
|
||||
#define _Imm11_ (s32)((mVU->code & 0x400) ? (0xfffffc00 | (mVU->code & 0x3ff)) : mVU->code & 0x3ff)
|
||||
#define _Imm12_ (((mVU->code >> 21) & 0x1) << 11) | (mVU->code & 0x7ff)
|
||||
#define _Imm15_ (((mVU->code >> 10) & 0x7800) | (mVU->code & 0x7ff))
|
||||
#define _Imm24_ (u32)(mVU->code & 0xffffff)
|
||||
|
||||
|
|
@ -162,8 +162,12 @@ declareAllVariables
|
|||
#define incPC2(x) { iPC = ((iPC + x) & (mVU->progSize-1)); }
|
||||
#define incCycles(x) { mVUincCycles<vuIndex>(x); }
|
||||
#define bSaveAddr ((xPC + (2 * 8)) & ((vuIndex) ? 0x3ff8:0xff8))
|
||||
#define branchAddr ((xPC + (_Imm11_ * 8)) & ((vuIndex) ? 0x3ff8:0xff8))
|
||||
#define branchAddr ((xPC + 8 + (_Imm11_ * 8)) & ((vuIndex) ? 0x3ff8:0xff8))
|
||||
#define shufflePQ (((mVU->q) ? 0xb0 : 0xe0) | ((mVU->q) ? 0x01 : 0x04))
|
||||
#define _Fsf_String ((_Fsf_ == 3) ? "w" : ((_Fsf_ == 2) ? "z" : ((_Fsf_ == 1) ? "y" : "x")))
|
||||
#define _Ftf_String ((_Ftf_ == 3) ? "w" : ((_Ftf_ == 2) ? "z" : ((_Ftf_ == 1) ? "y" : "x")))
|
||||
#define xyzwStr(x,s) (_X_Y_Z_W == x) ? s :
|
||||
#define _XYZW_String (xyzwStr(1, "w") (xyzwStr(2, "z") (xyzwStr(3, "zw") (xyzwStr(4, "y") (xyzwStr(5, "yw") (xyzwStr(6, "yz") (xyzwStr(7, "yzw") (xyzwStr(8, "x") (xyzwStr(9, "xw") (xyzwStr(10, "xz") (xyzwStr(11, "xzw") (xyzwStr(12, "xy") (xyzwStr(13, "xyw") (xyzwStr(14, "xyz") "xyzw"))))))))))))))
|
||||
|
||||
|
||||
#define _isNOP (1<<0) // Skip Lower Instruction
|
||||
|
|
|
|||
|
|
@ -1077,8 +1077,7 @@ microVUf(void) mVULowerOP_T3_11() { doTableStuff(mVULowerOP_T3_11_OPCODE, ((mVUg
|
|||
microVUf(void) mVUopU() { doTableStuff(mVU_UPPER_OPCODE, (mVUgetCode & 0x3f)); } // Gets Upper Opcode
|
||||
microVUf(void) mVUopL() { doTableStuff(mVULOWER_OPCODE, (mVUgetCode >> 25)); } // Gets Lower Opcode
|
||||
microVUf(void) mVUunknown() {
|
||||
SysPrintf("mVUunknown<%d,%d> : Unknown Micro VU opcode called (%x)\n", vuIndex, recPass, mVUgetCode);
|
||||
//pass2 { write8(0xcc); }
|
||||
pass2 { SysPrintf("microVU%d: Unknown Micro VU opcode called (%x)\n", vuIndex, mVUgetCode); }
|
||||
pass3 { mVUlog("Unknown", mVUgetCode); }
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -603,7 +603,7 @@ microVUf(void) mVU_ITOF12() { mVU_ITOFx<vuIndex, recPass>((uptr)mVU_ITOF_12); p
|
|||
microVUf(void) mVU_ITOF15() { mVU_ITOFx<vuIndex, recPass>((uptr)mVU_ITOF_15); pass3 { mVUlog("ITOF15"); } }
|
||||
microVUf(void) mVU_CLIP() {
|
||||
microVU* mVU = mVUx;
|
||||
pass1 { mVUanalyzeFMAC4<vuIndex>(_Fs_, _Ft_); mVUprint("clip broken"); }
|
||||
pass1 { mVUanalyzeFMAC4<vuIndex>(_Fs_, _Ft_); }
|
||||
pass2 {
|
||||
int Fs, Ft;
|
||||
mVUallocFMAC17a<vuIndex>(Fs, Ft);
|
||||
|
|
|
|||
Loading…
Reference in New Issue