diff --git a/pcsx2/x86/iVU0micro.cpp b/pcsx2/x86/iVU0micro.cpp
index bbc9b64cc9..1a2ee09ea7 100644
--- a/pcsx2/x86/iVU0micro.cpp
+++ b/pcsx2/x86/iVU0micro.cpp
@@ -84,7 +84,7 @@ namespace VU0micro
 
 		FreezeXMMRegs(1);
 		FreezeMMXRegs(1);
-		runVUrec(VU0.VI[REG_TPC].UL, 0x20000, 0);
+		runVUrec(VU0.VI[REG_TPC].UL, 5000, 0);
 		FreezeXMMRegs(0);
 		FreezeMMXRegs(0);
 	}
diff --git a/pcsx2/x86/iVU1micro.cpp b/pcsx2/x86/iVU1micro.cpp
index 93c43b36af..d282778f4c 100644
--- a/pcsx2/x86/iVU1micro.cpp
+++ b/pcsx2/x86/iVU1micro.cpp
@@ -143,7 +143,7 @@ namespace VU1micro
 
 		FreezeXMMRegs(1);
 		FreezeMMXRegs(1);
-		runVUrec(VU1.VI[REG_TPC].UL, 20000, 1);
+		runVUrec(VU1.VI[REG_TPC].UL, 5000, 1);
 		FreezeXMMRegs(0);
 		FreezeMMXRegs(0);
 	}
diff --git a/pcsx2/x86/microVU.cpp b/pcsx2/x86/microVU.cpp
index ae11ad3b1a..daa5f01ad3 100644
--- a/pcsx2/x86/microVU.cpp
+++ b/pcsx2/x86/microVU.cpp
@@ -69,12 +69,8 @@ microVUt(void) mVUreset() {
 	mVUdispatcherA<vuIndex>();
 	mVUdispatcherB<vuIndex>();
 
-	// Program Variables
+	// Clear All Program Data
 	memset(&mVU->prog, 0, sizeof(mVU->prog));
-	mVU->prog.finished = 1;
-	mVU->prog.cleared = 1;
-	mVU->prog.cur = -1;
-	mVU->prog.total = -1;
 
 	// Create Block Managers
 	for (int i = 0; i <= mVU->prog.max; i++) {
@@ -83,6 +79,13 @@ microVUt(void) mVUreset() {
 		}
 	}
 
+	// Program Variables
+	mVU->prog.finished = 1;
+	mVU->prog.cleared = 1;
+	mVU->prog.cur = -1;
+	mVU->prog.total = -1;
+	//mVU->prog.lpState = &mVU->prog.prog[15].allocInfo.block.pState; // Blank Pipeline State (ToDo: finish implementation)
+
 	// Setup Dynarec Cache Limits for Each Program
 	u8* z = (mVU->cache + 512); // Dispatcher Code is in first 512 bytes
 	for (int i = 0; i <= mVU->prog.max; i++) {
diff --git a/pcsx2/x86/microVU.h b/pcsx2/x86/microVU.h
index 0447c68676..78cd364220 100644
--- a/pcsx2/x86/microVU.h
+++ b/pcsx2/x86/microVU.h
@@ -18,7 +18,7 @@
 
 #pragma once
 #define mVUdebug	// Prints Extra Info to Console
-//#define mVUlogProg	// Dumps MicroPrograms into microVU0.txt/microVU1.txt
+#define mVUlogProg	// Dumps MicroPrograms into microVU0.txt/microVU1.txt
 #include "Common.h"
 #include "VU.h"
 #include "GS.h"
@@ -51,7 +51,7 @@ public:
 		if (listSize < 0) return NULL;
 		//if (blockList[0].pState.needExactMatch) { // Needs Detailed Search (Exact Match of Pipeline State)
 			for (int i = 0; i <= listSize; i++) {
-				if (!memcmp(pState, &blockList[i].pState, sizeof(microRegInfo))) return &blockList[i];
+				if (!memcmp(pState, &blockList[i].pState, sizeof(microRegInfo) - 1)) return &blockList[i];
 			}
 		/*}
 		else { // Can do Simple Search (Only Matches the Important Pipeline Stuff)
diff --git a/pcsx2/x86/microVU_Alloc.h b/pcsx2/x86/microVU_Alloc.h
index b1f1bbdc24..a16c3f4396 100644
--- a/pcsx2/x86/microVU_Alloc.h
+++ b/pcsx2/x86/microVU_Alloc.h
@@ -36,7 +36,8 @@ struct microRegInfo {
 	u8 p;
 	u8 r;
 	u8 xgkick;
-	u8 needExactMatch; // If set, block needs an exact match of pipeline state
+	u8 clip;
+	u8 needExactMatch; // If set, block needs an exact match of pipeline state (needs to be last byte in struct)
 };
 
 struct microTempRegInfo {
diff --git a/pcsx2/x86/microVU_Analyze.inl b/pcsx2/x86/microVU_Analyze.inl
index 0605559741..7a1992570f 100644
--- a/pcsx2/x86/microVU_Analyze.inl
+++ b/pcsx2/x86/microVU_Analyze.inl
@@ -101,6 +101,7 @@ microVUt(void) mVUanalyzeFMAC3(int Fd, int Fs, int Ft) {
 
 microVUt(void) mVUanalyzeFMAC4(int Fs, int Ft) {
 	microVU* mVU = mVUx;
+	mVUinfo |= doClip;
 	analyzeReg1(Fs);
 	analyzeReg4(Ft);
 }
diff --git a/pcsx2/x86/microVU_Compile.inl b/pcsx2/x86/microVU_Compile.inl
index 09a81815f5..aa60df2037 100644
--- a/pcsx2/x86/microVU_Compile.inl
+++ b/pcsx2/x86/microVU_Compile.inl
@@ -28,9 +28,9 @@
 	mVUprint("mVUcompile branchCase");										\
 	CMP16ItoM((uptr)&mVU->branch, 0);										\
 	incPC2(1);																\
-	pBlock = mVUblocks[iPC/2]->search((microRegInfo*)&mVUregs);				\
+	bBlock = mVUblocks[iPC/2]->search((microRegInfo*)&mVUregs);				\
 	incPC2(-1);																\
-	if (pBlock)	{ nJMPcc((uptr)pBlock->x86ptrStart - ((uptr)x86Ptr + 6)); }	\
+	if (bBlock)	{ nJMPcc((uptr)pBlock->x86ptrStart - ((uptr)x86Ptr + 6)); }	\
 	else		{ ajmp = JMPcc((uptr)0); }									\
 	break
 
@@ -94,8 +94,9 @@ microVUt(void) mVUsetFlags(int* bStatus, int* bMac) {
 	}
 
 	// Status/Mac Flags Setup Code
-	int xStatus	= 8, xMac = 8, xClip = 8; // Flag Instances start at #0 on every block ((8&3) == 0)
-	int pStatus	= 3, pMac = 3, pClip = 3;
+	int xStatus	= 8, xMac = 8; // Flag Instances start at #0 on every block ((8&3) == 0)
+	int pStatus	= 3, pMac = 3;
+	int xClip = mVUregs.clip + 8, pClip = mVUregs.clip + 7; // Clip Instance starts from where it left off
 	int xS = 0, yS = 1, zS = 0;
 	int xM = 0, yM = 1, zM = 0;
 	int xC = 0, yC = 1, zC = 0;
@@ -122,6 +123,7 @@ microVUt(void) mVUsetFlags(int* bStatus, int* bMac) {
 		incPC2(2);
 	}
 	mVUcount = xCount; // Restore count
+	mVUregs.clip = xClip&3; // Note: Clip timing isn't cycle-accurate between block linking; but hopefully doesn't matter
 
 	// Setup Last 4 instances of Status/Mac flags (needed for accurate block linking)
 	iPC = endPC;
@@ -238,13 +240,15 @@ microVUt(void) mVUdivSet() {
 
 microVUt(void) mVUendProgram() {
 	microVU* mVU = mVUx;
-	incCycles(55); // Ensures Valid P/Q instances
-	mVUcycles -= 55;
+	incCycles(100); // Ensures Valid P/Q instances (And sets all cycle data to 0)
+	mVUcycles -= 100;
 	if (mVU->q) { SSE2_PSHUFD_XMM_to_XMM(xmmPQ, xmmPQ, 0xe5); }
 	SSE_MOVSS_XMM_to_M32((uptr)&mVU->regs->VI[REG_Q].UL, xmmPQ);
 	SSE2_PSHUFD_XMM_to_XMM(xmmPQ, xmmPQ, mVU->p ? 3 : 2);
 	SSE_MOVSS_XMM_to_M32((uptr)&mVU->regs->VI[REG_P].UL, xmmPQ);
 
+	//memcpy_fast(&pBlock->pStateEnd, &mVUregs, sizeof(microRegInfo));
+	//MOV32ItoM((uptr)&mVU->prog.lpState, (int)&mVUblock.pState); // Save pipeline state (clipflag instance)
 	AND32ItoM((uptr)&microVU0.regs->VI[REG_VPU_STAT].UL, (vuIndex ? ~0x100 : ~0x001)); // VBS0/VBS1 flag
 	AND32ItoM((uptr)&mVU->regs->vifRegs->stat, ~0x4); // Clear VU 'is busy' signal for vif
 	MOV32ItoM((uptr)&mVU->regs->VI[REG_TPC].UL, xPC);
@@ -290,6 +294,7 @@ microVUt(void*) __fastcall mVUcompile(u32 startPC, uptr pState) {
 
 	for (int branch = 0;; ) {
 		incPC(1);
+		mVUinfo = 0;
 		incCycles(1);
 		startLoop();
 		mVUopU<vuIndex, 0>();
@@ -326,6 +331,7 @@ microVUt(void*) __fastcall mVUcompile(u32 startPC, uptr pState) {
 		
 		if (!isBdelay) { incPC(1); }
 		else {
+			microBlock* bBlock = NULL;
 			u32* ajmp = 0;
 			switch (mVUbranch) {
 				case 3: branchCase(JZ32,  JNZ32);	// IBEQ
@@ -365,7 +371,7 @@ microVUt(void*) __fastcall mVUcompile(u32 startPC, uptr pState) {
 			}
 			// Conditional Branches
 			mVUprint("mVUcompile conditional branch");
-			if (pBlock) { // Branch non-taken has already been compiled
+			if (bBlock) { // Branch non-taken has already been compiled
 				incPC(-3); // Go back to branch opcode (to get branch imm addr)
 				// Check if branch-block has already been compiled
 				pBlock = mVUblocks[branchAddr/8]->search((microRegInfo*)&mVUregs);
@@ -375,12 +381,17 @@ microVUt(void*) __fastcall mVUcompile(u32 startPC, uptr pState) {
 			}
 			else {
 				uptr jumpAddr;
-				incPC(1);  // Get PC for branch not-taken
+				u32 bPC = iPC; // mVUcompile can modify iPC and mVUregs, so back them up
+				memcpy_fast(&pBlock->pStateEnd, &mVUregs, sizeof(microRegInfo));
+	
+				incPC2(1);  // Get PC for branch not-taken
 				if (!vuIndex) mVUcompileVU0(xPC, (uptr)&mVUregs);
 				else		  mVUcompileVU1(xPC, (uptr)&mVUregs);
-				incPC(-4); // Go back to branch opcode (to get branch imm addr)
-				if (!vuIndex) jumpAddr = (uptr)mVUcompileVU0(branchAddr, (uptr)&mVUregs);
-				else		  jumpAddr = (uptr)mVUcompileVU1(branchAddr, (uptr)&mVUregs);
+
+				iPC = bPC;
+				incPC(-3); // Go back to branch opcode (to get branch imm addr)
+				if (!vuIndex) jumpAddr = (uptr)mVUcompileVU0(branchAddr, (uptr)&pBlock->pStateEnd);
+				else		  jumpAddr = (uptr)mVUcompileVU1(branchAddr, (uptr)&pBlock->pStateEnd);
 				*ajmp = (jumpAddr - ((uptr)ajmp + 4));
 			}
 			return thisPtr;
@@ -391,8 +402,8 @@ microVUt(void*) __fastcall mVUcompile(u32 startPC, uptr pState) {
 
 	// Do E-bit end stuff here
 	mVUendProgram<vuIndex>();
-	//ToDo: Save pipeline state?
-	return thisPtr;
+
+	return thisPtr; //ToDo: Save pipeline state?
 }
 
 void* __fastcall mVUcompileVU0(u32 startPC, uptr pState) { return mVUcompile<0>(startPC, pState); }
diff --git a/pcsx2/x86/microVU_Execute.inl b/pcsx2/x86/microVU_Execute.inl
index ebb5b3c633..ff892ab0ca 100644
--- a/pcsx2/x86/microVU_Execute.inl
+++ b/pcsx2/x86/microVU_Execute.inl
@@ -103,9 +103,6 @@ microVUt(void) mVUdispatcherB() {
 	}
 
 	SSE_MOVAPS_XMM_to_M128((uptr)&mVU->regs->ACC.UL[0], xmmACC);
-	//SSE_MOVSS_XMM_to_M32((uptr)&mVU->regs->VI[REG_Q].UL, xmmPQ); // ToDo: Ensure Correct Q/P instances
-	//SSE2_PSHUFD_XMM_to_XMM(xmmPQ, xmmPQ, 0); // wzyx = PPPP
-	//SSE_MOVSS_XMM_to_M32((uptr)&mVU->regs->VI[REG_P].UL, xmmPQ);
 
 	// Restore cpu state
 	POP32R(EDI);
diff --git a/pcsx2/x86/microVU_Log.inl b/pcsx2/x86/microVU_Log.inl
index c04ea798a2..4aaf139880 100644
--- a/pcsx2/x86/microVU_Log.inl
+++ b/pcsx2/x86/microVU_Log.inl
@@ -47,6 +47,7 @@ microVUx(void) __mVULog(const char* fmt, ...) {
 microVUt(void) __mVUdumpProgram(int progIndex) {
 	microVU* mVU = mVUx;
 	bool bitX[7];
+	//mVU->prog.cur = progIndex; // Needed in order to set iPC
 	mVUlog("*********************\n",   progIndex);
 	mVUlog("* Micro-Program #%02d *\n", progIndex);
 	mVUlog("*********************\n\n", progIndex);
@@ -68,7 +69,8 @@ microVUt(void) __mVUdumpProgram(int progIndex) {
 		if (mVU->code & _Mbit_) {bitX[2] = 1; bitX[5] = 1;}
 		if (mVU->code & _Dbit_) {bitX[3] = 1; bitX[5] = 1;}
 		if (mVU->code & _Tbit_) {bitX[4] = 1; bitX[5] = 1;}
-		
+
+		iPC = (i+1)/4;
 		mVUopU<vuIndex, 2>();
 
 		if (bitX[5]) { 
@@ -81,6 +83,7 @@ microVUt(void) __mVUdumpProgram(int progIndex) {
 			mVUlog(")");
 		}
 
+		iPC = i/4;
 		mVU->code = mVU->prog.prog[progIndex].data[i];
 		mVUlog("\n[%04x] (%08x) ", i*4, mVU->code);
 		mVUopL<vuIndex, 2>();
diff --git a/pcsx2/x86/microVU_Lower.inl b/pcsx2/x86/microVU_Lower.inl
index 0ae4c5011b..2522ef83a0 100644
--- a/pcsx2/x86/microVU_Lower.inl
+++ b/pcsx2/x86/microVU_Lower.inl
@@ -431,7 +431,6 @@ microVUf(void) mVU_ESUM() {
 
 microVUf(void) mVU_FCAND() {
 	microVU* mVU = mVUx;
-	pass1 { mVUprint("clip broken"); }
 	pass2 { 
 		mVUallocCFLAGa<vuIndex>(gprT1, fvcInstance);
 		AND32ItoR(gprT1, _Imm24_);
@@ -444,7 +443,6 @@ microVUf(void) mVU_FCAND() {
 
 microVUf(void) mVU_FCEQ() {
 	microVU* mVU = mVUx;
-	pass1 { mVUprint("clip broken"); }
 	pass2 { 
 		mVUallocCFLAGa<vuIndex>(gprT1, fvcInstance);
 		XOR32ItoR(gprT1, _Imm24_);
@@ -457,7 +455,6 @@ microVUf(void) mVU_FCEQ() {
 
 microVUf(void) mVU_FCGET() {
 	microVU* mVU = mVUx;
-	pass1 { mVUprint("clip broken"); }
 	pass2 { 
 		mVUallocCFLAGa<vuIndex>(gprT1, fvcInstance);
 		AND32ItoR(gprT1, 0xfff);
@@ -468,7 +465,6 @@ microVUf(void) mVU_FCGET() {
 
 microVUf(void) mVU_FCOR() {
 	microVU* mVU = mVUx;
-	pass1 { mVUprint("clip broken"); }
 	pass2 { 
 		mVUallocCFLAGa<vuIndex>(gprT1, fvcInstance);
 		OR32ItoR(gprT1, _Imm24_);
@@ -481,7 +477,7 @@ microVUf(void) mVU_FCOR() {
 
 microVUf(void) mVU_FCSET() {
 	microVU* mVU = mVUx;
-	pass1 { mVUprint("clip broken"); }
+	pass1 { mVUinfo |= doClip; }
 	pass2 { 
 		MOV32ItoR(gprT1, _Imm24_);
 		mVUallocCFLAGb<vuIndex>(gprT1, fcInstance);
@@ -660,6 +656,7 @@ microVUf(void) mVU_ISUB() {
 			mVUallocVIa<vuIndex>(gprT1, _Fs_);
 			mVUallocVIa<vuIndex>(gprT2, _Ft_);
 			SUB16RtoR(gprT1, gprT2);
+			mVUallocVIb<vuIndex>(gprT1, _Fd_);
 		}
 		else if (!isMMX(_Fd_)) { 
 			XOR32RtoR(gprT1, gprT1);
@@ -856,7 +853,7 @@ microVUf(void) mVU_LQ() {
 			mVUsaveReg<vuIndex>(xmmFt, (uptr)&mVU->regs->VF[_Ft_].UL[0], _X_Y_Z_W, 1);
 		}
 	}
-	pass3 { mVUlog("LQ"); }
+	pass3 { mVUlog("LQ.%s vf%02d, vi%02d + %d", _XYZW_String, _Ft_, _Fs_, _Imm11_); }
 }
 
 microVUf(void) mVU_LQD() {
@@ -878,7 +875,7 @@ microVUf(void) mVU_LQD() {
 			}
 		}
 	}
-	pass3 { mVUlog("LQD"); }
+	pass3 { mVUlog("LQD.%s vf%02d, --vi%02d", _XYZW_String, _Ft_, _Fs_); }
 }
 
 microVUf(void) mVU_LQI() {
@@ -901,7 +898,7 @@ microVUf(void) mVU_LQI() {
 			mVUallocVIb<vuIndex>(gprT2, _Fs_);
 		}
 	}
-	pass3 { mVUlog("LQI"); }
+	pass3 { mVUlog("LQI.%s vf%02d, vi%02d++", _XYZW_String, _Ft_, _Fs_); }
 }
 
 //------------------------------------------------------------------
@@ -924,7 +921,7 @@ microVUf(void) mVU_SQ() {
 			mVUsaveReg2<vuIndex>(xmmFs, gprT1, (uptr)mVU->regs->Mem, _X_Y_Z_W);
 		}
 	}
-	pass3 { mVUlog("SQ"); }
+	pass3 { mVUlog("SQ.%s vf%02d, vi%02d + %d", _XYZW_String, _Fs_, _Ft_, _Imm11_); }
 }
 
 microVUf(void) mVU_SQD() {
@@ -944,7 +941,7 @@ microVUf(void) mVU_SQD() {
 			mVUsaveReg2<vuIndex>(xmmFs, gprT1, (uptr)mVU->regs->Mem, _X_Y_Z_W);
 		}
 	}
-	pass3 { mVUlog("SQD"); }
+	pass3 { mVUlog("SQD.%s vf%02d, --vi%02d", _XYZW_String, _Fs_, _Ft_); }
 }
 
 microVUf(void) mVU_SQI() {
@@ -962,10 +959,10 @@ microVUf(void) mVU_SQI() {
 			getReg7(xmmFs, _Fs_);
 			mVUsaveReg2<vuIndex>(xmmFs, gprT1, (uptr)mVU->regs->Mem, _X_Y_Z_W);
 			ADD16ItoR(gprT2, 1);
-			mVUallocVIb<vuIndex>(gprT2, _Ft_); // ToDo: Backup to memory check.
+			mVUallocVIb<vuIndex>(gprT2, _Ft_);
 		}
 	}
-	pass3 { mVUlog("SQI"); }
+	pass3 { mVUlog("SQI.%s vf%02d, vi%02d++", _XYZW_String, _Fs_, _Ft_); }
 }
 
 //------------------------------------------------------------------
@@ -983,7 +980,7 @@ microVUf(void) mVU_RINIT() {
 		}
 		else MOV32ItoR(gprR, 0x3f800000);
 	}
-	pass3 { mVUlog("RINIT"); }
+	pass3 { mVUlog("RINIT R, vf%02d%s", _Fs_, _Fsf_String); }
 }
 
 microVUt(void) mVU_RGET_() {
@@ -1000,7 +997,7 @@ microVUf(void) mVU_RGET() {
 	microVU* mVU = mVUx;
 	pass1 { mVUanalyzeR2<vuIndex>(_Ft_, 1); }
 	pass2 { mVU_RGET_<vuIndex>(); }
-	pass3 { mVUlog("RGET"); }
+	pass3 { mVUlog("RGET.%s vf%02d, R", _XYZW_String, _Ft_); }
 }
 
 microVUf(void) mVU_RNEXT() {
@@ -1023,7 +1020,7 @@ microVUf(void) mVU_RNEXT() {
 		OR32ItoR (gprR, 0x3f800000);
 		mVU_RGET_<vuIndex>(); 
 	}
-	pass3 { mVUlog("RNEXT"); }
+	pass3 { mVUlog("RNEXT.%s vf%02d, R", _XYZW_String, _Ft_); }
 }
 
 microVUf(void) mVU_RXOR() {
@@ -1036,7 +1033,7 @@ microVUf(void) mVU_RXOR() {
 			XOR32RtoR(gprR,  gprT1);
 		}
 	}
-	pass3 { mVUlog("RXOR"); }
+	pass3 { mVUlog("RXOR R, vf%02d%s", _Fs_, _Fsf_String); }
 }
 
 //------------------------------------------------------------------
@@ -1066,7 +1063,7 @@ microVUf(void) mVU_XTOP() {
 		MOVZX32M16toR(gprT1, (uptr)&mVU->regs->vifRegs->top);
 		mVUallocVIb<vuIndex>(gprT1, _Ft_);
 	}
-	pass3 { mVUlog("XTOP"); }
+	pass3 { mVUlog("XTOP vi%02d", _Ft_); }
 }
 
 microVUf(void) mVU_XITOP() {
@@ -1076,7 +1073,7 @@ microVUf(void) mVU_XITOP() {
 		MOVZX32M16toR(gprT1, (uptr)&mVU->regs->vifRegs->itop);
 		mVUallocVIb<vuIndex>(gprT1, _Ft_);
 	}
-	pass3 { mVUlog("XITOP"); }
+	pass3 { mVUlog("XITOP vi%02d", _Ft_); }
 }
 
 //------------------------------------------------------------------
@@ -1101,7 +1098,7 @@ microVUf(void) mVU_XGKICK() {
 		CALLFunc((uptr)mVU_XGKICK_);
 		POP32R(gprR); // Restore
 	}
-	pass3 { mVUlog("XGKICK"); }
+	pass3 { mVUlog("XGKICK vi%02d", _Fs_); }
 }
 
 //------------------------------------------------------------------
@@ -1111,7 +1108,7 @@ microVUf(void) mVU_XGKICK() {
 microVUf(void) mVU_B() {
 	microVU* mVU = mVUx;
 	mVUbranch = 1;
-	pass3 { mVUlog("B"); }
+	pass3 { mVUlog("B [%04x]", branchAddr); }
 }
 microVUf(void) mVU_BAL() {
 	microVU* mVU = mVUx;
@@ -1120,11 +1117,8 @@ microVUf(void) mVU_BAL() {
 	pass2 {
 		MOV32ItoR(gprT1, bSaveAddr);
 		mVUallocVIb<vuIndex>(gprT1, _Ft_);
-		// Note: Not sure if the lower instruction in the branch-delay slot
-		// should read the previous VI-value or the VI-value resulting from this branch.
-		// This code does the latter...
 	}
-	pass3 { mVUlog("BAL"); }
+	pass3 { mVUlog("BAL vi%02d [%04x]", _Ft_, branchAddr); }
 }
 microVUf(void) mVU_IBEQ() {
 	microVU* mVU = mVUx;
@@ -1137,7 +1131,7 @@ microVUf(void) mVU_IBEQ() {
 		else { mVUallocVIa<vuIndex>(gprT2, _Ft_); XOR32RtoR(gprT1, gprT2); }
 		MOV32RtoM((uptr)&mVU->branch, gprT1);
 	}
-	pass3 { mVUlog("IBEQ"); }
+	pass3 { mVUlog("IBEQ vi%02d, vi%02d [%04x]", _Ft_, _Fs_, branchAddr); }
 }
 microVUf(void) mVU_IBGEZ() {
 	microVU* mVU = mVUx;
@@ -1148,7 +1142,7 @@ microVUf(void) mVU_IBGEZ() {
 		else mVUallocVIa<vuIndex>(gprT1, _Fs_);
 		MOV32RtoM((uptr)&mVU->branch, gprT1);
 	}
-	pass3 { mVUlog("IBGEZ"); }
+	pass3 { mVUlog("IBGEZ vi%02d [%04x]", _Fs_, branchAddr); }
 }
 microVUf(void) mVU_IBGTZ() {
 	microVU* mVU = mVUx;
@@ -1159,7 +1153,7 @@ microVUf(void) mVU_IBGTZ() {
 		else mVUallocVIa<vuIndex>(gprT1, _Fs_);
 		MOV32RtoM((uptr)&mVU->branch, gprT1);
 	}
-	pass3 { mVUlog("IBGTZ"); }
+	pass3 { mVUlog("IBGTZ vi%02d [%04x]", _Fs_, branchAddr); }
 }
 microVUf(void) mVU_IBLEZ() {
 	microVU* mVU = mVUx;
@@ -1170,7 +1164,7 @@ microVUf(void) mVU_IBLEZ() {
 		else mVUallocVIa<vuIndex>(gprT1, _Fs_);
 		MOV32RtoM((uptr)&mVU->branch, gprT1);
 	}
-	pass3 { mVUlog("IBLEZ"); }
+	pass3 { mVUlog("IBLEZ vi%02d [%04x]", _Fs_, branchAddr); }
 }
 microVUf(void) mVU_IBLTZ() {
 	microVU* mVU = mVUx;
@@ -1181,7 +1175,7 @@ microVUf(void) mVU_IBLTZ() {
 		else mVUallocVIa<vuIndex>(gprT1, _Fs_);
 		MOV32RtoM((uptr)&mVU->branch, gprT1);
 	}
-	pass3 { mVUlog("IBLTZ"); }
+	pass3 { mVUlog("IBLTZ vi%02d [%04x]", _Fs_, branchAddr); }
 }
 microVUf(void) mVU_IBNE() {
 	microVU* mVU = mVUx;
@@ -1194,7 +1188,7 @@ microVUf(void) mVU_IBNE() {
 		else { mVUallocVIa<vuIndex>(gprT2, _Ft_); XOR32RtoR(gprT1, gprT2); }
 		MOV32RtoM((uptr)&mVU->branch, gprT1);
 	}
-	pass3 { mVUlog("IBNE"); }
+	pass3 { mVUlog("IBNE vi%02d, vi%02d [%04x]", _Ft_, _Fs_, branchAddr); }
 }
 microVUf(void) mVU_JR() {
 	microVU* mVU = mVUx;
@@ -1205,7 +1199,7 @@ microVUf(void) mVU_JR() {
 		else mVUallocVIa<vuIndex>(gprT1, _Fs_);
 		MOV32RtoM((uptr)&mVU->branch, gprT1);
 	}
-	pass3 { mVUlog("JR"); }
+	pass3 { mVUlog("JR [vi%02d]", _Fs_); }
 }
 microVUf(void) mVU_JALR() {
 	microVU* mVU = mVUx;
@@ -1217,11 +1211,8 @@ microVUf(void) mVU_JALR() {
 		MOV32RtoM((uptr)&mVU->branch, gprT1);
 		MOV32ItoR(gprT1, bSaveAddr);
 		mVUallocVIb<vuIndex>(gprT1, _Ft_);
-		// Note: Not sure if the lower instruction in the branch-delay slot
-		// should read the previous VI-value or the VI-value resulting from this branch.
-		// This code does the latter...
 	}
-	pass3 { mVUlog("JALR"); }
+	pass3 { mVUlog("JALR vi%02d, [vi%02d]", _Ft_, _Fs_); }
 }
 
 #endif //PCSX2_MICROVU
diff --git a/pcsx2/x86/microVU_Misc.h b/pcsx2/x86/microVU_Misc.h
index 5046494b53..fb2eb21fec 100644
--- a/pcsx2/x86/microVU_Misc.h
+++ b/pcsx2/x86/microVU_Misc.h
@@ -89,8 +89,8 @@ declareAllVariables
 #define _Ftf_	((mVU->code >> 23) & 0x03)
 
 #define _Imm5_	(((mVU->code & 0x400) ? 0xfff0 : 0) | ((mVU->code >> 6) & 0xf))
-#define _Imm11_	(s32)(mVU->code & 0x400 ? 0xfffffc00 | (mVU->code & 0x3ff) : mVU->code & 0x3ff)
-#define _Imm12_	(((mVU->code >> 21 ) & 0x1) << 11) | (mVU->code & 0x7ff)
+#define _Imm11_	(s32)((mVU->code & 0x400) ? (0xfffffc00 | (mVU->code & 0x3ff)) : mVU->code & 0x3ff)
+#define _Imm12_	(((mVU->code >> 21) & 0x1) << 11) | (mVU->code & 0x7ff)
 #define _Imm15_	(((mVU->code >> 10) & 0x7800) | (mVU->code & 0x7ff))
 #define _Imm24_	(u32)(mVU->code & 0xffffff)
 
@@ -162,8 +162,12 @@ declareAllVariables
 #define incPC2(x)	 { iPC = ((iPC + x) & (mVU->progSize-1)); }
 #define incCycles(x) { mVUincCycles<vuIndex>(x); }
 #define bSaveAddr	 ((xPC + (2 * 8)) & ((vuIndex) ? 0x3ff8:0xff8))
-#define branchAddr	 ((xPC + (_Imm11_ * 8)) & ((vuIndex) ? 0x3ff8:0xff8))
+#define branchAddr	 ((xPC + 8 + (_Imm11_ * 8)) & ((vuIndex) ? 0x3ff8:0xff8))
 #define shufflePQ	 (((mVU->q) ? 0xb0 : 0xe0) | ((mVU->q) ? 0x01 : 0x04))
+#define _Fsf_String	 ((_Fsf_ == 3) ? "w" : ((_Fsf_ == 2) ? "z" : ((_Fsf_ == 1) ? "y" : "x")))
+#define _Ftf_String	 ((_Ftf_ == 3) ? "w" : ((_Ftf_ == 2) ? "z" : ((_Ftf_ == 1) ? "y" : "x")))
+#define xyzwStr(x,s) (_X_Y_Z_W == x) ? s :
+#define _XYZW_String (xyzwStr(1, "w") (xyzwStr(2, "z") (xyzwStr(3, "zw") (xyzwStr(4, "y") (xyzwStr(5, "yw") (xyzwStr(6, "yz") (xyzwStr(7, "yzw") (xyzwStr(8, "x") (xyzwStr(9, "xw") (xyzwStr(10, "xz") (xyzwStr(11, "xzw") (xyzwStr(12, "xy") (xyzwStr(13, "xyw") (xyzwStr(14, "xyz") "xyzw"))))))))))))))
 
 
 #define _isNOP		 (1<<0) // Skip Lower Instruction
diff --git a/pcsx2/x86/microVU_Tables.inl b/pcsx2/x86/microVU_Tables.inl
index 41b8b9a1c7..26dc6ea8cd 100644
--- a/pcsx2/x86/microVU_Tables.inl
+++ b/pcsx2/x86/microVU_Tables.inl
@@ -1077,8 +1077,7 @@ microVUf(void) mVULowerOP_T3_11()	{ doTableStuff(mVULowerOP_T3_11_OPCODE,	((mVUg
 microVUf(void) mVUopU() { doTableStuff(mVU_UPPER_OPCODE, (mVUgetCode & 0x3f)); } // Gets Upper Opcode
 microVUf(void) mVUopL() { doTableStuff(mVULOWER_OPCODE,  (mVUgetCode >>  25)); } // Gets Lower Opcode
 microVUf(void) mVUunknown() { 
-	SysPrintf("mVUunknown<%d,%d> : Unknown Micro VU opcode called (%x)\n", vuIndex, recPass, mVUgetCode);
-	//pass2 { write8(0xcc); }
+	pass2 { SysPrintf("microVU%d: Unknown Micro VU opcode called (%x)\n", vuIndex, mVUgetCode); }
 	pass3 { mVUlog("Unknown", mVUgetCode); }
 }
 
diff --git a/pcsx2/x86/microVU_Upper.inl b/pcsx2/x86/microVU_Upper.inl
index 51a2a325d6..2d45895a63 100644
--- a/pcsx2/x86/microVU_Upper.inl
+++ b/pcsx2/x86/microVU_Upper.inl
@@ -603,7 +603,7 @@ microVUf(void) mVU_ITOF12()	 { mVU_ITOFx<vuIndex, recPass>((uptr)mVU_ITOF_12);	p
 microVUf(void) mVU_ITOF15()	 { mVU_ITOFx<vuIndex, recPass>((uptr)mVU_ITOF_15);	pass3 { mVUlog("ITOF15"); } }
 microVUf(void) mVU_CLIP() {
 	microVU* mVU = mVUx;
-	pass1 { mVUanalyzeFMAC4<vuIndex>(_Fs_, _Ft_); mVUprint("clip broken"); }
+	pass1 { mVUanalyzeFMAC4<vuIndex>(_Fs_, _Ft_); }
 	pass2 {
 		int Fs, Ft;
 		mVUallocFMAC17a<vuIndex>(Fs, Ft);