mirror of https://github.com/PCSX2/pcsx2.git
more lower instructions implemented
git-svn-id: http://pcsx2.googlecode.com/svn/trunk@725 96395faa-99c1-11dd-bbfe-3dabce05a288
This commit is contained in:
cottonvibes
parent
80f3dc5840
commit
a5d95b75c5
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@ -702,7 +702,7 @@ microVUt(void) mVUallocFMAC21b(int& ACCw, int& ACCr) {
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//------------------------------------------------------------------
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#define getQreg(reg) { \
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mVUunpack_xyzw<vuIndex>(reg, xmmPQ, writeQ); \
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mVUunpack_xyzw<vuIndex>(reg, xmmPQ, readQ); \
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/*if (CHECK_VU_EXTRA_OVERFLOW) mVUclamp2<vuIndex>(reg, xmmT1, 15);*/ \
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}
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@ -905,4 +905,13 @@ microVUt(void) mVUallocVIb(int GPRreg, int _reg_) {
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/*if (CHECK_VU_EXTRA_OVERFLOW) mVUclamp2<vuIndex>(reg, xmmT1, 15);*/ \
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}
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//------------------------------------------------------------------
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// Div/Sqrt/Rsqrt Allocator Helpers
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//------------------------------------------------------------------
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#define getReg5(reg, _reg_, _fxf_) { \
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mVUloadReg<vuIndex>(reg, (uptr)&mVU->regs->VF[_reg_].UL[0], (1 << (3 - _fxf_))); \
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if (CHECK_VU_EXTRA_OVERFLOW) mVUclamp2<vuIndex>(reg, xmmT1, (1 << (3 - _fxf_))); \
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}
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#endif //PCSX2_MICROVU
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@ -23,29 +23,136 @@
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// Micro VU Micromode Lower instructions
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//------------------------------------------------------------------
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microVUf(void) mVU_DIV(){}
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microVUf(void) mVU_SQRT(){}
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microVUf(void) mVU_RSQRT(){}
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microVUf(void) mVU_DIV() {
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microVU* mVU = mVUx;
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if (recPass == 0) {}
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else {
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//u8 *pjmp;, *pjmp1;
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u32 *ajmp32, *bjmp32;
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microVUf(void) mVU_EATAN(){}
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microVUf(void) mVU_EATANxy(){}
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microVUf(void) mVU_EATANxz(){}
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microVUf(void) mVU_EEXP(){}
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microVUf(void) mVU_ELENG(){}
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microVUf(void) mVU_ERCPR(){}
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microVUf(void) mVU_ERLENG(){}
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microVUf(void) mVU_ERSADD(){}
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microVUf(void) mVU_ERSQRT(){}
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microVUf(void) mVU_ESADD(){}
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microVUf(void) mVU_ESIN(){}
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microVUf(void) mVU_ESQRT(){}
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microVUf(void) mVU_ESUM(){}
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getReg5(xmmFs, _Fs_, _Fsf_);
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getReg5(xmmFt, _Ft_, _Ftf_);
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microVUf(void) mVU_FCAND(){}
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microVUf(void) mVU_FCEQ(){}
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microVUf(void) mVU_FCOR(){}
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microVUf(void) mVU_FCSET(){}
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microVUf(void) mVU_FCGET(){}
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//AND32ItoM(VU_VI_ADDR(REG_STATUS_FLAG, 2), 0xFCF); // Clear D/I flags
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// FT can be zero here! so we need to check if its zero and set the correct flag.
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SSE_XORPS_XMM_to_XMM(xmmT1, xmmT1); // Clear xmmT1
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SSE_CMPEQPS_XMM_to_XMM(xmmT1, xmmFt); // Set all F's if each vector is zero
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SSE_MOVMSKPS_XMM_to_R32(gprT1, xmmT1); // Move the sign bits of the previous calculation
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AND32ItoR(gprT1, 1); // Grab "Is Zero" bits from the previous calculation
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ajmp32 = JZ32(0); // Skip if none are
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//SSE_XORPS_XMM_to_XMM(xmmT1, xmmT1); // Clear xmmT1
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//SSE_CMPEQPS_XMM_to_XMM(xmmT1, xmmFs); // Set all F's if each vector is zero
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//SSE_MOVMSKPS_XMM_to_R32(gprT1, xmmT1); // Move the sign bits of the previous calculation
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//AND32ItoR(gprT1, 1); // Grab "Is Zero" bits from the previous calculation
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//pjmp = JZ8(0);
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// OR32ItoM( VU_VI_ADDR(REG_STATUS_FLAG, 2), 0x410 ); // Set invalid flag (0/0)
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// pjmp1 = JMP8(0);
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//x86SetJ8(pjmp);
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// OR32ItoM( VU_VI_ADDR(REG_STATUS_FLAG, 2), 0x820 ); // Zero divide (only when not 0/0)
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//x86SetJ8(pjmp1);
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SSE_XORPS_XMM_to_XMM(xmmFs, xmmFt);
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SSE_ANDPS_M128_to_XMM(xmmFs, (uptr)mVU_signbit);
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SSE_ORPS_M128_to_XMM(xmmFs, (uptr)mVU_maxvals); // If division by zero, then xmmFs = +/- fmax
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bjmp32 = JMP32(0);
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x86SetJ32(ajmp32);
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SSE_DIVSS_XMM_to_XMM(xmmFs, xmmFt);
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mVUclamp1<vuIndex>(xmmFs, xmmFt, 8);
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x86SetJ32(bjmp32);
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mVUunpack_xyzw<vuIndex>(xmmFs, xmmFs, 0);
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mVUmergeRegs<vuIndex>(xmmPQ, xmmFs, writeQ ? 4 : 8);
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}
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}
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microVUf(void) mVU_SQRT() {
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microVU* mVU = mVUx;
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if (recPass == 0) {}
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else {
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//u8* pjmp;
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getReg5(xmmFt, _Ft_, _Ftf_);
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//AND32ItoM(VU_VI_ADDR(REG_STATUS_FLAG, 2), 0xFCF); // Clear D/I flags
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/* Check for negative sqrt */
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//SSE_MOVMSKPS_XMM_to_R32(gprT1, xmmFt);
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//AND32ItoR(gprT1, 1); //Check sign
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//pjmp = JZ8(0); //Skip if none are
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// OR32ItoM(VU_VI_ADDR(REG_STATUS_FLAG, 2), 0x410); // Invalid Flag - Negative number sqrt
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//x86SetJ8(pjmp);
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SSE_ANDPS_M128_to_XMM(xmmFt, (uptr)mVU_absclip); // Do a cardinal sqrt
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if (CHECK_VU_OVERFLOW) SSE_MINSS_M32_to_XMM(xmmFt, (uptr)mVU_maxvals); // Clamp infinities (only need to do positive clamp since xmmFt is positive)
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SSE_SQRTSS_XMM_to_XMM(xmmFt, xmmFt);
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mVUunpack_xyzw<vuIndex>(xmmFt, xmmFt, 0);
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mVUmergeRegs<vuIndex>(xmmPQ, xmmFt, writeQ ? 4 : 8);
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}
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}
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microVUf(void) mVU_RSQRT() {
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microVU* mVU = mVUx;
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if (recPass == 0) {}
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else {
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u8 *ajmp8, *bjmp8;
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getReg5(xmmFs, _Fs_, _Fsf_);
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getReg5(xmmFt, _Ft_, _Ftf_);
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//AND32ItoM(VU_VI_ADDR(REG_STATUS_FLAG, 2), 0xFCF); // Clear D/I flags
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/* Check for negative divide */
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//SSE_MOVMSKPS_XMM_to_R32(gprT1, xmmT1);
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//AND32ItoR(gprT1, 1); //Check sign
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//ajmp8 = JZ8(0); //Skip if none are
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// OR32ItoM(VU_VI_ADDR(REG_STATUS_FLAG, 2), 0x410); // Invalid Flag - Negative number sqrt
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//x86SetJ8(ajmp8);
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SSE_ANDPS_M128_to_XMM(xmmFt, (uptr)mVU_absclip); // Do a cardinal sqrt
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SSE_SQRTSS_XMM_to_XMM(xmmFt, xmmFt);
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// Ft can still be zero here! so we need to check if its zero and set the correct flag.
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SSE_XORPS_XMM_to_XMM(xmmT1, xmmT1); // Clear t1reg
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SSE_CMPEQSS_XMM_to_XMM(xmmT1, xmmFt); // Set all F's if each vector is zero
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SSE_MOVMSKPS_XMM_to_R32(gprT1, xmmT1); // Move the sign bits of the previous calculation
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AND32ItoR(gprT1, 1); // Grab "Is Zero" bits from the previous calculation
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ajmp8 = JZ8(0); // Skip if none are
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//OR32ItoM(VU_VI_ADDR(REG_STATUS_FLAG, 2), 0x820); // Zero divide flag
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SSE_ANDPS_M128_to_XMM(xmmFs, (uptr)mVU_signbit);
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SSE_ORPS_M128_to_XMM(xmmFs, (uptr)mVU_maxvals); // EEREC_TEMP = +/-Max
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bjmp8 = JMP8(0);
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x86SetJ8(ajmp8);
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SSE_DIVSS_XMM_to_XMM(xmmFs, xmmFt);
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mVUclamp1<vuIndex>(xmmFs, xmmFt, 8);
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x86SetJ8(bjmp8);
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mVUunpack_xyzw<vuIndex>(xmmFs, xmmFs, 0);
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mVUmergeRegs<vuIndex>(xmmPQ, xmmFs, writeQ ? 4 : 8);
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}
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}
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microVUf(void) mVU_EATAN() {}
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microVUf(void) mVU_EATANxy() {}
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microVUf(void) mVU_EATANxz() {}
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microVUf(void) mVU_EEXP() {}
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microVUf(void) mVU_ELENG() {}
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microVUf(void) mVU_ERCPR() {}
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microVUf(void) mVU_ERLENG() {}
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microVUf(void) mVU_ERSADD() {}
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microVUf(void) mVU_ERSQRT() {}
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microVUf(void) mVU_ESADD() {}
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microVUf(void) mVU_ESIN() {}
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microVUf(void) mVU_ESQRT() {}
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microVUf(void) mVU_ESUM() {}
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microVUf(void) mVU_FCAND() {}
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microVUf(void) mVU_FCEQ() {}
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microVUf(void) mVU_FCOR() {}
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microVUf(void) mVU_FCSET() {}
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microVUf(void) mVU_FCGET() {}
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microVUf(void) mVU_FMAND() {
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microVU* mVU = mVUx;
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@ -119,29 +226,89 @@ microVUf(void) mVU_FSSET() {
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}
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}
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microVUf(void) mVU_IADD(){}
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microVUf(void) mVU_IADDI(){}
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microVUf(void) mVU_IADDIU(){}
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microVUf(void) mVU_IAND(){}
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microVUf(void) mVU_IOR(){}
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microVUf(void) mVU_ISUB(){}
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microVUf(void) mVU_ISUBIU(){}
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microVUf(void) mVU_IADD() {
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microVU* mVU = mVUx;
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if (recPass == 0) {}
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else {
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mVUallocVIa<vuIndex>(gprT1, _Fs_);
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mVUallocVIa<vuIndex>(gprT2, _Ft_);
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ADD16RtoR(gprT1, gprT2);
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mVUallocVIb<vuIndex>(gprT1, _Fd_);
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}
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}
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microVUf(void) mVU_IADDI() {
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microVU* mVU = mVUx;
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if (recPass == 0) {}
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else {
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mVUallocVIa<vuIndex>(gprT1, _Fs_);
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ADD16ItoR(gprT1, _Imm5_);
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mVUallocVIb<vuIndex>(gprT1, _Ft_);
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}
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}
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microVUf(void) mVU_IADDIU() {
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microVU* mVU = mVUx;
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if (recPass == 0) {}
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else {
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mVUallocVIa<vuIndex>(gprT1, _Fs_);
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ADD16ItoR(gprT1, _Imm12_);
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mVUallocVIb<vuIndex>(gprT1, _Ft_);
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}
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}
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microVUf(void) mVU_IAND() {
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microVU* mVU = mVUx;
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if (recPass == 0) {}
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else {
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mVUallocVIa<vuIndex>(gprT1, _Fs_);
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mVUallocVIa<vuIndex>(gprT2, _Ft_);
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AND32RtoR(gprT1, gprT2);
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mVUallocVIb<vuIndex>(gprT1, _Fd_);
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}
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}
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microVUf(void) mVU_IOR() {
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microVU* mVU = mVUx;
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if (recPass == 0) {}
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else {
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mVUallocVIa<vuIndex>(gprT1, _Fs_);
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mVUallocVIa<vuIndex>(gprT2, _Ft_);
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OR32RtoR(gprT1, gprT2);
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mVUallocVIb<vuIndex>(gprT1, _Fd_);
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}
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}
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microVUf(void) mVU_ISUB() {
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microVU* mVU = mVUx;
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if (recPass == 0) {}
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else {
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mVUallocVIa<vuIndex>(gprT1, _Fs_);
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mVUallocVIa<vuIndex>(gprT2, _Ft_);
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SUB16RtoR(gprT1, gprT2);
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mVUallocVIb<vuIndex>(gprT1, _Fd_);
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}
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}
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microVUf(void) mVU_ISUBIU() {
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microVU* mVU = mVUx;
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if (recPass == 0) {}
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else {
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mVUallocVIa<vuIndex>(gprT1, _Fs_);
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SUB16ItoR(gprT1, _Imm12_);
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mVUallocVIb<vuIndex>(gprT1, _Ft_);
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}
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}
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microVUf(void) mVU_B(){}
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microVUf(void) mVU_BAL(){}
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microVUf(void) mVU_IBEQ(){}
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microVUf(void) mVU_IBGEZ(){}
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microVUf(void) mVU_IBGTZ(){}
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microVUf(void) mVU_IBLTZ(){}
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microVUf(void) mVU_IBLEZ(){}
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microVUf(void) mVU_IBNE(){}
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microVUf(void) mVU_JR(){}
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microVUf(void) mVU_JALR(){}
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microVUf(void) mVU_B() {}
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microVUf(void) mVU_BAL() {}
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microVUf(void) mVU_IBEQ() {}
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microVUf(void) mVU_IBGEZ() {}
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microVUf(void) mVU_IBGTZ() {}
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microVUf(void) mVU_IBLTZ() {}
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microVUf(void) mVU_IBLEZ() {}
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microVUf(void) mVU_IBNE() {}
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microVUf(void) mVU_JR() {}
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microVUf(void) mVU_JALR() {}
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microVUf(void) mVU_ILW(){}
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microVUf(void) mVU_ISW(){}
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microVUf(void) mVU_ILWR(){}
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microVUf(void) mVU_ISWR(){}
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microVUf(void) mVU_ILW() {}
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microVUf(void) mVU_ISW() {}
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microVUf(void) mVU_ILWR() {}
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microVUf(void) mVU_ISWR() {}
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microVUf(void) mVU_MOVE() {
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microVU* mVU = mVUx;
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@ -156,8 +323,7 @@ microVUf(void) mVU_MFIR() {
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if (recPass == 0) {}
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else {
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mVUallocVIa<vuIndex>(gprT1, _Fs_);
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SHL32ItoR(gprT1, 16);
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SAR32ItoR(gprT1, 16);
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MOVSX32R16toR(gprT1, gprT1);
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SSE2_MOVD_R_to_XMM(xmmT1, gprT1);
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if (!_XYZW_SS) { mVUunpack_xyzw<vuIndex>(xmmT1, xmmT1, 0); }
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mVUsaveReg<vuIndex>(xmmT1, (uptr)&mVU->regs->VF[_Ft_].UL[0], _X_Y_Z_W);
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@ -189,23 +355,23 @@ microVUf(void) mVU_MR32() {
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}
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}
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microVUf(void) mVU_LQ(){}
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microVUf(void) mVU_LQD(){}
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microVUf(void) mVU_LQI(){}
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microVUf(void) mVU_SQ(){}
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microVUf(void) mVU_SQD(){}
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microVUf(void) mVU_SQI(){}
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//microVUf(void) mVU_LOI(){}
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microVUf(void) mVU_LQ() {}
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microVUf(void) mVU_LQD() {}
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microVUf(void) mVU_LQI() {}
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microVUf(void) mVU_SQ() {}
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microVUf(void) mVU_SQD() {}
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microVUf(void) mVU_SQI() {}
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//microVUf(void) mVU_LOI() {}
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microVUf(void) mVU_RINIT(){}
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microVUf(void) mVU_RGET(){}
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microVUf(void) mVU_RNEXT(){}
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microVUf(void) mVU_RXOR(){}
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microVUf(void) mVU_RINIT() {}
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microVUf(void) mVU_RGET() {}
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microVUf(void) mVU_RNEXT() {}
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microVUf(void) mVU_RXOR() {}
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microVUf(void) mVU_WAITP(){}
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microVUf(void) mVU_WAITQ(){}
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microVUf(void) mVU_WAITP() {}
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microVUf(void) mVU_WAITQ() {}
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microVUf(void) mVU_XGKICK(){}
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microVUf(void) mVU_XGKICK() {}
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microVUf(void) mVU_XTOP() {
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microVU* mVU = mVUx;
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if (recPass == 0) {}
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@ -61,6 +61,8 @@ PCSX2_ALIGNED16_EXTERN(const float mVU_ITOF_15[4]);
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#define _Imm11_ (s32)(mVU->code & 0x400 ? 0xfffffc00 | (mVU->code & 0x3ff) : mVU->code & 0x3ff)
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#define _UImm11_ (s32)(mVU->code & 0x7ff)
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#define _Imm12_ (((mVU->code >> 21 ) & 0x1) << 11) | (mVU->code & 0x7ff)
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#define _Imm5_ (((mVU->code & 0x400) ? 0xfff0 : 0) | ((mVU->code >> 6) & 0xf))
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#define _Imm15_ (((mVU->code >> 10) & 0x7800) | (mVU->code & 0x7ff))
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#define xmmT1 0 // Temp Reg
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#define xmmFs 1 // Holds the Value of Fs (writes back result Fd)
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