mirror of https://github.com/PCSX2/pcsx2.git
started on the lower instructions
git-svn-id: http://pcsx2.googlecode.com/svn/trunk@724 96395faa-99c1-11dd-bbfe-3dabce05a288
This commit is contained in:
cottonvibes
parent
a44c6f0f83
commit
80f3dc5840
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@ -44,7 +44,7 @@ struct microAllocInfo {
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// bit 4 = (00 = instance #0, 01 = instance #1, 10 = instance #2, 11 = instance #3)
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// bit 5 = Write to Q1 or Q2?
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// bit 6 = Read Q1 or Q2?
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// bit 7 = Write VI(Fd) Result to backup memory?
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// bit 7 = Read/Write to P1 or P2?
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// bit 8 = Update Mac Flags?
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// bit 9 = Update Status Flags?
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// bit 10 = Used with bit 11 to make a 2-bit key for mac flag instance
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@ -861,7 +861,8 @@ microVUt(void) mVUallocSFLAGa(int reg, int fInstance) {
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microVUt(void) mVUallocSFLAGb(int reg, int fInstance) {
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getFlagReg(fInstance, fInstance);
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MOV32RtoR(fInstance, reg);
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AND32ItoR(fInstance, 0xffff0000);
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OR16RtoR(fInstance, reg);
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}
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microVUt(void) mVUallocMFLAGa(int reg, int fInstance) {
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@ -877,4 +878,31 @@ microVUt(void) mVUallocMFLAGb(int reg, int fInstance) {
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OR32RtoR(fInstance, reg);
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}
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//------------------------------------------------------------------
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// VI Reg Allocators
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//------------------------------------------------------------------
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microVUt(void) mVUallocVIa(int GPRreg, int _reg_) {
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microVU* mVU = mVUx;
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if (_reg_ == 0) { XOR32RtoR(GPRreg, GPRreg); }
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else if (_reg_ < 9) { MOVD32MMXtoR(GPRreg, mmxVI1 + (_reg_ - 1)); }
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else { MOVZX32M16toR(GPRreg, (uptr)&mVU->regs->VI[_reg_].UL); }
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}
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microVUt(void) mVUallocVIb(int GPRreg, int _reg_) {
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microVU* mVU = mVUx;
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if (_reg_ == 0) { return; }
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else if (_reg_ < 9) { MOVD32RtoMMX(mmxVI1 + (_reg_ - 1), GPRreg); }
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else { MOV16RtoM((uptr)&mVU->regs->VI[_reg_].UL, GPRreg); }
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}
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//------------------------------------------------------------------
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// P Reg Allocator
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//------------------------------------------------------------------
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#define getPreg(reg) { \
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mVUunpack_xyzw<vuIndex>(reg, xmmPQ, (2 + writeP)); \
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/*if (CHECK_VU_EXTRA_OVERFLOW) mVUclamp2<vuIndex>(reg, xmmT1, 15);*/ \
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}
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#endif //PCSX2_MICROVU
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@ -26,6 +26,99 @@
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microVUf(void) mVU_DIV(){}
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microVUf(void) mVU_SQRT(){}
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microVUf(void) mVU_RSQRT(){}
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microVUf(void) mVU_EATAN(){}
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microVUf(void) mVU_EATANxy(){}
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microVUf(void) mVU_EATANxz(){}
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microVUf(void) mVU_EEXP(){}
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microVUf(void) mVU_ELENG(){}
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microVUf(void) mVU_ERCPR(){}
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microVUf(void) mVU_ERLENG(){}
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microVUf(void) mVU_ERSADD(){}
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microVUf(void) mVU_ERSQRT(){}
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microVUf(void) mVU_ESADD(){}
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microVUf(void) mVU_ESIN(){}
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microVUf(void) mVU_ESQRT(){}
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microVUf(void) mVU_ESUM(){}
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microVUf(void) mVU_FCAND(){}
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microVUf(void) mVU_FCEQ(){}
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microVUf(void) mVU_FCOR(){}
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microVUf(void) mVU_FCSET(){}
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microVUf(void) mVU_FCGET(){}
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microVUf(void) mVU_FMAND() {
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microVU* mVU = mVUx;
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if (recPass == 0) {}
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else {
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mVUallocMFLAGa<vuIndex>(gprT1, fvmInstance);
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mVUallocVIa<vuIndex>(gprT2, _Fs_);
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AND16RtoR(gprT1, gprT2);
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mVUallocVIb<vuIndex>(gprT1, _Ft_);
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}
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}
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microVUf(void) mVU_FMEQ() {
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microVU* mVU = mVUx;
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if (recPass == 0) {}
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else {
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mVUallocMFLAGa<vuIndex>(gprT1, fvmInstance);
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mVUallocVIa<vuIndex>(gprT2, _Fs_);
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CMP16RtoR(gprT1, gprT2);
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SETE8R(gprT1);
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AND16ItoR(gprT1, 0x1);
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mVUallocVIb<vuIndex>(gprT1, _Ft_);
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}
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}
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microVUf(void) mVU_FMOR() {
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microVU* mVU = mVUx;
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if (recPass == 0) {}
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else {
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mVUallocMFLAGa<vuIndex>(gprT1, fvmInstance);
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mVUallocVIa<vuIndex>(gprT2, _Fs_);
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OR16RtoR(gprT1, gprT2);
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mVUallocVIb<vuIndex>(gprT1, _Ft_);
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}
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}
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microVUf(void) mVU_FSAND() {
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microVU* mVU = mVUx;
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if (recPass == 0) {}
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else {
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mVUallocSFLAGa<vuIndex>(gprT1, fvsInstance);
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AND16ItoR(gprT1, _Imm12_);
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mVUallocVIb<vuIndex>(gprT1, _Ft_);
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}
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}
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microVUf(void) mVU_FSEQ() {
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microVU* mVU = mVUx;
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if (recPass == 0) {}
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else {
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mVUallocSFLAGa<vuIndex>(gprT1, fvsInstance);
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CMP16ItoR(gprT1, _Imm12_);
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SETE8R(gprT1);
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AND16ItoR(gprT1, 0x1);
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mVUallocVIb<vuIndex>(gprT1, _Ft_);
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}
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}
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microVUf(void) mVU_FSOR() {
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microVU* mVU = mVUx;
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if (recPass == 0) {}
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else {
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mVUallocSFLAGa<vuIndex>(gprT1, fvsInstance);
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OR16ItoR(gprT1, _Imm12_);
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mVUallocVIb<vuIndex>(gprT1, _Ft_);
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}
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}
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microVUf(void) mVU_FSSET() {
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microVU* mVU = mVUx;
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if (recPass == 0) {}
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else {
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int flagReg;
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getFlagReg(flagReg, fsInstance);
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MOV16ItoR(gprT1, (_Imm12_ & 0xfc0));
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}
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}
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microVUf(void) mVU_IADD(){}
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microVUf(void) mVU_IADDI(){}
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microVUf(void) mVU_IADDIU(){}
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@ -33,64 +126,100 @@ microVUf(void) mVU_IAND(){}
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microVUf(void) mVU_IOR(){}
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microVUf(void) mVU_ISUB(){}
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microVUf(void) mVU_ISUBIU(){}
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microVUf(void) mVU_MOVE(){}
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microVUf(void) mVU_MFIR(){}
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microVUf(void) mVU_MTIR(){}
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microVUf(void) mVU_MR32(){}
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microVUf(void) mVU_LQ(){}
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microVUf(void) mVU_LQD(){}
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microVUf(void) mVU_LQI(){}
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microVUf(void) mVU_SQ(){}
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microVUf(void) mVU_SQD(){}
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microVUf(void) mVU_SQI(){}
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microVUf(void) mVU_ILW(){}
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microVUf(void) mVU_ISW(){}
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microVUf(void) mVU_ILWR(){}
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microVUf(void) mVU_ISWR(){}
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microVUf(void) mVU_LOI(){}
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microVUf(void) mVU_RINIT(){}
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microVUf(void) mVU_RGET(){}
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microVUf(void) mVU_RNEXT(){}
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microVUf(void) mVU_RXOR(){}
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microVUf(void) mVU_WAITQ(){}
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microVUf(void) mVU_FSAND(){}
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microVUf(void) mVU_FSEQ(){}
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microVUf(void) mVU_FSOR(){}
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microVUf(void) mVU_FSSET(){}
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microVUf(void) mVU_FMAND(){}
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microVUf(void) mVU_FMEQ(){}
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microVUf(void) mVU_FMOR(){}
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microVUf(void) mVU_FCAND(){}
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microVUf(void) mVU_FCEQ(){}
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microVUf(void) mVU_FCOR(){}
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microVUf(void) mVU_FCSET(){}
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microVUf(void) mVU_FCGET(){}
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microVUf(void) mVU_B(){}
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microVUf(void) mVU_BAL(){}
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microVUf(void) mVU_IBEQ(){}
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microVUf(void) mVU_IBGEZ(){}
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microVUf(void) mVU_IBGTZ(){}
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microVUf(void) mVU_IBLTZ(){}
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microVUf(void) mVU_IBLEZ(){}
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microVUf(void) mVU_IBNE(){}
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microVUf(void) mVU_B(){}
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microVUf(void) mVU_BAL(){}
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microVUf(void) mVU_JR(){}
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microVUf(void) mVU_JALR(){}
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microVUf(void) mVU_MFP(){}
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microVUf(void) mVU_ILW(){}
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microVUf(void) mVU_ISW(){}
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microVUf(void) mVU_ILWR(){}
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microVUf(void) mVU_ISWR(){}
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microVUf(void) mVU_MOVE() {
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microVU* mVU = mVUx;
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if (recPass == 0) {}
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else {
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mVUloadReg<vuIndex>(xmmT1, (uptr)&mVU->regs->VF[_Fs_].UL[0], _X_Y_Z_W);
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mVUsaveReg<vuIndex>(xmmT1, (uptr)&mVU->regs->VF[_Ft_].UL[0], _X_Y_Z_W);
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}
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}
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microVUf(void) mVU_MFIR() {
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microVU* mVU = mVUx;
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if (recPass == 0) {}
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else {
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mVUallocVIa<vuIndex>(gprT1, _Fs_);
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SHL32ItoR(gprT1, 16);
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SAR32ItoR(gprT1, 16);
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SSE2_MOVD_R_to_XMM(xmmT1, gprT1);
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if (!_XYZW_SS) { mVUunpack_xyzw<vuIndex>(xmmT1, xmmT1, 0); }
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mVUsaveReg<vuIndex>(xmmT1, (uptr)&mVU->regs->VF[_Ft_].UL[0], _X_Y_Z_W);
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}
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}
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microVUf(void) mVU_MFP() {
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microVU* mVU = mVUx;
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if (recPass == 0) {}
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else {
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getPreg(xmmFt);
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mVUsaveReg<vuIndex>(xmmFt, (uptr)&mVU->regs->VF[_Ft_].UL[0], _X_Y_Z_W);
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}
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}
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microVUf(void) mVU_MTIR() {
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microVU* mVU = mVUx;
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if (recPass == 0) {}
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else {
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MOVZX32M16toR(gprT1, (uptr)&mVU->regs->VF[_Fs_].UL[_Fsf_]);
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mVUallocVIb<vuIndex>(gprT1, _Ft_);
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}
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}
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microVUf(void) mVU_MR32() {
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microVU* mVU = mVUx;
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if (recPass == 0) {}
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else {
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mVUloadReg<vuIndex>(xmmT1, (uptr)&mVU->regs->VF[_Fs_].UL[0], (_X_Y_Z_W == 8) ? 4 : 15);
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if (_X_Y_Z_W != 8) { SSE_SHUFPS_XMM_to_XMM(xmmT1, xmmT1, 0x39); }
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mVUsaveReg<vuIndex>(xmmT1, (uptr)&mVU->regs->VF[_Ft_].UL[0], _X_Y_Z_W);
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}
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}
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microVUf(void) mVU_LQ(){}
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microVUf(void) mVU_LQD(){}
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microVUf(void) mVU_LQI(){}
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microVUf(void) mVU_SQ(){}
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microVUf(void) mVU_SQD(){}
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microVUf(void) mVU_SQI(){}
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//microVUf(void) mVU_LOI(){}
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microVUf(void) mVU_RINIT(){}
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microVUf(void) mVU_RGET(){}
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microVUf(void) mVU_RNEXT(){}
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microVUf(void) mVU_RXOR(){}
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microVUf(void) mVU_WAITP(){}
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microVUf(void) mVU_ESADD(){}
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microVUf(void) mVU_ERSADD(){}
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microVUf(void) mVU_ELENG(){}
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microVUf(void) mVU_ERLENG(){}
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microVUf(void) mVU_EATANxy(){}
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microVUf(void) mVU_EATANxz(){}
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microVUf(void) mVU_ESUM(){}
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microVUf(void) mVU_ERCPR(){}
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microVUf(void) mVU_ESQRT(){}
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microVUf(void) mVU_ERSQRT(){}
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microVUf(void) mVU_ESIN(){}
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microVUf(void) mVU_EATAN(){}
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microVUf(void) mVU_EEXP(){}
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microVUf(void) mVU_WAITQ(){}
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microVUf(void) mVU_XGKICK(){}
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microVUf(void) mVU_XTOP(){}
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microVUf(void) mVU_XITOP(){}
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microVUf(void) mVU_XTOP() {
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microVU* mVU = mVUx;
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if (recPass == 0) {}
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else {
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MOVZX32M16toR( gprT1, (uptr)&mVU->regs->vifRegs->top);
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mVUallocVIb<vuIndex>(gprT1, _Ft_);
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}
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}
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microVUf(void) mVU_XITOP() {
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microVU* mVU = mVUx;
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if (recPass == 0) {}
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else {
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MOVZX32M16toR( gprT1, (uptr)&mVU->regs->vifRegs->itop );
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mVUallocVIb<vuIndex>(gprT1, _Ft_);
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}
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}
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#endif //PCSX2_MICROVU
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@ -55,11 +55,12 @@ PCSX2_ALIGNED16_EXTERN(const float mVU_ITOF_15[4]);
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#define _bc_z ((mVU->code & 0x03) == 2)
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#define _bc_w ((mVU->code & 0x03) == 3)
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#define _Fsf_ ((mVU->code >> 21) & 0x03)
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#define _Ftf_ ((mVU->code >> 23) & 0x03)
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#define _Fsf_ ((mVU->code >> 21) & 0x03)
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#define _Ftf_ ((mVU->code >> 23) & 0x03)
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#define _Imm11_ (s32)(mVU->code & 0x400 ? 0xfffffc00 | (mVU->code & 0x3ff) : mVU->code & 0x3ff)
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#define _UImm11_ (s32)(mVU->code & 0x7ff)
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#define _Imm12_ (((mVU->code >> 21 ) & 0x1) << 11) | (mVU->code & 0x7ff)
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#define xmmT1 0 // Temp Reg
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#define xmmFs 1 // Holds the Value of Fs (writes back result Fd)
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@ -70,14 +71,14 @@ PCSX2_ALIGNED16_EXTERN(const float mVU_ITOF_15[4]);
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#define xmmACC3 6 // Holds ACC Instance #3
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#define xmmPQ 7 // Holds the Value and Backup Values of P and Q regs
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#define mmxT1 0 // Temp Reg
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#define mmxC 1 // Clip Flag?
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#define mmxVI0 2 // Holds VI 00 to 03?
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#define mmxVI1 3 // Holds VI 04 to 07?
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#define mmxVI2 4 // Holds VI 08 to 11?
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#define mmxVI3 5 // Holds VI 12 to 15?
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#define mmxM 6 // ?
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#define mmxS 7 // ?
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#define mmxVI1 0 // Holds VI 1
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#define mmxVI2 1 // Holds VI 2
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#define mmxVI3 2 // Holds VI 3
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#define mmxVI4 3 // Holds VI 4
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#define mmxVI5 4 // Holds VI 5
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#define mmxVI6 5 // Holds VI 6
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#define mmxVI7 6 // Holds VI 7
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#define mmxVI8 7 // Holds VI 8
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#define gprT1 0 // Temp Reg
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#define gprT2 1 // Temp Reg
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@ -103,7 +104,8 @@ PCSX2_ALIGNED16_EXTERN(const float mVU_ITOF_15[4]);
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#define readACC ((mVUallocInfo.info[mVUallocInfo.curPC] & (3<<3)) >> 3)
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#define writeQ ((mVUallocInfo.info[mVUallocInfo.curPC] & (1<<5)) >> 5)
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#define readQ ((mVUallocInfo.info[mVUallocInfo.curPC] & (1<<6)) >> 6)
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//#define setFd (mVUallocInfo.info[mVUallocInfo.curPC] & (1<<7))
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#define writeP ((mVUallocInfo.info[mVUallocInfo.curPC] & (1<<7)) >> 7)
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#define readP ((mVUallocInfo.info[mVUallocInfo.curPC] & (1<<7)) >> 7) // same as write
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#define doFlags (mVUallocInfo.info[mVUallocInfo.curPC] & (3<<8))
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#define doMac (mVUallocInfo.info[mVUallocInfo.curPC] & (1<<8))
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#define doStatus (mVUallocInfo.info[mVUallocInfo.curPC] & (1<<9))
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@ -111,6 +113,8 @@ PCSX2_ALIGNED16_EXTERN(const float mVU_ITOF_15[4]);
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#define fsInstance ((mVUallocInfo.info[mVUallocInfo.curPC] & (3<<12)) >> 12)
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#define fpmInstance (((u8)((mVUallocInfo.info[mVUallocInfo.curPC] & (3<<10)) >> 10) - 1) & 0x3)
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#define fpsInstance (((u8)((mVUallocInfo.info[mVUallocInfo.curPC] & (3<<12)) >> 12) - 1) & 0x3)
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#define fvmInstance ((mVUallocInfo.info[mVUallocInfo.curPC] & (3<<14)) >> 14)
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#define fvsInstance ((mVUallocInfo.info[mVUallocInfo.curPC] & (3<<16)) >> 16)
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//#define getFs (mVUallocInfo.info[mVUallocInfo.curPC] & (1<<13))
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//#define getFt (mVUallocInfo.info[mVUallocInfo.curPC] & (1<<14))
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Reference in New Issue