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microVU: Finally fixed the Kingdom Hearts missing poly bug =D 

git-svn-id: http://pcsx2.googlecode.com/svn/trunk@1668 96395faa-99c1-11dd-bbfe-3dabce05a288
This commit is contained in:
cottonvibes 2009-08-22 03:13:50 +00:00
parent 643e884b03
commit a5884b6577
5 changed files with 31 additions and 6 deletions
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9
pcsx2/x86/microVU.h
View File

@ -96,6 +96,15 @@ public:
} }
return NULL; return NULL;
} }
void printInfo() {
microBlockLink* linkI = &blockList;
for (int i = 0; i <= listI; i++) {
DevCon::Status("[Block #%d][q=%02d][p=%02d][xgkick=%d][vi15=%08x][viBackup=%02d][flags=%02x][exactMatch=%x]",
params i, linkI->block->pState.q, linkI->block->pState.p, linkI->block->pState.xgkick, linkI->block->pState.vi15,
linkI->block->pState.viBackUp, linkI->block->pState.flags, linkI->block->pState.needExactMatch);
linkI = linkI->next;
}
}
}; };
#define mMaxRanges 128 #define mMaxRanges 128

8
pcsx2/x86/microVU_Execute.inl
View File

@ -130,6 +130,14 @@ microVUx(void) mVUcleanUp() {
mVU->cycles = mVU->totalCycles - mVU->cycles; mVU->cycles = mVU->totalCycles - mVU->cycles;
mVU->regs->cycle += mVU->cycles; mVU->regs->cycle += mVU->cycles;
cpuRegs.cycle += ((mVU->cycles < 3000) ? mVU->cycles : 3000) * Config.Hacks.VUCycleSteal; cpuRegs.cycle += ((mVU->cycles < 3000) ? mVU->cycles : 3000) * Config.Hacks.VUCycleSteal;
//static int ax = 0; ax++;
//if (!(ax % 100000)) {
// for (u32 i = 0; i < (mVU->progSize / 2); i++) {
// if (mVUcurProg.block[i]) {
// mVUcurProg.block[i]->printInfo();
// }
// }
//}
} }
//------------------------------------------------------------------ //------------------------------------------------------------------

4
pcsx2/x86/microVU_Flags.inl
View File

@ -238,8 +238,9 @@ void mVUflagPass(mV, u32 startPC, u32 xCount) {
iPC = startPC / 4; iPC = startPC / 4;
mVUcount = 0; mVUcount = 0;
mVUbranch = 0; mVUbranch = 0;
for (int branch = 0; mVUcount < xCount; mVUcount++) { for (int branch = 0; mVUcount < xCount; mVUcount=(mVUregs.needExactMatch&8)?(mVUcount+1):mVUcount) {
incPC(1); incPC(1);
mVUopU(mVU, 3);
if ( curI & _Ebit_ ) { branch = 1; } if ( curI & _Ebit_ ) { branch = 1; }
if ( curI & _DTbit_ ) { branch = 6; } if ( curI & _DTbit_ ) { branch = 6; }
if (!(curI & _Ibit_) ) { incPC(-1); mVUopL(mVU, 3); incPC(1); } if (!(curI & _Ibit_) ) { incPC(-1); mVUopL(mVU, 3); incPC(1); }
@ -276,5 +277,6 @@ microVUt(void) mVUsetFlagInfo(mV) {
incPC(-3); incPC(-3);
mVUregs.needExactMatch |= backupFlagInfo; mVUregs.needExactMatch |= backupFlagInfo;
} }
mVUregs.needExactMatch &= 0x7;
} }

6
pcsx2/x86/microVU_Lower.inl
View File

@ -520,7 +520,7 @@ mVUop(mVU_FMAND) {
mVUallocVIb(mVU, gprT1, _It_); mVUallocVIb(mVU, gprT1, _It_);
} }
pass3 { mVUlog("FMAND vi%02d, vi%02d", _Ft_, _Fs_); } pass3 { mVUlog("FMAND vi%02d, vi%02d", _Ft_, _Fs_); }
pass4 { mVUregs.needExactMatch |= 2; } pass4 { mVUregs.needExactMatch |= 2; }
} }
mVUop(mVU_FMEQ) { mVUop(mVU_FMEQ) {
@ -534,7 +534,7 @@ mVUop(mVU_FMEQ) {
mVUallocVIb(mVU, gprT1, _It_); mVUallocVIb(mVU, gprT1, _It_);
} }
pass3 { mVUlog("FMEQ vi%02d, vi%02d", _Ft_, _Fs_); } pass3 { mVUlog("FMEQ vi%02d, vi%02d", _Ft_, _Fs_); }
pass4 { mVUregs.needExactMatch |= 2; } pass4 { mVUregs.needExactMatch |= 2; }
} }
mVUop(mVU_FMOR) { mVUop(mVU_FMOR) {
@ -546,7 +546,7 @@ mVUop(mVU_FMOR) {
mVUallocVIb(mVU, gprT1, _It_); mVUallocVIb(mVU, gprT1, _It_);
} }
pass3 { mVUlog("FMOR vi%02d, vi%02d", _Ft_, _Fs_); } pass3 { mVUlog("FMOR vi%02d, vi%02d", _Ft_, _Fs_); }
pass4 { mVUregs.needExactMatch |= 2; } pass4 { mVUregs.needExactMatch |= 2; }
} }
//------------------------------------------------------------------ //------------------------------------------------------------------

6
pcsx2/x86/microVU_Upper.inl
View File

@ -172,6 +172,7 @@ void mVU_FMACa(microVU* mVU, int recPass, int opCase, int opType, bool isACC, co
mVU->regAlloc->clearNeeded(Ft); mVU->regAlloc->clearNeeded(Ft);
} }
pass3 { mVU_printOP(mVU, opCase, opName, isACC); } pass3 { mVU_printOP(mVU, opCase, opName, isACC); }
pass4 { if ((opType != 3) && (opType != 4)) mVUregs.needExactMatch |= 8; }
} }
// MADDA/MSUBA Opcodes // MADDA/MSUBA Opcodes
@ -210,6 +211,7 @@ void mVU_FMACb(microVU* mVU, int recPass, int opCase, int opType, const char* op
mVU->regAlloc->clearNeeded(Ft); mVU->regAlloc->clearNeeded(Ft);
} }
pass3 { mVU_printOP(mVU, opCase, opName, 1); } pass3 { mVU_printOP(mVU, opCase, opName, 1); }
pass4 { mVUregs.needExactMatch |= 8; }
} }
// MADD Opcodes // MADD Opcodes
@ -237,6 +239,7 @@ void mVU_FMACc(microVU* mVU, int recPass, int opCase, const char* opName) {
mVU->regAlloc->clearNeeded(ACC); mVU->regAlloc->clearNeeded(ACC);
} }
pass3 { mVU_printOP(mVU, opCase, opName, 0); } pass3 { mVU_printOP(mVU, opCase, opName, 0); }
pass4 { mVUregs.needExactMatch |= 8; }
} }
// MSUB Opcodes // MSUB Opcodes
@ -259,6 +262,7 @@ void mVU_FMACd(microVU* mVU, int recPass, int opCase, const char* opName) {
mVU->regAlloc->clearNeeded(Fs); mVU->regAlloc->clearNeeded(Fs);
} }
pass3 { mVU_printOP(mVU, opCase, opName, 0); } pass3 { mVU_printOP(mVU, opCase, opName, 0); }
pass4 { mVUregs.needExactMatch |= 8; }
} }
// ABS Opcode // ABS Opcode
@ -288,6 +292,7 @@ mVUop(mVU_OPMULA) {
mVU->regAlloc->clearNeeded(Fs); mVU->regAlloc->clearNeeded(Fs);
} }
pass3 { mVUlog("OPMULA"); mVUlogACC(); mVUlogFt(); } pass3 { mVUlog("OPMULA"); mVUlogACC(); mVUlogFt(); }
pass4 { mVUregs.needExactMatch |= 8; }
} }
// OPMSUB Opcode // OPMSUB Opcode
@ -309,6 +314,7 @@ mVUop(mVU_OPMSUB) {
} }
pass3 { mVUlog("OPMSUB"); mVUlogFd(); mVUlogFt(); } pass3 { mVUlog("OPMSUB"); mVUlogFd(); mVUlogFt(); }
pass4 { mVUregs.needExactMatch |= 8; }
} }
// FTOI0/FTIO4/FTIO12/FTIO15 Opcodes // FTOI0/FTIO4/FTIO12/FTIO15 Opcodes