diff --git a/pcsx2/x86/microVU.h b/pcsx2/x86/microVU.h
index 49ae3feef6..b3231bafbd 100644
--- a/pcsx2/x86/microVU.h
+++ b/pcsx2/x86/microVU.h
@@ -96,6 +96,15 @@ public:
 		}
 		return NULL;
 	}
+	void printInfo() {
+		microBlockLink* linkI = &blockList;
+		for (int i = 0; i <= listI; i++) {
+			DevCon::Status("[Block #%d][q=%02d][p=%02d][xgkick=%d][vi15=%08x][viBackup=%02d][flags=%02x][exactMatch=%x]",
+			params i, linkI->block->pState.q, linkI->block->pState.p, linkI->block->pState.xgkick, linkI->block->pState.vi15,
+			linkI->block->pState.viBackUp, linkI->block->pState.flags, linkI->block->pState.needExactMatch);
+			linkI = linkI->next;
+		}
+	}
 };
 
 #define mMaxRanges 128
diff --git a/pcsx2/x86/microVU_Execute.inl b/pcsx2/x86/microVU_Execute.inl
index 673d9ce10c..76c0e4fb5d 100644
--- a/pcsx2/x86/microVU_Execute.inl
+++ b/pcsx2/x86/microVU_Execute.inl
@@ -130,6 +130,14 @@ microVUx(void) mVUcleanUp() {
 	mVU->cycles = mVU->totalCycles - mVU->cycles;
 	mVU->regs->cycle += mVU->cycles;
 	cpuRegs.cycle += ((mVU->cycles < 3000) ? mVU->cycles : 3000) * Config.Hacks.VUCycleSteal;
+	//static int ax = 0; ax++;
+	//if (!(ax % 100000)) {
+	//	for (u32 i = 0; i < (mVU->progSize / 2); i++) {
+	//		if (mVUcurProg.block[i]) {
+	//			mVUcurProg.block[i]->printInfo();
+	//		}
+	//	}
+	//}
 }
 
 //------------------------------------------------------------------
diff --git a/pcsx2/x86/microVU_Flags.inl b/pcsx2/x86/microVU_Flags.inl
index ddc58d5fe0..aaecae5f16 100644
--- a/pcsx2/x86/microVU_Flags.inl
+++ b/pcsx2/x86/microVU_Flags.inl
@@ -238,8 +238,9 @@ void mVUflagPass(mV, u32 startPC, u32 xCount) {
 	iPC		  = startPC / 4;
 	mVUcount  = 0;
 	mVUbranch = 0;
-	for (int branch = 0; mVUcount < xCount; mVUcount++) {
+	for (int branch = 0; mVUcount < xCount; mVUcount=(mVUregs.needExactMatch&8)?(mVUcount+1):mVUcount) {
 		incPC(1);
+		mVUopU(mVU, 3);
 		if (  curI & _Ebit_  )	{ branch = 1; }
 		if (  curI & _DTbit_ )	{ branch = 6; }
 		if (!(curI & _Ibit_) )	{ incPC(-1); mVUopL(mVU, 3); incPC(1); }
@@ -267,14 +268,15 @@ microVUt(void) mVUsetFlagInfo(mV) {
 		else { mVUflagPass(mVU, (mVUlow.constJump.regValue*8)&(mVU->microMemSize-8), 4); }
 	}
 	branchType3 {
-		incPC(-1); 
+		incPC(-1);
 		mVUflagPass(mVU, branchAddr, 4);
 		int backupFlagInfo = mVUregs.needExactMatch;
 		mVUregs.needExactMatch = 0;
 		incPC(4); // Branch Not Taken
 		mVUflagPass(mVU, xPC, 4);
-		incPC(-3);		
+		incPC(-3);
 		mVUregs.needExactMatch |= backupFlagInfo;
 	}
+	mVUregs.needExactMatch &= 0x7;
 }
 
diff --git a/pcsx2/x86/microVU_Lower.inl b/pcsx2/x86/microVU_Lower.inl
index 03df227c96..cf51547bf5 100644
--- a/pcsx2/x86/microVU_Lower.inl
+++ b/pcsx2/x86/microVU_Lower.inl
@@ -520,7 +520,7 @@ mVUop(mVU_FMAND) {
 		mVUallocVIb(mVU, gprT1, _It_);
 	}
 	pass3 { mVUlog("FMAND vi%02d, vi%02d", _Ft_, _Fs_); }
-	pass4 { mVUregs.needExactMatch |= 2;   }
+	pass4 { mVUregs.needExactMatch |= 2; }
 }
 
 mVUop(mVU_FMEQ) {
@@ -534,7 +534,7 @@ mVUop(mVU_FMEQ) {
 		mVUallocVIb(mVU, gprT1, _It_);
 	}
 	pass3 { mVUlog("FMEQ vi%02d, vi%02d", _Ft_, _Fs_); }
-	pass4 { mVUregs.needExactMatch |= 2;  }
+	pass4 { mVUregs.needExactMatch |= 2; }
 }
 
 mVUop(mVU_FMOR) {
@@ -546,7 +546,7 @@ mVUop(mVU_FMOR) {
 		mVUallocVIb(mVU, gprT1, _It_);
 	}
 	pass3 { mVUlog("FMOR vi%02d, vi%02d", _Ft_, _Fs_); }
-	pass4 { mVUregs.needExactMatch |= 2;  }
+	pass4 { mVUregs.needExactMatch |= 2; }
 }
 
 //------------------------------------------------------------------
diff --git a/pcsx2/x86/microVU_Upper.inl b/pcsx2/x86/microVU_Upper.inl
index 2b152f5493..9d0d074f14 100644
--- a/pcsx2/x86/microVU_Upper.inl
+++ b/pcsx2/x86/microVU_Upper.inl
@@ -172,6 +172,7 @@ void mVU_FMACa(microVU* mVU, int recPass, int opCase, int opType, bool isACC, co
 		mVU->regAlloc->clearNeeded(Ft);
 	}
 	pass3 { mVU_printOP(mVU, opCase, opName, isACC); }
+	pass4 { if ((opType != 3) && (opType != 4)) mVUregs.needExactMatch |= 8; }
 }
 
 // MADDA/MSUBA Opcodes
@@ -210,6 +211,7 @@ void mVU_FMACb(microVU* mVU, int recPass, int opCase, int opType, const char* op
 		mVU->regAlloc->clearNeeded(Ft);
 	}
 	pass3 { mVU_printOP(mVU, opCase, opName, 1); }
+	pass4 { mVUregs.needExactMatch |= 8; }
 }
 
 // MADD Opcodes
@@ -237,6 +239,7 @@ void mVU_FMACc(microVU* mVU, int recPass, int opCase, const char* opName) {
 		mVU->regAlloc->clearNeeded(ACC);
 	}
 	pass3 { mVU_printOP(mVU, opCase, opName, 0); }
+	pass4 { mVUregs.needExactMatch |= 8; }
 }
 
 // MSUB Opcodes
@@ -259,6 +262,7 @@ void mVU_FMACd(microVU* mVU, int recPass, int opCase, const char* opName) {
 		mVU->regAlloc->clearNeeded(Fs);
 	}
 	pass3 { mVU_printOP(mVU, opCase, opName, 0); }
+	pass4 { mVUregs.needExactMatch |= 8; }
 }
 
 // ABS Opcode
@@ -288,6 +292,7 @@ mVUop(mVU_OPMULA) {
 		mVU->regAlloc->clearNeeded(Fs);
 	}
 	pass3 { mVUlog("OPMULA"); mVUlogACC(); mVUlogFt(); }
+	pass4 { mVUregs.needExactMatch |= 8; }
 }
 
 // OPMSUB Opcode
@@ -309,6 +314,7 @@ mVUop(mVU_OPMSUB) {
 
 	}
 	pass3 { mVUlog("OPMSUB"); mVUlogFd(); mVUlogFt(); }
+	pass4 { mVUregs.needExactMatch |= 8; }
 }
 
 // FTOI0/FTIO4/FTIO12/FTIO15 Opcodes