Stub out some functions in the cache code.

git-svn-id: http://pcsx2.googlecode.com/svn/trunk@1588 96395faa-99c1-11dd-bbfe-3dabce05a288

common/include/Pcsx2Config.h

@@ -120,6 +120,10 @@ extern SessionOverrideFlags g_Session;
 
 #define EE_CONST_PROP // rec2 - enables constant propagation (faster)
 
+// These are broken, so don't enable.
+//#define PCSX2_CACHE_EMU_MEM
+//#define ENABLECACHE
+
 // Memory Card configuration, per slot.
 struct McdConfig
 {

pcsx2/Cache.cpp

@@ -26,9 +26,8 @@ _cacheS pCache[64];
 namespace R5900{
 namespace Interpreter 
 {
-
-// fixme - this code no longer compiles if PCSX2_CACHE_EMU_MEM is defined - do we need it any more?
 #ifdef PCSX2_CACHE_EMU_MEM
+
 int getFreeCache(u32 mem, int mode, int * way) {
 	u8 * out;
 	u32 paddr;
@@ -37,15 +36,16 @@ int getFreeCache(u32 mem, int mode, int * way) {
 	int number;
 	int i = (mem >> 6) & 0x3F;
 	
-	paddr = memLUTR[mem >> 12];
+	paddr = getMemR(mem);
-	taddr[0] = memLUTW[pCache[i].tag[0]>>12];
+	taddr[0] = getMemW(pCache[i].tag[0]);
-	taddr[1] = memLUTW[pCache[i].tag[1]>>12];
+	taddr[1] = getMemW(pCache[i].tag[1]);
 
 	if (taddr[0] == paddr && (pCache[i].tag[0] & 0x20)) 
 	{
 		*way = 0;
 		return i;
-	}else if(taddr[1] == paddr && (pCache[i].tag[1] & 0x20)) 
+	}
+	else if(taddr[1] == paddr && (pCache[i].tag[1] & 0x20)) 
 	{
 		*way = 1;
 		return i;
@@ -67,8 +67,6 @@ int getFreeCache(u32 mem, int mode, int * way) {
 		((u64*)out)[7] = ((u64*)pCache[i].data[number][3].b8._8)[1];
 	}
 	
-
-	
 	if(mode == 1)
 	{
 		pCache[i].tag[number] |= 0x40;	// Set Dirty Bit if mode == write
@@ -89,8 +87,10 @@ int getFreeCache(u32 mem, int mode, int * way) {
 	((u64*)pCache[i].data[number][3].b8._8)[0] = ((u64*)out)[6];
 	((u64*)pCache[i].data[number][3].b8._8)[1] = ((u64*)out)[7];
 
-	if(pCache[i].tag[number] & 0x10) pCache[i].tag[number] &= ~(0x10);
+	if(pCache[i].tag[number] & 0x10)
-	else pCache[i].tag[number] |= 0x10;
+		pCache[i].tag[number] &= ~(0x10);
+	else 
+		pCache[i].tag[number] |= 0x10;
 	
 	pCache[i].tag[number] |= 0x20;
 	*way = number;
@@ -163,9 +163,9 @@ void CACHE() {
 			int index = (addr >> 6) & 0x3F;
 			u32 paddr[2];
 			int way;
-			u32 taddr = memLUTR[addr >> 12];
+			u32 taddr = getMemR(addr);
-			paddr[0] = memLUTW[pCache[index].tag[0] >> 12];
+			paddr[0] = getMemW(pCache[index].tag[0]);
-			paddr[1] = memLUTW[pCache[index].tag[1] >> 12];
+			paddr[1] = getMemW(pCache[index].tag[1]);
 
 			if(paddr[0] == taddr && (pCache[index].tag[0] & 0x20))
 			{
@@ -199,9 +199,9 @@ void CACHE() {
 			int index = (addr >> 6) & 0x3F;
 			u32 paddr[2];
 			int way;
-			u32 taddr = memLUTW[addr >> 12];
+			u32 taddr = getMemW(addr);
-			paddr[0] = memLUTW[pCache[index].tag[0] >> 12];
+			paddr[0] = getMemW(pCache[index].tag[0]);
-			paddr[1] = memLUTW[pCache[index].tag[1] >> 12];
+			paddr[1] = getMemW(pCache[index].tag[1]);
 
 			if(paddr[0] == taddr && (pCache[index].tag[0] & 0x20))
 			{
@@ -250,9 +250,9 @@ void CACHE() {
 			int index = (addr >> 6) & 0x3F;
 			u32 paddr[2];
 			int way;
-			u32 taddr = memLUTW[addr >> 12];
+			u32 taddr = getMemW(addr);
-			paddr[0] = memLUTW[pCache[index].tag[0] >> 12];
+			paddr[0] = getMemW(pCache[index].tag[0]);
-			paddr[1] = memLUTW[pCache[index].tag[1] >> 12];
+			paddr[1] = getMemW(pCache[index].tag[1]);
 
 			if(paddr[0] == taddr && (pCache[index].tag[0] & 0x20))
 			{
@@ -360,7 +360,7 @@ void CACHE() {
 
 			if(pCache[index].tag[way] & 0x60)	// Dirty
 			{
-				u32 paddr = memLUTW[pCache[index].tag[way] >> 12];
+				u32 paddr = getMemW(pCache[index].tag[way]);
 				char * t = (char *)(paddr);
 				out = (u8*)(t + (addr & 0xFC0));
 				((u64*)out)[0] = ((u64*)pCache[index].data[way][0].b8._8)[0];

pcsx2/Cache.h

@@ -45,4 +45,15 @@ void writeCache64(u32 mem, u64 value);
 void writeCache128(u32 mem, u64 *value);
 u8  *readCache(u32 mem);
 
+// Fixme - these two functions do nothing, and the cache code relies on these two functions.	
+static __forceinline u32 getMemR(s32 mem)
+{
+	return 0;//memLUTR[mem >> 12];
+}
+
+static __forceinline u32 getMemW(s32 mem)
+{
+	return 0;//memLUTW[mem>>12];
+}
+
 #endif /* __CACHE_H__ */

pcsx2/Memory.cpp

@@ -594,8 +594,8 @@ void memClearPageAddr(u32 vaddr)
 	vtlb_VMapUnmap(vaddr,0x1000); // -> whut ?
 
 #ifdef FULLTLB
-	memLUTRK[vaddr >> 12] = 0;
+//	memLUTRK[vaddr >> 12] = 0;
-	memLUTWK[vaddr >> 12] = 0;
+//	memLUTWK[vaddr >> 12] = 0;
 #endif
 }
 

pcsx2/x86/ix86-32/iCore-32.cpp

@@ -53,14 +53,14 @@ u32 _x86GetAddr(int type, int reg)
 	switch(type&~X86TYPE_VU1) 
 	{
 		case X86TYPE_GPR: 
-			ret = &cpuRegs.GPR.r[reg]; 
+			ret = (u32)&cpuRegs.GPR.r[reg]; 
 			break;
 		
 		case X86TYPE_VI: 
 			if (type & X86TYPE_VU1)
-				ret = &VU1.VI[reg];
+				ret = (u32)&VU1.VI[reg];
 			else
-				ret = &VU0.VI[reg];
+				ret = (u32)&VU0.VI[reg];
 			break;
 		
 		case X86TYPE_MEMOFFSET: 
@@ -73,30 +73,30 @@ u32 _x86GetAddr(int type, int reg)
 		
 		case X86TYPE_VUQREAD:
 			if  (type & X86TYPE_VU1)
-				ret = &VU1.VI[REG_Q];
+				ret = (u32)&VU1.VI[REG_Q];
 			else
-				ret =&VU0.VI[REG_Q];
+				ret = (u32)&VU0.VI[REG_Q];
 			break;
 		
 		case X86TYPE_VUPREAD: 
 			if  (type & X86TYPE_VU1)
-				ret = &VU1.VI[REG_P];
+				ret = (u32)&VU1.VI[REG_P];
 			else
-				ret =&VU0.VI[REG_P];
+				ret = (u32)&VU0.VI[REG_P];
 			break;
 		
 		case X86TYPE_VUQWRITE: 
 			if  (type & X86TYPE_VU1)
-				ret = &VU1.q;
+				ret = (u32)&VU1.q;
 			else
-				ret =&VU0.q;
+				ret = (u32)&VU0.q;
 			break;
 		
 		case X86TYPE_VUPWRITE: 
 			if  (type & X86TYPE_VU1)
-				ret = &VU1.p;
+				ret = (u32)&VU1.p;
 			else
-				ret =&VU0.p;
+				ret = (u32)&VU0.p;
 			break;
 		
 		case X86TYPE_PSX: