mirror of https://github.com/PCSX2/pcsx2.git
Some cleanup around iCore.
git-svn-id: http://pcsx2.googlecode.com/svn/trunk@1587 96395faa-99c1-11dd-bbfe-3dabce05a288
This commit is contained in:
arcum42
parent
3d18ddf16b
commit
d1f8bf4d71
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@ -41,7 +41,7 @@ enum gifstate_t
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// Should be a gifstate_t rather then int, but I don't feel like possibly interfering with savestates right now.
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static int gifstate = GIF_STATE_READY;
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static u64 s_gstag = 0; // used for querying the last tag
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//static u64 s_gstag = 0; // used for querying the last tag
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// This should be a bool, as should the return value of hwDmacSrcChainWithStack.
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// Next time I feel like breaking the save state, it will be. --arcum42
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@ -667,7 +667,7 @@ void psxHwWrite8(u32 add, u8 value) {
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case 0x1f80380c:
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{
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bool flush = false;
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//bool flush = false;
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// Terminate lines on CR or full buffers, and ignore \n's if the string contents
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// are empty (otherwise terminate on \n too!)
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@ -99,7 +99,7 @@ int _getFreeXMMreg()
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for (i=0; i<iREGCNT_XMM; i++) {
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if (xmmregs[i].needed) continue;
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if (xmmregs[i].type == XMMTYPE_GPRREG ) {
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if( !(g_pCurInstInfo->regs[xmmregs[i].reg] & (EEINST_LIVE0|EEINST_LIVE1|EEINST_LIVE2)) ) {
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if (!(EEINST_ISLIVEXMM(xmmregs[i].reg))) {
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_freeXMMreg(i);
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return i;
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}
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@ -144,12 +144,10 @@ int _getFreeXMMreg()
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}
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int _allocTempXMMreg(XMMSSEType type, int xmmreg) {
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if (xmmreg == -1) {
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if (xmmreg == -1)
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xmmreg = _getFreeXMMreg();
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}
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else {
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else
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_freeXMMreg(xmmreg);
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}
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xmmregs[xmmreg].inuse = 1;
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xmmregs[xmmreg].type = XMMTYPE_TEMP;
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@ -102,7 +102,11 @@
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#define X86TYPE_VU1 0x80
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#define X86_ISVI(type) ((type&~X86TYPE_VU1) == X86TYPE_VI)
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//#define X86_ISVI(type) ((type&~X86TYPE_VU1) == X86TYPE_VI)
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static __forceinline int X86_ISVI(int type)
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{
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return ((type&~X86TYPE_VU1) == X86TYPE_VI);
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}
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struct _x86regs {
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u8 inuse;
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@ -199,25 +203,37 @@ int _signExtendXMMtoM(u32 to, x86SSERegType from, int candestroy); // returns tr
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// only valid during writes. If write128, then upper 64bits are in an mmxreg
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// (mmreg&0xf). Constant is used from gprreg ((mmreg>>16)&0x1f)
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#define MEM_EECONSTTAG 0x0100 // argument is a GPR and comes from g_cpuConstRegs
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#define MEM_PSXCONSTTAG 0x0200
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#define MEM_MEMORYTAG 0x0400
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#define MEM_MMXTAG 0x0800 // mmreg is mmxreg
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#define MEM_XMMTAG 0x8000 // mmreg is xmmreg
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#define MEM_X86TAG 0x4000 // ignored most of the time
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#define MEM_GPRTAG 0x2000 // argument is a GPR reg
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#define MEM_CONSTTAG 0x1000 // argument is a const
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enum memtag
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{
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MEM_EECONSTTAG = 0x0100, // argument is a GPR and comes from g_cpuConstRegs
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MEM_PSXCONSTTAG = 0x0200,
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MEM_MEMORYTAG = 0x0400,
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MEM_MMXTAG = 0x0800, // mmreg is mmxreg
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MEM_XMMTAG = 0x8000, // mmreg is xmmreg
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MEM_X86TAG = 0x4000, // ignored most of the time
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MEM_GPRTAG = 0x2000, // argument is a GPR reg
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MEM_CONSTTAG = 0x1000 // argument is a const
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};
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#define IS_EECONSTREG(reg) (reg>=0&&((reg)&MEM_EECONSTTAG))
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#define IS_PSXCONSTREG(reg) (reg>=0&&((reg)&MEM_PSXCONSTTAG))
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#define IS_MMXREG(reg) (reg>=0&&((reg)&MEM_MMXTAG))
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#define IS_XMMREG(reg) (reg>=0&&((reg)&MEM_XMMTAG))
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template<memtag tag> static __forceinline bool IS_REG(s32 reg)
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{
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return ((reg >= 0) && (reg & tag));
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}
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// fixme - these 4 are only called for u32 registers; should the reg>=0 really be there?
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#define IS_X86REG(reg) (reg>=0&&((reg)&MEM_X86TAG))
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#define IS_GPRREG(reg) (reg>=0&&((reg)&MEM_GPRTAG))
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#define IS_CONSTREG(reg) (reg>=0&&((reg)&MEM_CONSTTAG))
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#define IS_MEMORYREG(reg) (reg>=0&&((reg)&MEM_MEMORYTAG))
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template<memtag tag> static __forceinline bool IS_REG(u32 reg)
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{
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return (reg & tag);
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}
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#define IS_EECONSTREG(reg) IS_REG<MEM_EECONSTTAG>(reg)
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#define IS_PSXCONSTREG(reg) IS_REG<MEM_PSXCONSTTAG>(reg)
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#define IS_MMXREG(reg) IS_REG<MEM_MMXTAG>(reg)
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#define IS_XMMREG(reg) IS_REG<MEM_XMMTAG>(reg)
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#define IS_X86REG(reg) IS_REG<MEM_X86TAG>(reg)
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#define IS_GPRREG(reg) IS_REG<MEM_GPRTAG>(reg)
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#define IS_CONSTREG(reg) IS_REG<MEM_CONSTTAG>(reg)
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#define IS_MEMORYREG(reg) IS_REG<MEM_MEMORYTAG>(reg)
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//////////////////////
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// Instruction Info //
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@ -265,13 +281,13 @@ extern u32 _recIsRegWritten(EEINST* pinst, int size, u8 xmmtype, u8 reg);
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extern u32 _recIsRegUsed(EEINST* pinst, int size, u8 xmmtype, u8 reg);
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extern void _recFillRegister(EEINST& pinst, int type, int reg, int write);
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#define EEINST_ISLIVE64(reg) (g_pCurInstInfo->regs[reg] & (EEINST_LIVE0|EEINST_LIVE1))
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#define EEINST_ISLIVEXMM(reg) (g_pCurInstInfo->regs[reg] & (EEINST_LIVE0|EEINST_LIVE1|EEINST_LIVE2))
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#define EEINST_ISLIVE1(reg) (g_pCurInstInfo->regs[reg] & EEINST_LIVE1)
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#define EEINST_ISLIVE2(reg) (g_pCurInstInfo->regs[reg] & EEINST_LIVE2)
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static __forceinline bool EEINST_ISLIVE64(u32 reg) { return (g_pCurInstInfo->regs[reg] & (EEINST_LIVE0|EEINST_LIVE1)); }
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static __forceinline bool EEINST_ISLIVEXMM(u32 reg) { return (g_pCurInstInfo->regs[reg] & (EEINST_LIVE0|EEINST_LIVE1|EEINST_LIVE2)); }
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static __forceinline bool EEINST_ISLIVE1(u32 reg) { return (g_pCurInstInfo->regs[reg] & EEINST_LIVE1); }
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static __forceinline bool EEINST_ISLIVE2(u32 reg) { return (g_pCurInstInfo->regs[reg] & EEINST_LIVE2); }
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#define FPUINST_ISLIVE(reg) (g_pCurInstInfo->fpuregs[reg] & EEINST_LIVE0)
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#define FPUINST_LASTUSE(reg) (g_pCurInstInfo->fpuregs[reg] & EEINST_LASTUSE)
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static __forceinline bool FPUINST_ISLIVE(u32 reg) { return (g_pCurInstInfo->fpuregs[reg] & EEINST_LIVE0); }
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static __forceinline bool FPUINST_LASTUSE(u32 reg) { return (g_pCurInstInfo->fpuregs[reg] & EEINST_LASTUSE); }
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// if set, then the variable at this inst really has its upper 32 bits valid
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// The difference between EEINST_LIVE1 is that the latter is used in back propagation
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@ -309,8 +325,8 @@ void SetMMXstate();
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void SetFPUstate();
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// max is 0x7f, when 0x80 is set, need to flush reg
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#define MMX_GET_CACHE(ptr, index) ((u8*)ptr)[index]
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#define MMX_SET_CACHE(ptr, ind3, ind2, ind1, ind0) ((u32*)ptr)[0] = (ind3<<24)|(ind2<<16)|(ind1<<8)|ind0;
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//#define MMX_GET_CACHE(ptr, index) ((u8*)ptr)[index]
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//#define MMX_SET_CACHE(ptr, ind3, ind2, ind1, ind0) ((u32*)ptr)[0] = (ind3<<24)|(ind2<<16)|(ind1<<8)|ind0;
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#define MMX_GPR 0
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#define MMX_HI XMMGPR_HI
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#define MMX_LO XMMGPR_LO
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@ -319,9 +335,20 @@ void SetFPUstate();
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#define MMX_COP0 96
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#define MMX_TEMP 0x7f
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#define MMX_IS32BITS(x) (((x)>=MMX_FPU&&(x)<MMX_COP0+32)||(x)==MMX_FPUACC)
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// If x is unsigned, the first part of this is always true, and it usually is.
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#define MMX_ISGPR(x) ((x) >= MMX_GPR && (x) < MMX_GPR+34)
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static __forceinline bool MMX_IS32BITS(s32 x)
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{
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return (((x >= MMX_FPU) && (x < MMX_COP0 + 32)) || (x == MMX_FPUACC));
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}
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static __forceinline bool MMX_ISGPR(s32 x)
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{
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return ((x >= MMX_GPR) && (x < MMX_GPR + 34));
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}
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static __forceinline bool MMX_ISGPR(u32 x)
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{
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return (x < MMX_GPR + 34);
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}
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struct _mmxregs {
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u8 inuse;
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@ -32,12 +32,11 @@ using namespace std;
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// landmass of shared code. (air)
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extern u32 g_psxConstRegs[32];
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u16 x86FpuState;
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u16 g_mmxAllocCounter = 0;
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static u16 g_mmxAllocCounter = 0;
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// X86 caching
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int g_x86checknext;
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static int g_x86checknext;
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// use special x86 register allocation for ia32
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@ -49,38 +48,83 @@ void _initX86regs() {
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u32 _x86GetAddr(int type, int reg)
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{
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switch(type&~X86TYPE_VU1) {
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case X86TYPE_GPR: return (u32)&cpuRegs.GPR.r[reg];
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case X86TYPE_VI: {
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//assert( reg < 16 || reg == REG_R );
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return (type&X86TYPE_VU1)?(u32)&VU1.VI[reg]:(u32)&VU0.VI[reg];
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}
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case X86TYPE_MEMOFFSET: return 0;
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case X86TYPE_VIMEMOFFSET: return 0;
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case X86TYPE_VUQREAD: return (type&X86TYPE_VU1)?(u32)&VU1.VI[REG_Q]:(u32)&VU0.VI[REG_Q];
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case X86TYPE_VUPREAD: return (type&X86TYPE_VU1)?(u32)&VU1.VI[REG_P]:(u32)&VU0.VI[REG_P];
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case X86TYPE_VUQWRITE: return (type&X86TYPE_VU1)?(u32)&VU1.q:(u32)&VU0.q;
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case X86TYPE_VUPWRITE: return (type&X86TYPE_VU1)?(u32)&VU1.p:(u32)&VU0.p;
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case X86TYPE_PSX: return (u32)&psxRegs.GPR.r[reg];
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u32 ret = 0;
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switch(type&~X86TYPE_VU1)
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{
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case X86TYPE_GPR:
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ret = &cpuRegs.GPR.r[reg];
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break;
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case X86TYPE_VI:
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if (type & X86TYPE_VU1)
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ret = &VU1.VI[reg];
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else
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ret = &VU0.VI[reg];
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break;
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case X86TYPE_MEMOFFSET:
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ret = 0;
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break;
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case X86TYPE_VIMEMOFFSET:
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ret = 0;
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break;
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case X86TYPE_VUQREAD:
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if (type & X86TYPE_VU1)
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ret = &VU1.VI[REG_Q];
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else
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ret =&VU0.VI[REG_Q];
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break;
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case X86TYPE_VUPREAD:
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if (type & X86TYPE_VU1)
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ret = &VU1.VI[REG_P];
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else
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ret =&VU0.VI[REG_P];
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break;
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case X86TYPE_VUQWRITE:
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if (type & X86TYPE_VU1)
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ret = &VU1.q;
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else
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ret =&VU0.q;
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break;
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case X86TYPE_VUPWRITE:
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if (type & X86TYPE_VU1)
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ret = &VU1.p;
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else
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ret =&VU0.p;
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break;
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case X86TYPE_PSX:
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ret = (u32)&psxRegs.GPR.r[reg];
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break;
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case X86TYPE_PCWRITEBACK:
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return (u32)&g_recWriteback;
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ret = (u32)&g_recWriteback;
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break;
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case X86TYPE_VUJUMP:
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return (u32)&g_recWriteback;
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ret = (u32)&g_recWriteback;
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break;
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jNO_DEFAULT;
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}
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return 0;
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return ret;
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}
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int _getFreeX86reg(int mode)
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{
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int i, tempi;
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int tempi = -1;
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u32 bestcount = 0x10000;
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int maxreg = (mode&MODE_8BITREG)?4:iREGCNT_GPR;
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for (i=0; i<iREGCNT_GPR; i++) {
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for (int i=0; i<iREGCNT_GPR; i++) {
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int reg = (g_x86checknext+i)%iREGCNT_GPR;
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if( reg == 0 || reg == ESP ) continue;
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if( reg >= maxreg ) continue;
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@ -92,8 +136,7 @@ int _getFreeX86reg(int mode)
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}
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}
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tempi = -1;
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for (i=1; i<maxreg; i++) {
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for (int i=1; i<maxreg; i++) {
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if( i == ESP ) continue;
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if( (mode&MODE_NOFRAME) && i==EBP ) continue;
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@ -139,7 +182,6 @@ void _flushConstReg(int reg)
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void _flushConstRegs()
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{
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s32 i, j;
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s32 zero_cnt = 0, minusone_cnt = 0;
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s32 eaxval = 1; // 0, -1
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u32 done[4] = {0, 0, 0, 0};
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@ -149,13 +191,12 @@ void _flushConstRegs()
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// flush 0 and -1 first
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// ignore r0
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for (i = 1, j = 0; i < 32; j++ && ++i, j %= 2) {
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if (!GPR_IS_CONST1(i) || g_cpuFlushedConstReg & (1<<i))
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continue;
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if (g_cpuConstRegs[i].SL[j] != 0)
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continue;
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if (eaxval != 0)
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XOR32RtoR(EAX, EAX), eaxval = 0;
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for (int i = 1, j = 0; i < 32; j++ && ++i, j %= 2) {
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if (!GPR_IS_CONST1(i) || g_cpuFlushedConstReg & (1<<i)) continue;
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if (g_cpuConstRegs[i].SL[j] != 0) continue;
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if (eaxval != 0) XOR32RtoR(EAX, EAX), eaxval = 0;
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MOV32RtoM((uptr)&cpuRegs.GPR.r[i].SL[j], EAX);
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done[j] |= 1<<i;
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zero_cnt++;
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@ -163,11 +204,9 @@ void _flushConstRegs()
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rewindPtr = x86Ptr;
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for (i = 1, j = 0; i < 32; j++ && ++i, j %= 2) {
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if (!GPR_IS_CONST1(i) || g_cpuFlushedConstReg & (1<<i))
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continue;
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if (g_cpuConstRegs[i].SL[j] != -1)
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continue;
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for (int i = 1, j = 0; i < 32; j++ && ++i, j %= 2) {
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if (!GPR_IS_CONST1(i) || g_cpuFlushedConstReg & (1<<i)) continue;
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if (g_cpuConstRegs[i].SL[j] != -1) continue;
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if (eaxval > 0) XOR32RtoR(EAX, EAX), eaxval = 0;
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if (eaxval == 0) NOT32R(EAX), eaxval = -1;
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@ -184,17 +223,17 @@ void _flushConstRegs()
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done[1] |= done[3];
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}
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for (i = 1; i < 32; ++i) {
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for (int i = 1; i < 32; ++i) {
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if (GPR_IS_CONST1(i)) {
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if (!(g_cpuFlushedConstReg&(1<<i))) {
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if (!(done[0] & (1<<i)))
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MOV32ItoM((uptr)&cpuRegs.GPR.r[i].UL[0], g_cpuConstRegs[i].UL[0]);
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if (!(done[1] & (1<<i)))
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MOV32ItoM((uptr)&cpuRegs.GPR.r[i].UL[1], g_cpuConstRegs[i].UL[1]);
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g_cpuFlushedConstReg |= 1<<i;
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}
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if (g_cpuHasConstReg == g_cpuFlushedConstReg)
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break;
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if (g_cpuHasConstReg == g_cpuFlushedConstReg) break;
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}
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}
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}
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@ -206,14 +245,13 @@ int _allocX86reg(int x86reg, int type, int reg, int mode)
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// don't alloc EAX and ESP,EBP if MODE_NOFRAME
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int oldmode = mode;
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int noframe = mode&MODE_NOFRAME;
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int maxreg = (mode&MODE_8BITREG)?4:iREGCNT_GPR;
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int noframe = mode & MODE_NOFRAME;
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int maxreg = (mode & MODE_8BITREG) ? 4 : iREGCNT_GPR;
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mode &= ~(MODE_NOFRAME|MODE_8BITREG);
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int readfromreg = -1;
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if( type != X86TYPE_TEMP ) {
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if( maxreg < iREGCNT_GPR ) {
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if ( type != X86TYPE_TEMP ) {
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if ( maxreg < iREGCNT_GPR ) {
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// make sure reg isn't in the higher regs
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for(i = maxreg; i < iREGCNT_GPR; ++i) {
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@ -232,8 +270,7 @@ int _allocX86reg(int x86reg, int type, int reg, int mode)
|
|||
}
|
||||
|
||||
for (i=1; i<maxreg; i++) {
|
||||
if( i == ESP ) continue;
|
||||
|
||||
if ( i == ESP ) continue;
|
||||
if (!x86regs[i].inuse || x86regs[i].type != type || x86regs[i].reg != reg) continue;
|
||||
|
||||
if( (noframe && i == EBP) || (i >= maxreg) ) {
|
||||
|
|
@ -272,12 +309,10 @@ int _allocX86reg(int x86reg, int type, int reg, int mode)
|
|||
}
|
||||
}
|
||||
|
||||
if (x86reg == -1) {
|
||||
if (x86reg == -1)
|
||||
x86reg = _getFreeX86reg(oldmode);
|
||||
}
|
||||
else {
|
||||
else
|
||||
_freeX86reg(x86reg);
|
||||
}
|
||||
|
||||
x86regs[x86reg].type = type;
|
||||
x86regs[x86reg].reg = reg;
|
||||
|
|
@ -378,6 +413,7 @@ void _deleteX86reg(int type, int reg, int flush)
|
|||
case 0:
|
||||
_freeX86reg(i);
|
||||
break;
|
||||
|
||||
case 1:
|
||||
if( x86regs[i].mode & MODE_WRITE) {
|
||||
|
||||
|
|
@ -391,6 +427,7 @@ void _deleteX86reg(int type, int reg, int flush)
|
|||
x86regs[i].mode |= MODE_READ;
|
||||
}
|
||||
return;
|
||||
|
||||
case 2:
|
||||
x86regs[i].inuse = 0;
|
||||
break;
|
||||
|
|
@ -470,7 +507,7 @@ int _getFreeMMXreg()
|
|||
// check for dead regs
|
||||
for (i=0; i<iREGCNT_MMX; i++) {
|
||||
if (mmxregs[i].needed) continue;
|
||||
if (mmxregs[i].reg >= MMX_GPR && mmxregs[i].reg < MMX_GPR+34 ) { // mmxregs[i] is unsigned, and MMX_GPR == 0, so the first part is always true.
|
||||
if (MMX_ISGPR(mmxregs[i].reg)) {
|
||||
if( !(g_pCurInstInfo->regs[mmxregs[i].reg-MMX_GPR] & (EEINST_LIVE0|EEINST_LIVE1)) ) {
|
||||
_freeMMXreg(i);
|
||||
return i;
|
||||
|
|
@ -485,7 +522,7 @@ int _getFreeMMXreg()
|
|||
// check for future xmm usage
|
||||
for (i=0; i<iREGCNT_MMX; i++) {
|
||||
if (mmxregs[i].needed) continue;
|
||||
if (mmxregs[i].reg >= MMX_GPR && mmxregs[i].reg < MMX_GPR+34 ) {
|
||||
if (MMX_ISGPR(mmxregs[i].reg)) {
|
||||
if( !(g_pCurInstInfo->regs[mmxregs[i].reg] & EEINST_MMX) ) {
|
||||
_freeMMXreg(i);
|
||||
return i;
|
||||
|
|
@ -612,7 +649,7 @@ int _checkMMXreg(int reg, int mode)
|
|||
PXORRtoR(i, i);
|
||||
}
|
||||
else {
|
||||
if( MMX_ISGPR(reg) && (mode&(MODE_READHALF|MODE_READ)) ) _flushConstReg(reg-MMX_GPR);
|
||||
if (MMX_ISGPR(reg) && (mode&(MODE_READHALF|MODE_READ))) _flushConstReg(reg-MMX_GPR);
|
||||
if( (mode & MODE_READHALF) || (MMX_IS32BITS(reg)&&(mode&MODE_READ)) )
|
||||
MOVDMtoMMX(i, (u32)_MMXGetAddr(reg));
|
||||
else
|
||||
|
|
@ -713,7 +750,7 @@ u8 _hasFreeMMXreg()
|
|||
// check for dead regs
|
||||
for (i=0; i<iREGCNT_MMX; i++) {
|
||||
if (mmxregs[i].needed) continue;
|
||||
if (mmxregs[i].reg >= MMX_GPR && mmxregs[i].reg < MMX_GPR+34 ) {
|
||||
if (MMX_ISGPR(mmxregs[i].reg)) {
|
||||
if( !EEINST_ISLIVE64(mmxregs[i].reg-MMX_GPR) ) {
|
||||
return 1;
|
||||
}
|
||||
|
|
@ -723,7 +760,7 @@ u8 _hasFreeMMXreg()
|
|||
// check for dead regs
|
||||
for (i=0; i<iREGCNT_MMX; i++) {
|
||||
if (mmxregs[i].needed) continue;
|
||||
if (mmxregs[i].reg >= MMX_GPR && mmxregs[i].reg < MMX_GPR+34 ) {
|
||||
if (MMX_ISGPR(mmxregs[i].reg)) {
|
||||
if( !(g_pCurInstInfo->regs[mmxregs[i].reg-MMX_GPR]&EEINST_USED) ) {
|
||||
return 1;
|
||||
}
|
||||
|
|
@ -739,8 +776,8 @@ void _freeMMXreg(int mmxreg)
|
|||
if (!mmxregs[mmxreg].inuse) return;
|
||||
|
||||
if (mmxregs[mmxreg].mode & MODE_WRITE ) {
|
||||
|
||||
if( mmxregs[mmxreg].reg >= MMX_GPR && mmxregs[mmxreg].reg < MMX_GPR+32 )
|
||||
// Not sure if this line is accurate, since if the 32 was 34, it would be MMX_ISGPR.
|
||||
if ( /*mmxregs[mmxreg].reg >= MMX_GPR &&*/ mmxregs[mmxreg].reg < MMX_GPR+32 ) // Checking if a u32 is >=0 is pointless.
|
||||
assert( !(g_cpuHasConstReg & (1<<(mmxregs[mmxreg].reg-MMX_GPR))) );
|
||||
|
||||
assert( mmxregs[mmxreg].reg != MMX_GPR );
|
||||
|
|
|
|||
|
|
@ -478,8 +478,6 @@ void recResetEE( void )
|
|||
__asm__("emms");
|
||||
#endif
|
||||
|
||||
#define GET_HWADDR(mem)
|
||||
|
||||
for (int i = 0; i < 0x10000; i++)
|
||||
recLUT_SetPage(recLUT, 0, 0, 0, i, 0);
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue