mirror of https://github.com/PCSX2/pcsx2.git
Fixed a bunch of silly mistakes I'm ashamed of. no the bios can actually access the memcards.
git-svn-id: http://pcsx2.googlecode.com/svn/trunk@2499 96395faa-99c1-11dd-bbfe-3dabce05a288
This commit is contained in:
gigaherz
parent
7dfaa65ef3
commit
a323d31bf3
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@ -311,32 +311,32 @@ s32 errDmaRead(s32 channel, u32* data, u32 bytesLeft, u32* bytesProcessed);
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#define MEM_BASE2 0x1f801500
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#define CHANNEL_BASE1(ch) (MEM_BASE1 + ((ch)<<4))
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#define CHANNEL_BASE2(ch) (MEM_BASE1 + ((ch)<<4))
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#define CHANNEL_BASE2(ch) (MEM_BASE2 + ((ch)<<4))
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u32& DmaHandlerInfo::REG_MADR(void) { return psxHu32(DmacRegisterBase + 0x0); }
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u32& DmaHandlerInfo::REG_BCR(void) { return psxHu32(DmacRegisterBase + 0x4); }
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u32& DmaHandlerInfo::REG_CHCR(void) { return psxHu32(DmacRegisterBase + 0xC); }
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u32& DmaHandlerInfo::REG_CHCR(void) { return psxHu32(DmacRegisterBase + 0x8); }
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u32& DmaHandlerInfo::REG_TADR(void) { return psxHu32(DmacRegisterBase + 0xC); }
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DmaHandlerInfo IopDmaHandlers[DMA_CHANNEL_MAX] =
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{
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// First DMAC, same as PS1
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{"Ps1 Mdec", CHANNEL_BASE1(0), 0}, //0
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{"Ps1 Mdec", CHANNEL_BASE1(1), 0}, //1
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{"Ps1 Gpu", CHANNEL_BASE1(2), 0}, //2
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{"CDVD", CHANNEL_BASE1(3), cdvdDmaRead, errDmaWrite, cdvdDmaInterrupt}, //3: CDVD
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{"SPU2 Core0", CHANNEL_BASE1(4), spu2DmaRead, spu2DmaWrite, spu2DmaInterrupt}, //4: Spu Core0
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{"?", CHANNEL_BASE1(5), 0}, //5
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{"OT", CHANNEL_BASE1(6), 0}, //6: OT?
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{"Ps1 Mdec", 0}, //0
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{"Ps1 Mdec", 0}, //1
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{"Ps1 Gpu", 0}, //2
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{"CDVD", 2, CHANNEL_BASE1(3), cdvdDmaRead, errDmaWrite, cdvdDmaInterrupt}, //3: CDVD
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{"SPU2 Core0", 3, CHANNEL_BASE1(4), spu2DmaRead, spu2DmaWrite, spu2DmaInterrupt}, //4: Spu Core0
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{"?", 0}, //5
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{"OT", 0}, //6: OT?
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// Second DMAC, new in PS2 IOP
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{"SPU2 Core1", CHANNEL_BASE2(0), spu2DmaRead, spu2DmaWrite, spu2DmaInterrupt}, //7: Spu Core1
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{"Dev9", CHANNEL_BASE2(1), 0},//dev9DmaRead, dev9DmaWrite, dev9DmaInterrupt}, //8: Dev9
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{"Sif0", CHANNEL_BASE2(2), 0},//sif0DmaRead, sif0DmaWrite, sif0DmaInterrupt}, //9: SIF0
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{"Sif1", CHANNEL_BASE2(3), 0},//sif1DmaRead, sif1DmaWrite, sif1DmaInterrupt}, //10: SIF1
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{"Sio2 (writes)", CHANNEL_BASE2(4), errDmaRead, sio2DmaWrite, sio2DmaInterrupt}, //11: Sio2
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{"Sio2 (reads)", CHANNEL_BASE2(5), sio2DmaRead, errDmaWrite, sio2DmaInterrupt}, //12: Sio2
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{"SPU2 Core1", 3, CHANNEL_BASE2(0), spu2DmaRead, spu2DmaWrite, spu2DmaInterrupt}, //7: Spu Core1
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{"Dev9", 0},// CHANNEL_BASE2(1), dev9DmaRead, dev9DmaWrite, dev9DmaInterrupt}, //8: Dev9
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{"Sif0", 0},// CHANNEL_BASE2(2), sif0DmaRead, sif0DmaWrite, sif0DmaInterrupt}, //9: SIF0
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{"Sif1", 0},// CHANNEL_BASE2(3), sif1DmaRead, sif1DmaWrite, sif1DmaInterrupt}, //10: SIF1
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{"Sio2 (writes)", 2, CHANNEL_BASE2(4), errDmaRead, sio2DmaWrite, sio2DmaInterrupt}, //11: Sio2
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{"Sio2 (reads)", 1, CHANNEL_BASE2(5), sio2DmaRead, errDmaWrite, sio2DmaInterrupt}, //12: Sio2
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{"?", 0}, //13
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// if each dmac has 7 channels, the list would end here, but i made it 16 cos I'm not sure :p
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{"?", 0}, //14
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@ -363,11 +363,30 @@ void IopDmaStart(int channel)
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{
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// I dont' really understand this, but it's used above. Is this BYTES OR WHAT?
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int bcr = IopDmaHandlers[channel].REG_BCR();
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int size = 4* (bcr >> 16) * (bcr & 0xFFFF);
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int bcr_size = (bcr & 0xFFFF);
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int bcr_count = (bcr >> 16);
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int size = 4* bcr_count * bcr_size;
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int chcr = IopDmaHandlers[channel].REG_CHCR();
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int dirf = IopDmaHandlers[channel].DirectionFlags&3;
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if(dirf != 3)
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{
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bool ok = (chcr & DMA_CTRL_DIRECTION)? (dirf==2) : (dirf==1);
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if(!ok)
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{
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// hack?!
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IopDmaHandlers[channel].REG_CHCR() &= ~DMA_CTRL_ACTIVE;
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return;
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}
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}
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Console.WriteLn(Color_StrongOrange,"Starting NewDMA ch=%d, size=%d dir=%d", channel, size, chcr&DMA_CTRL_DIRECTION);
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IopDmaHandlers[channel].REG_CHCR() |= DMA_CTRL_ACTIVE;
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IopDmaHandlers[channel].ByteCount = size;
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IopDmaHandlers[channel].Target=0;
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IopDmaHandlers[channel].Target = 0;
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IopDmaHandlers[channel].Activated = true;
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//SetDmaUpdateTarget(1);
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{
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@ -386,6 +405,7 @@ void IopDmaUpdate(u32 elapsed)
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{
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s32 MinDelay=0;
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int doNotHang=10;
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do {
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MinDelay = 0x7FFFFFFF;
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@ -393,7 +413,7 @@ void IopDmaUpdate(u32 elapsed)
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{
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DmaHandlerInfo *ch = IopDmaHandlers + i;
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if (ch->REG_CHCR()&DMA_CTRL_ACTIVE)
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if ((ch->Activated) && (ch->REG_CHCR()&DMA_CTRL_ACTIVE))
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{
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ch->Target -= elapsed;
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if (ch->Target <= 0)
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@ -408,7 +428,9 @@ void IopDmaUpdate(u32 elapsed)
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}
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else
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{
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DmaHandler handler = (ch->REG_CHCR() & DMA_CTRL_DIRECTION) ? IopDmaHandlers[i].Write : IopDmaHandlers[i].Read;
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int chcr = ch->REG_CHCR();
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DmaHandler handler = (chcr & DMA_CTRL_DIRECTION) ? IopDmaHandlers[i].Write : IopDmaHandlers[i].Read;
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u32 BCount = 0;
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s32 Target = (handler) ? handler(i, (u32*)iopPhysMem(ch->REG_MADR()), ch->ByteCount, &BCount) : 0;
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@ -422,6 +444,9 @@ void IopDmaUpdate(u32 elapsed)
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if (Target < 0)
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{
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// TODO: ... What to do if the handler gives an error code? :P
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ch->REG_CHCR() &= ~DMA_CTRL_ACTIVE;
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RaiseDmaIrq(i);
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IopDmaHandlers[i].Interrupt(i);
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}
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else if (BCount > 0)
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{
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@ -453,7 +478,7 @@ void IopDmaUpdate(u32 elapsed)
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}
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elapsed=0;
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}
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while(MinDelay <= 0);
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while(MinDelay <= 0 && (doNotHang-->0));
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if(MinDelay<0x7FFFFFFF)
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SetDmaUpdateTarget(MinDelay);
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@ -463,7 +488,7 @@ void IopDmaUpdate(u32 elapsed)
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s32 errDmaRead(s32 channel, u32* data, u32 bytesLeft, u32* bytesProcessed)
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{
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Console.Error("ERROR: Tried to read using DMA %d (%s). Ignoring.", 0, channel, IopDmaHandlers[channel]);
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Console.Error("ERROR: Tried to read using DMA %d (%s). Ignoring.", channel, IopDmaHandlers[channel]);
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*bytesProcessed = bytesLeft;
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return 0;
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@ -471,7 +496,7 @@ s32 errDmaRead(s32 channel, u32* data, u32 bytesLeft, u32* bytesProcessed)
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s32 errDmaWrite(s32 channel, u32* data, u32 bytesLeft, u32* bytesProcessed)
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{
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Console.Error("ERROR: Tried to write using DMA %d (%s). Ignoring.", 0, channel, IopDmaHandlers[channel]);
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Console.Error("ERROR: Tried to write using DMA %d (%s). Ignoring.", channel, IopDmaHandlers[channel]);
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*bytesProcessed = bytesLeft;
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return 0;
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@ -29,18 +29,23 @@ class DmaHandlerInfo
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{
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public:
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const char* Name;
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u32 DirectionFlags;
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u32 DmacRegisterBase;
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DmaHandler Read;
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DmaHandler Write;
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DmaIHandler Interrupt;
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// runtime variables
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bool Activated; // this is turned on when the channel is first handled,
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// and serves as a signal that the channel shoudl be handled by the loop.
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// temporary until I code a better method
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u32 ByteCount;
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u32 Target;
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s32 Target;
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u32& REG_MADR(void);
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u32& REG_BCR(void);
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u32& REG_CHCR(void);
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u32& REG_TADR(void);
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};
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// FIXME: Dummy constants, to be "filled in" with proper values later
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@ -231,11 +231,13 @@ s32 sio2DmaRead(s32 channel, u32* tdata, u32 bytesLeft, u32* bytesProcessed)
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read++;
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if(sio2.recvIndex == sio2.packet.sendSize)
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{
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PSX_INT(IopEvt_Dma12,read/2); // Interrupts should always occur at the end
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//read = bytesLeft;
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break;
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}
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}
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//PSX_INT(IopEvt_Dma12,read/2); // Interrupts should always occur at the end
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*bytesProcessed = read;
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#endif
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return 0;
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@ -258,13 +260,15 @@ s32 sio2DmaWrite(s32 channel, u32* tdata, u32 bytesLeft, u32* bytesProcessed)
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sio.count = 1;
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sio2_fifoIn(*(data++));
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written++;
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if(sio2.packet.sendSize == BUFSIZE)
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if((sio2.packet.sendSize == BUFSIZE))
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{
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PSX_INT(IopEvt_Dma11,written/2); // Interrupts should always occur at the end
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//written = bytesLeft;
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break;
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}
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}
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//PSX_INT(IopEvt_Dma11,written/2); // Interrupts should always occur at the end
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*bytesProcessed = written;
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#endif
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return 0;
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