diff --git a/pcsx2/x86/ix86-32/iR5900LoadStore.cpp b/pcsx2/x86/ix86-32/iR5900LoadStore.cpp
index 53d5653475..58a152b3ba 100644
--- a/pcsx2/x86/ix86-32/iR5900LoadStore.cpp
+++ b/pcsx2/x86/ix86-32/iR5900LoadStore.cpp
@@ -939,7 +939,7 @@ void recLQC2()
 
 	if (GPR_IS_CONST1(_Rs_))
 	{
-		int addr = g_cpuConstRegs[_Rs_].UL[0] + _Imm_;
+		const u32 addr = (g_cpuConstRegs[_Rs_].UL[0] + _Imm_) & ~0xFu;
 
 		gpr = vtlb_DynGenReadQuad_Const(128, addr, -1);
 	}
@@ -948,6 +948,7 @@ void recLQC2()
 		_eeMoveGPRtoR(arg1regd, _Rs_);
 		if (_Imm_ != 0)
 			xADD(arg1regd, _Imm_);
+		xAND(arg1regd, ~0xF);
 
 		iFlushCall(FLUSH_FULLVTLB);
 
@@ -991,7 +992,7 @@ void recSQC2()
 
 	if (GPR_IS_CONST1(_Rs_))
 	{
-		int addr = g_cpuConstRegs[_Rs_].UL[0] + _Imm_;
+		const u32 addr = (g_cpuConstRegs[_Rs_].UL[0] + _Imm_) & ~0xFu;
 		vtlb_DynGenWrite_Const(128, addr);
 	}
 	else
@@ -999,6 +1000,7 @@ void recSQC2()
 		_eeMoveGPRtoR(arg1regd, _Rs_);
 		if (_Imm_ != 0)
 			xADD(arg1regd, _Imm_);
+		xAND(arg1regd, ~0xF);
 
 		iFlushCall(FLUSH_FULLVTLB);