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PGIF: Remove force fifo clear on GP1 (00-01) 

Clearing GP0 fifo is handled internally in PS1DRV.

This commit additionally remove annoying log from devbuilds.
This commit is contained in:
kozarovv 2021-09-29 09:10:36 +02:00 committed by Kojin
parent 2241e635c6
commit a09a6db24d
2 changed files with 3 additions and 10 deletions
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2
pcsx2/ps2/Iop/IopHwRead.cpp
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@ -310,8 +310,6 @@ static __fi T _HwRead_16or32_Page1( u32 addr )
mcase(HW_PS1_GPU_DATA) : mcase(HW_PS1_GPU_DATA) :
ret = psxGPUr(addr); ret = psxGPUr(addr);
//ret = psxHu32(addr); // old
DevCon.Warning("GPU Data Read %x", ret);
break; break;
mcase(HW_PS1_GPU_STATUS) : mcase(HW_PS1_GPU_STATUS) :

11
pcsx2/ps2/pgif.cpp
View File

@ -233,17 +233,10 @@ u32 immRespHndl(u32 cmd, u32 data)
void handleGp1Command(u32 cmd) void handleGp1Command(u32 cmd)
{ {
//Check GP1() command and configure PGIF accordingly. //Check GP1() command and configure PGIF accordingly.
//Commands 0x00 - 0x01 are partially handled in ps1drv, we should just clear fifo. //Commands 0x00 - 0x01, 0x03, 0x05 - 0x08 are fully handled in ps1drv.
const u32 cmdNr = ((cmd >> 24) & 0xFF) & 0x3F; const u32 cmdNr = ((cmd >> 24) & 0xFF) & 0x3F;
switch (cmdNr) switch (cmdNr)
{ {
case 0:
// Pgpu reset, mostly handled by ps1drv (00201D64 in ps1drv). Comment for case 1 apply here too.
ringBufferClear(&rb_gp0);
break;
case 1: //Reset GP0 fifo, seems to check that something is empty, so maybe we should do the same before clear?
ringBufferClear(&rb_gp0);
break;
case 2: //Acknowledge GPU IRQ case 2: //Acknowledge GPU IRQ
ackGpuIrq1(); ackGpuIrq1();
break; break;
@ -274,6 +267,8 @@ void handleGp1Command(u32 cmd)
break; break;
} }
break; break;
default:
break;
} }
} }