From a09a6db24ddc9c03657985393e050995bd5b7d78 Mon Sep 17 00:00:00 2001 From: kozarovv <15552250+kozarovv@users.noreply.github.com> Date: Wed, 29 Sep 2021 09:10:36 +0200 Subject: [PATCH] PGIF: Remove force fifo clear on GP1 (00-01) Clearing GP0 fifo is handled internally in PS1DRV. This commit additionally remove annoying log from devbuilds. --- pcsx2/ps2/Iop/IopHwRead.cpp | 2 -- pcsx2/ps2/pgif.cpp | 11 +++-------- 2 files changed, 3 insertions(+), 10 deletions(-) diff --git a/pcsx2/ps2/Iop/IopHwRead.cpp b/pcsx2/ps2/Iop/IopHwRead.cpp index d1e0243678..00be2e5b9e 100644 --- a/pcsx2/ps2/Iop/IopHwRead.cpp +++ b/pcsx2/ps2/Iop/IopHwRead.cpp @@ -310,8 +310,6 @@ static __fi T _HwRead_16or32_Page1( u32 addr ) mcase(HW_PS1_GPU_DATA) : ret = psxGPUr(addr); - //ret = psxHu32(addr); // old - DevCon.Warning("GPU Data Read %x", ret); break; mcase(HW_PS1_GPU_STATUS) : diff --git a/pcsx2/ps2/pgif.cpp b/pcsx2/ps2/pgif.cpp index 442e081ce4..64be6abd2c 100644 --- a/pcsx2/ps2/pgif.cpp +++ b/pcsx2/ps2/pgif.cpp @@ -233,17 +233,10 @@ u32 immRespHndl(u32 cmd, u32 data) void handleGp1Command(u32 cmd) { //Check GP1() command and configure PGIF accordingly. - //Commands 0x00 - 0x01 are partially handled in ps1drv, we should just clear fifo. + //Commands 0x00 - 0x01, 0x03, 0x05 - 0x08 are fully handled in ps1drv. const u32 cmdNr = ((cmd >> 24) & 0xFF) & 0x3F; switch (cmdNr) { - case 0: - // Pgpu reset, mostly handled by ps1drv (00201D64 in ps1drv). Comment for case 1 apply here too. - ringBufferClear(&rb_gp0); - break; - case 1: //Reset GP0 fifo, seems to check that something is empty, so maybe we should do the same before clear? - ringBufferClear(&rb_gp0); - break; case 2: //Acknowledge GPU IRQ ackGpuIrq1(); break; @@ -274,6 +267,8 @@ void handleGp1Command(u32 cmd) break; } break; + default: + break; } }