mirror of https://github.com/PCSX2/pcsx2.git
SPU2Ghz: Had to revert dma.cpp to rev244 for the most part. The dma cache system in DoDMAWrite() broke Arc the Lad dma audio. The auido starts to loop a bit in rev 264 and from there on it gets worse.
Sorry for not finding this earlier, I hope the cache can get fixed so we can include it again. git-svn-id: http://pcsx2-playground.googlecode.com/svn/trunk@333 a6443dda-0b58-4228-96e9-037be469359c
This commit is contained in:
ramapcsx2
Gregory Hainaut
parent
d0c0b20505
commit
7e828a69ee
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@ -92,9 +92,9 @@ void DMALogClose() {
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__forceinline u16 DmaRead(u32 core)
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{
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Cores[core].TDA&=0xfffff;
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const u16 ret = (u16)spu2M_Read(Cores[core].TDA);
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Cores[core].TDA++;
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Cores[core].TDA&=0xfffff;
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return ret;
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}
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@ -189,6 +189,8 @@ void StartADMAWrite(int core,u16 *pMem, u32 sz)
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void DoDMAWrite(int core,u16 *pMem,u32 size)
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{
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u32 i;
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{
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// Perform an alignment check.
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// Not really important. Everything should work regardless,
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@ -216,102 +218,52 @@ void DoDMAWrite(int core,u16 *pMem,u32 size)
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if(MsgDMA()) ConLog(" * SPU2: DMA%c Transfer of %d bytes to %x (%02x %x %04x).\n",(core==0)?'4':'7',size<<1,Cores[core].TSA,Cores[core].DMABits,Cores[core].AutoDMACtrl,(~Cores[core].Regs.ATTR)&0x7fff);
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// split the DMA copy into two chunks if needed.
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// Optimized!
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// Instead of checking the adpcm cache for every word, we check for every block.
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// That way we can use the optimized fast write instruction to commit the memory.
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Cores[core].TDA = Cores[core].TSA & 0xfffff;
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u32 buff1end = Cores[core].TDA + size;
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s32 buff2end = buff1end - 0xfffff;
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if( buff2end > 0 )
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buff1end = 0xfffff;
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{
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u32 nexta = Cores[core].TDA >> 3; // next address in 8 word blocks
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const u32 leftsidebit = nexta & 31;
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u32 rightsidebit; // assigned later
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u32 nexta = Cores[core].TDA >> 3;
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u32 flagbitmask = 1ul << ( nexta & 31 );
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nexta >>= 5;
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// Left side remainder:
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// this produces a bitmask of the left side remainder of the cache flags:
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pcm_cache_flags[nexta] &= (1ul << leftsidebit)-1;
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// middle run!
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// Traverse from start to finish in 8*32 word blocks,
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// and clear all the the pcm cache flags for each block.
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const u32 buff1size = (buff1end-Cores[core].TDA);
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memcpy( GetMemPtr( Cores[core].TDA ), pMem, buff1size*2 );
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//for(; Cores[core].TDA<buff1end; ++Cores[core].TDA, ++pMem)
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// *GetMemPtr( Cores[core].TDA ) = *pMem;
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buff1end >>= (3+5); // 8 words per block, 32 blocks per int.
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memset( &pcm_cache_flags[nexta], 0, sizeof( u32 ) * (buff1end-nexta) );
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if( buff2end > 0 )
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// Traverse from start to finish in 8 word blocks,
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// and clear the pcm cache flag for each block.
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u32 stmp = ( size + 7 ) >> 3; // round up
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for( i=0; i<stmp; i++ )
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{
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// second branch needs cleared:
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// It starts at the beginning of memory and moves forward to buff2end
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const u32 endpt2 = buff2end >> (3+5); // 8 words per block, 32 blocks per int.
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memset( pcm_cache_flags, 0, sizeof( u32 ) * endpt2 );
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memcpy( GetMemPtr( 0 ), &pMem[buff1size], buff2end*2 );
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//for(Cores[core].TDA=0; Cores[core].TDA<(u32)buff2end; ++Cores[core].TDA, ++pMem)
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// *GetMemPtr( Cores[core].TDA ) = *pMem;
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rightsidebit = buff2end >> 3;
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nexta = endpt2;
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if(Cores[core].IRQEnable)
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pcm_cache_flags[nexta] &= ~flagbitmask;
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flagbitmask <<= 1;
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if( flagbitmask == 0 )
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{
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// Flag interrupt?
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// If IRQA occurs between start and dest, flag it.
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// Since the buffer wraps, the conditional might seem odd, but it works.
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if( ( Cores[core].IRQA >= Cores[core].TDA ) ||
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( Cores[core].IRQA <= (u32)buff2end ) )
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{
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Spdif.Info=4<<core;
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SetIrqCall();
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}
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}
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Cores[core].TDA = buff2end;
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}
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else
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{
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rightsidebit = buff1end >> 3;
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nexta = buff1end;
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Cores[core].TDA = buff1end;
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if(Cores[core].IRQEnable)
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{
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// Flag interrupt?
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// If IRQA occurs between start and dest, flag it:
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if( ( Cores[core].IRQA >= Cores[core].TSA ) &&
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( Cores[core].IRQA <= Cores[core].TDA ) )
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{
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Spdif.Info=4<<core;
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SetIrqCall();
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}
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nexta++;
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flagbitmask = 1;
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}
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}
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// clear the right-side remainder:
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pcm_cache_flags[nexta] &= ~((1ul << (32-(rightsidebit&31)))-1);
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}
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//Cores[core].TDA=Cores[core].TSA+size;
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for(i=0;i<size;i++)
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{
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*GetMemPtr( Cores[core].TDA ) = pMem[i];
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//spu2M_Write( Cores[core].TDA, pMem[i] );
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Cores[core].TDA++;
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Cores[core].TDA&=0xfffff;
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}
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i=Cores[core].TSA;
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Cores[core].TDA=Cores[core].TSA+size;
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if((Cores[core].TDA>0xFFFFF)||((Cores[core].TDA>=Cores[core].IRQA)&&(i<=Cores[core].IRQA))) {
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if(Cores[core].IRQEnable)
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{
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Spdif.Info=4<<core;
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SetIrqCall();
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}
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}
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Cores[core].TSA=Cores[core].TDA&0xFFFF0;
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Cores[core].DMAICounter=size;
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Cores[core].TADR=Cores[core].MADR+(size<<1);
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}
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void SPU2readDMA(int core, u16* pMem, u32 size)
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@ -369,6 +321,7 @@ void SPU2writeDMA(int core, u16* pMem, u32 size)
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}
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else
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{
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DoDMAWrite(core,pMem,size);
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}
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Cores[core].Regs.STATX &= ~0x80;
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@ -429,4 +382,3 @@ void CALLBACK SPU2interruptDMA7() {
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Cores[1].Regs.STATX |= 0x80;
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//Cores[1].Regs.ATTR &= ~0x30;
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}
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