mirror of https://github.com/PCSX2/pcsx2.git
Turn a few defines into inlined functions, and remove a few unneeded comments.
git-svn-id: http://pcsx2-playground.googlecode.com/svn/trunk@331 a6443dda-0b58-4228-96e9-037be469359c
This commit is contained in:
arcum42
Gregory Hainaut
parent
2ecf6d1372
commit
8a9aafdee7
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@ -1284,13 +1284,6 @@ extern "C" void cpudetectSSE3(void* pfnCallSSE3)
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// exception handling doesn't work, so disable for x86 builds of linux
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cpucaps.hasStreamingSIMD3Extensions = 0;
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#endif
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// try {
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// __asm__("call *%0" : : "m"(pfnCallSSE3) );
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// }
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// catch(...) {
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// SysPrintf("no SSE3 found\n");
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// cpucaps.hasStreamingSIMD3Extensions = 0;
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// }
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#endif
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}
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@ -1314,13 +1307,6 @@ return;
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// exception handling doesn't work, so disable for x86 builds of linux
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cpucaps.hasStreamingSIMD4Extensions = 0;
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#endif
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// try {
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// __asm__("call *%0" : : "m"(pfnCallSSE4) );
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// }
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// catch(...) {
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// SysPrintf("no SSE4.1 found\n");
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// cpucaps.hasStreamingSIMD4Extensions = 0;
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// }
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#endif
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}
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@ -61,7 +61,6 @@ void psx##f(); \
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static void rpsx##f() { \
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MOV32ItoM((uptr)&psxRegs.code, (u32)psxRegs.code); \
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_psxFlushCall(FLUSH_EVERYTHING); \
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/*MOV32ItoM((u32)&psxRegs.pc, (u32)pc);*/ \
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CALLFunc((uptr)psx##f); \
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PSX_DEL_CONST(_Rt_); \
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/* branch = 2; */\
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@ -634,11 +633,11 @@ int _psxPrepareReg(int gprreg)
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static u32 s_nAddMemOffset = 0;
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#define SET_HWLOC() { \
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x86SetJ8(j8Ptr[0]); \
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SHR32ItoR(ECX, 3); \
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if( s_nAddMemOffset ) ADD32ItoR(ECX, s_nAddMemOffset); \
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} \
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static __forceinline void SET_HWLOC() {
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x86SetJ8(j8Ptr[0]);
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SHR32ItoR(ECX, 3);
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if( s_nAddMemOffset ) ADD32ItoR(ECX, s_nAddMemOffset);
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}
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int rpsxSetMemLocation(int regs, int mmreg)
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{
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@ -49,7 +49,7 @@ extern _GSgifTransfer1 GSgifTransfer1;
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#ifdef PCSX2_DEVBUILD
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// These would amke more sense in GS.cpp, but then the legacy "C" files
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// These would make more sense in GS.cpp, but then the legacy "C" files
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// (like this one!) wouldn't be able to access them (C++ name mangling)
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__forceinline void GSGIFTRANSFER1(u32 *pMem, u32 addr) {
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@ -257,20 +257,13 @@ void VU_MERGE15(int dest, int src) { // 1111s
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}
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typedef void (*VUMERGEFN)(int dest, int src);
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static VUMERGEFN s_VuMerge[16] = {
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VU_MERGE0, VU_MERGE1, VU_MERGE2, VU_MERGE3,
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VU_MERGE4, VU_MERGE5, VU_MERGE6, VU_MERGE7,
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VU_MERGE8, VU_MERGE9, VU_MERGE10, VU_MERGE11,
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VU_MERGE12, VU_MERGE13, VU_MERGE14, VU_MERGE15 };
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/*
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#define VU_MERGE_REGS(dest, src) { \
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if( dest != src ) s_VuMerge[_X_Y_Z_W](dest, src); \
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} \
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#define VU_MERGE_REGS_CUSTOM(dest, src, xyzw) { \
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if( dest != src ) s_VuMerge[xyzw](dest, src); \
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} \
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*/
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void VU_MERGE_REGS_CUSTOM(int dest, int src, int xyzw)
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{
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xyzw &= 0xf;
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@ -1037,18 +1030,7 @@ int _vuGetTempXMMreg(int info)
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if( _hasFreeXMMreg() ) {
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t1reg = _allocTempXMMreg(XMMT_FPS, -1);
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/*
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if( t1reg == EEREC_TEMP && _hasFreeXMMreg() ) {
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int t = _allocTempXMMreg(XMMT_FPS, -1);
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_freeXMMreg(t1reg);
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t1reg = t;
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_freeXMMreg(t1reg);
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}
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else {
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_freeXMMreg(t1reg);
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t1reg = -1;
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}
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*/
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if( t1reg == EEREC_TEMP ) {
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if( _hasFreeXMMreg() ) {
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int t = _allocTempXMMreg(XMMT_FPS, -1);
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@ -5642,20 +5624,14 @@ void VU1XGKICK_MTGSTransfer(u32 *pMem, u32 addr)
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size = 0x4000-(size<<4)-(addr&0x3fff);
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assert( size >= 0 );
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// can't exceed 0x4000
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// left = addr+size-0x4000;
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// if( left > 0 ) size -= left;
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if( size > 0 ) {
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pmem = GSRingBufCopy(NULL, size, GS_RINGTYPE_P1);
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assert( pmem != NULL );
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FreezeMMXRegs(1);
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memcpy_fast(pmem, (u8*)pMem+addr, size);
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FreezeMMXRegs(0);
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// if( left > 0 ) {
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// memcpy_fast(pmem+size-left, (u8*)pMem, left);
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// }
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GSRINGBUF_DONECOPY(pmem, size);
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if( !CHECK_DUALCORE ) {
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@ -160,18 +160,29 @@ void testaddrs()
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}
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#endif
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#define SET_HWLOC() { \
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if( s_bCachingMem & 2 ) x86SetJ32(j32Ptr[2]); \
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else x86SetJ8(j8Ptr[0]); \
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if( s_bCachingMem & 2 ) x86SetJ32(j32Ptr[3]); \
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else x86SetJ8(j8Ptr[3]); \
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if (x86FpuState==MMX_STATE) { \
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if (cpucaps.has3DNOWInstructionExtensions) FEMMS(); \
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else EMMS(); \
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} \
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if( s_nAddMemOffset ) ADD32ItoR(ECX, s_nAddMemOffset); \
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if( s_bCachingMem & 4 ) AND32ItoR(ECX, 0x5fffffff); \
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} \
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static __forceinline void SET_HWLOC() {
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if ( s_bCachingMem & 2 )
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{
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x86SetJ32(j32Ptr[2]);
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x86SetJ32(j32Ptr[3]);
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}
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else
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{
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x86SetJ8(j8Ptr[0]);
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x86SetJ8(j8Ptr[3]);
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}
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if (x86FpuState==MMX_STATE) {
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if (cpucaps.has3DNOWInstructionExtensions)
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FEMMS();
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else
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EMMS();
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}
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if( s_nAddMemOffset )
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ADD32ItoR(ECX, s_nAddMemOffset);
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if( s_bCachingMem & 4 )
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AND32ItoR(ECX, 0x5fffffff);
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}
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static u16 g_MemMasks0[16] = {0x00f0, 0x80f1, 0x00f2, 0x00f3,
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0x00f1, 0x00f5, 0x00f1, 0x00f5,
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@ -1223,7 +1223,7 @@ _inline void ADD16ItoR( x86IntRegType to, u16 from )
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{
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write8( 0x83 );
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ModRM( 3, 0, to );
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write8( from );
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write8((u8)from );
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}
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else
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{
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@ -1242,7 +1242,7 @@ _inline void ADD16ItoM( uptr to, u16 from )
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write8( 0x83 );
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ModRM( 0, 0, DISP32 );
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write32( MEMADDR(to, 6) );
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write8( from );
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write8((u8)from );
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}
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else
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{
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@ -2432,7 +2432,7 @@ _inline void AND16ItoR( x86IntRegType to, u16 from )
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else if ( from < 0x80 ) {
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write8( 0x83 );
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ModRM( 3, 0x4, to );
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write8( from );
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write8((u8)from );
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}
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else {
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write8( 0x81 );
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@ -2449,7 +2449,7 @@ _inline void AND16ItoM( uptr to, u16 from )
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write8( 0x83 );
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ModRM( 0, 0x4, DISP32 );
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write32( MEMADDR(to, 6) );
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write8( from );
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write8((u8)from );
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}
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else
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{
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@ -239,9 +239,9 @@ extern u32 *j32Ptr[32];
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#define RexRXB(w, reg, index, base) if( w||(reg) >= 8 || (index) >= 8 || (base) >= 8 ) assert(0);
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#endif
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extern void write8( int val );
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extern void write16( int val );
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extern void write32( u32 val );
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extern __forceinline void write8( u8 val );
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extern __forceinline void write16( u16 val );
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extern __forceinline void write32( u32 val );
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extern void write64( u64 val );
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@ -1787,32 +1787,32 @@ extern void SSE2EMU_MOVD_R_to_XMM( x86SSERegType to, x86IntRegType from );
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#define WRITECHECK()
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#endif
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#define write8(val ) { \
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*(u8*)x86Ptr = (u8)val; \
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x86Ptr++; \
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} \
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__forceinline void write8(u8 val ) {
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*(u8*)x86Ptr = (u8)val;
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x86Ptr++;
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}
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#define write16(val ) \
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{ \
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*(u16*)x86Ptr = (u16)val; \
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x86Ptr += 2; \
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} \
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__forceinline void write16(u16 val )
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{
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*(u16*)x86Ptr = (u16)val;
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x86Ptr += 2;
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}
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#define write24(val ) \
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{ \
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*(u8*)x86Ptr = (u8)(val & 0xff); \
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x86Ptr++; \
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*(u8*)x86Ptr = (u8)((val >> 8) & 0xff); \
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x86Ptr++; \
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*(u8*)x86Ptr = (u8)((val >> 16) & 0xff); \
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x86Ptr++; \
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} \
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__forceinline void write24(u32 val )
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{
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*(u8*)x86Ptr = (u8)(val & 0xff);
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x86Ptr++;
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*(u8*)x86Ptr = (u8)((val >> 8) & 0xff);
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x86Ptr++;
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*(u8*)x86Ptr = (u8)((val >> 16) & 0xff);
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x86Ptr++;
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}
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#define write32( val ) \
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{ \
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*(u32*)x86Ptr = val; \
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x86Ptr += 4; \
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} \
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__forceinline void write32(u32 val )
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{
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*(u32*)x86Ptr = val;
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x86Ptr += 4;
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}
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#ifdef __cplusplus
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}
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