From 8a9aafdee71e97982f456eed7a13ca2b48b075f6 Mon Sep 17 00:00:00 2001 From: arcum42 Date: Sat, 15 Nov 2008 16:37:37 +0000 Subject: [PATCH] Turn a few defines into inlined functions, and remove a few unneeded comments. git-svn-id: http://pcsx2-playground.googlecode.com/svn/trunk@331 a6443dda-0b58-4228-96e9-037be469359c --- pcsx2/x86/iCore.cpp | 14 -------- pcsx2/x86/iR3000Atables.cpp | 11 +++--- pcsx2/x86/iVUmicro.c | 34 +++---------------- pcsx2/x86/ix86-32/iR5900LoadStore.c | 35 ++++++++++++------- pcsx2/x86/ix86/ix86.c | 8 ++--- pcsx2/x86/ix86/ix86.h | 52 ++++++++++++++--------------- 6 files changed, 63 insertions(+), 91 deletions(-) diff --git a/pcsx2/x86/iCore.cpp b/pcsx2/x86/iCore.cpp index 265bce9551..15a1ea158a 100644 --- a/pcsx2/x86/iCore.cpp +++ b/pcsx2/x86/iCore.cpp @@ -1284,13 +1284,6 @@ extern "C" void cpudetectSSE3(void* pfnCallSSE3) // exception handling doesn't work, so disable for x86 builds of linux cpucaps.hasStreamingSIMD3Extensions = 0; #endif -// try { -// __asm__("call *%0" : : "m"(pfnCallSSE3) ); -// } -// catch(...) { -// SysPrintf("no SSE3 found\n"); -// cpucaps.hasStreamingSIMD3Extensions = 0; -// } #endif } @@ -1314,13 +1307,6 @@ return; // exception handling doesn't work, so disable for x86 builds of linux cpucaps.hasStreamingSIMD4Extensions = 0; #endif -// try { -// __asm__("call *%0" : : "m"(pfnCallSSE4) ); -// } -// catch(...) { -// SysPrintf("no SSE4.1 found\n"); -// cpucaps.hasStreamingSIMD4Extensions = 0; -// } #endif } diff --git a/pcsx2/x86/iR3000Atables.cpp b/pcsx2/x86/iR3000Atables.cpp index 572b4353fa..7012afd5be 100644 --- a/pcsx2/x86/iR3000Atables.cpp +++ b/pcsx2/x86/iR3000Atables.cpp @@ -61,7 +61,6 @@ void psx##f(); \ static void rpsx##f() { \ MOV32ItoM((uptr)&psxRegs.code, (u32)psxRegs.code); \ _psxFlushCall(FLUSH_EVERYTHING); \ - /*MOV32ItoM((u32)&psxRegs.pc, (u32)pc);*/ \ CALLFunc((uptr)psx##f); \ PSX_DEL_CONST(_Rt_); \ /* branch = 2; */\ @@ -634,11 +633,11 @@ int _psxPrepareReg(int gprreg) static u32 s_nAddMemOffset = 0; -#define SET_HWLOC() { \ - x86SetJ8(j8Ptr[0]); \ - SHR32ItoR(ECX, 3); \ - if( s_nAddMemOffset ) ADD32ItoR(ECX, s_nAddMemOffset); \ -} \ +static __forceinline void SET_HWLOC() { + x86SetJ8(j8Ptr[0]); + SHR32ItoR(ECX, 3); + if( s_nAddMemOffset ) ADD32ItoR(ECX, s_nAddMemOffset); +} int rpsxSetMemLocation(int regs, int mmreg) { diff --git a/pcsx2/x86/iVUmicro.c b/pcsx2/x86/iVUmicro.c index c270aec30d..ed530ca4a4 100644 --- a/pcsx2/x86/iVUmicro.c +++ b/pcsx2/x86/iVUmicro.c @@ -49,7 +49,7 @@ extern _GSgifTransfer1 GSgifTransfer1; #ifdef PCSX2_DEVBUILD -// These would amke more sense in GS.cpp, but then the legacy "C" files +// These would make more sense in GS.cpp, but then the legacy "C" files // (like this one!) wouldn't be able to access them (C++ name mangling) __forceinline void GSGIFTRANSFER1(u32 *pMem, u32 addr) { @@ -257,20 +257,13 @@ void VU_MERGE15(int dest, int src) { // 1111s } typedef void (*VUMERGEFN)(int dest, int src); + static VUMERGEFN s_VuMerge[16] = { VU_MERGE0, VU_MERGE1, VU_MERGE2, VU_MERGE3, VU_MERGE4, VU_MERGE5, VU_MERGE6, VU_MERGE7, VU_MERGE8, VU_MERGE9, VU_MERGE10, VU_MERGE11, VU_MERGE12, VU_MERGE13, VU_MERGE14, VU_MERGE15 }; -/* -#define VU_MERGE_REGS(dest, src) { \ - if( dest != src ) s_VuMerge[_X_Y_Z_W](dest, src); \ -} \ -#define VU_MERGE_REGS_CUSTOM(dest, src, xyzw) { \ - if( dest != src ) s_VuMerge[xyzw](dest, src); \ -} \ -*/ void VU_MERGE_REGS_CUSTOM(int dest, int src, int xyzw) { xyzw &= 0xf; @@ -1037,18 +1030,7 @@ int _vuGetTempXMMreg(int info) if( _hasFreeXMMreg() ) { t1reg = _allocTempXMMreg(XMMT_FPS, -1); - /* - if( t1reg == EEREC_TEMP && _hasFreeXMMreg() ) { - int t = _allocTempXMMreg(XMMT_FPS, -1); - _freeXMMreg(t1reg); - t1reg = t; - _freeXMMreg(t1reg); - } - else { - _freeXMMreg(t1reg); - t1reg = -1; - } - */ + if( t1reg == EEREC_TEMP ) { if( _hasFreeXMMreg() ) { int t = _allocTempXMMreg(XMMT_FPS, -1); @@ -5642,20 +5624,14 @@ void VU1XGKICK_MTGSTransfer(u32 *pMem, u32 addr) size = 0x4000-(size<<4)-(addr&0x3fff); assert( size >= 0 ); - - // can't exceed 0x4000 -// left = addr+size-0x4000; -// if( left > 0 ) size -= left; + if( size > 0 ) { - pmem = GSRingBufCopy(NULL, size, GS_RINGTYPE_P1); assert( pmem != NULL ); FreezeMMXRegs(1); memcpy_fast(pmem, (u8*)pMem+addr, size); FreezeMMXRegs(0); - // if( left > 0 ) { - // memcpy_fast(pmem+size-left, (u8*)pMem, left); - // } + GSRINGBUF_DONECOPY(pmem, size); if( !CHECK_DUALCORE ) { diff --git a/pcsx2/x86/ix86-32/iR5900LoadStore.c b/pcsx2/x86/ix86-32/iR5900LoadStore.c index 925e4a4c9a..ec31e88dcc 100644 --- a/pcsx2/x86/ix86-32/iR5900LoadStore.c +++ b/pcsx2/x86/ix86-32/iR5900LoadStore.c @@ -160,18 +160,29 @@ void testaddrs() } #endif -#define SET_HWLOC() { \ - if( s_bCachingMem & 2 ) x86SetJ32(j32Ptr[2]); \ - else x86SetJ8(j8Ptr[0]); \ - if( s_bCachingMem & 2 ) x86SetJ32(j32Ptr[3]); \ - else x86SetJ8(j8Ptr[3]); \ - if (x86FpuState==MMX_STATE) { \ - if (cpucaps.has3DNOWInstructionExtensions) FEMMS(); \ - else EMMS(); \ - } \ - if( s_nAddMemOffset ) ADD32ItoR(ECX, s_nAddMemOffset); \ - if( s_bCachingMem & 4 ) AND32ItoR(ECX, 0x5fffffff); \ -} \ +static __forceinline void SET_HWLOC() { + if ( s_bCachingMem & 2 ) + { + x86SetJ32(j32Ptr[2]); + x86SetJ32(j32Ptr[3]); + } + else + { + x86SetJ8(j8Ptr[0]); + x86SetJ8(j8Ptr[3]); + } + + if (x86FpuState==MMX_STATE) { + if (cpucaps.has3DNOWInstructionExtensions) + FEMMS(); + else + EMMS(); + } + if( s_nAddMemOffset ) + ADD32ItoR(ECX, s_nAddMemOffset); + if( s_bCachingMem & 4 ) + AND32ItoR(ECX, 0x5fffffff); +} static u16 g_MemMasks0[16] = {0x00f0, 0x80f1, 0x00f2, 0x00f3, 0x00f1, 0x00f5, 0x00f1, 0x00f5, diff --git a/pcsx2/x86/ix86/ix86.c b/pcsx2/x86/ix86/ix86.c index eb46e3b921..cfdfa695c2 100644 --- a/pcsx2/x86/ix86/ix86.c +++ b/pcsx2/x86/ix86/ix86.c @@ -1223,7 +1223,7 @@ _inline void ADD16ItoR( x86IntRegType to, u16 from ) { write8( 0x83 ); ModRM( 3, 0, to ); - write8( from ); + write8((u8)from ); } else { @@ -1242,7 +1242,7 @@ _inline void ADD16ItoM( uptr to, u16 from ) write8( 0x83 ); ModRM( 0, 0, DISP32 ); write32( MEMADDR(to, 6) ); - write8( from ); + write8((u8)from ); } else { @@ -2432,7 +2432,7 @@ _inline void AND16ItoR( x86IntRegType to, u16 from ) else if ( from < 0x80 ) { write8( 0x83 ); ModRM( 3, 0x4, to ); - write8( from ); + write8((u8)from ); } else { write8( 0x81 ); @@ -2449,7 +2449,7 @@ _inline void AND16ItoM( uptr to, u16 from ) write8( 0x83 ); ModRM( 0, 0x4, DISP32 ); write32( MEMADDR(to, 6) ); - write8( from ); + write8((u8)from ); } else { diff --git a/pcsx2/x86/ix86/ix86.h b/pcsx2/x86/ix86/ix86.h index 8945a445ed..019b571522 100644 --- a/pcsx2/x86/ix86/ix86.h +++ b/pcsx2/x86/ix86/ix86.h @@ -239,9 +239,9 @@ extern u32 *j32Ptr[32]; #define RexRXB(w, reg, index, base) if( w||(reg) >= 8 || (index) >= 8 || (base) >= 8 ) assert(0); #endif -extern void write8( int val ); -extern void write16( int val ); -extern void write32( u32 val ); +extern __forceinline void write8( u8 val ); +extern __forceinline void write16( u16 val ); +extern __forceinline void write32( u32 val ); extern void write64( u64 val ); @@ -1787,32 +1787,32 @@ extern void SSE2EMU_MOVD_R_to_XMM( x86SSERegType to, x86IntRegType from ); #define WRITECHECK() #endif -#define write8(val ) { \ - *(u8*)x86Ptr = (u8)val; \ - x86Ptr++; \ -} \ +__forceinline void write8(u8 val ) { + *(u8*)x86Ptr = (u8)val; + x86Ptr++; +} -#define write16(val ) \ -{ \ - *(u16*)x86Ptr = (u16)val; \ - x86Ptr += 2; \ -} \ +__forceinline void write16(u16 val ) +{ + *(u16*)x86Ptr = (u16)val; + x86Ptr += 2; +} -#define write24(val ) \ -{ \ - *(u8*)x86Ptr = (u8)(val & 0xff); \ - x86Ptr++; \ - *(u8*)x86Ptr = (u8)((val >> 8) & 0xff); \ - x86Ptr++; \ - *(u8*)x86Ptr = (u8)((val >> 16) & 0xff); \ - x86Ptr++; \ -} \ +__forceinline void write24(u32 val ) +{ + *(u8*)x86Ptr = (u8)(val & 0xff); + x86Ptr++; + *(u8*)x86Ptr = (u8)((val >> 8) & 0xff); + x86Ptr++; + *(u8*)x86Ptr = (u8)((val >> 16) & 0xff); + x86Ptr++; +} -#define write32( val ) \ -{ \ - *(u32*)x86Ptr = val; \ - x86Ptr += 4; \ -} \ +__forceinline void write32(u32 val ) +{ + *(u32*)x86Ptr = val; + x86Ptr += 4; +} #ifdef __cplusplus }