started on the lower instructions

git-svn-id: http://pcsx2.googlecode.com/svn/trunk@724 96395faa-99c1-11dd-bbfe-3dabce05a288

pcsx2/x86/microVU_Alloc.h

@@ -44,7 +44,7 @@ struct microAllocInfo {
 					// bit 4 = (00 = instance #0, 01 = instance #1, 10 = instance #2, 11 = instance #3)
 					// bit 5 = Write to Q1 or Q2?
 					// bit 6 = Read Q1 or Q2?
-					// bit 7 = Write VI(Fd) Result to backup memory?
+					// bit 7 = Read/Write to P1 or P2?
 					// bit 8 = Update Mac Flags?
 					// bit 9 = Update Status Flags?
 					// bit 10 = Used with bit 11 to make a 2-bit key for mac flag instance

pcsx2/x86/microVU_Alloc.inl

@@ -861,7 +861,8 @@ microVUt(void) mVUallocSFLAGa(int reg, int fInstance) {
 
 microVUt(void) mVUallocSFLAGb(int reg, int fInstance) {
 	getFlagReg(fInstance, fInstance);
-	MOV32RtoR(fInstance, reg);
+	AND32ItoR(fInstance, 0xffff0000);
+	OR16RtoR(fInstance, reg);
 }
 
 microVUt(void) mVUallocMFLAGa(int reg, int fInstance) {
@@ -877,4 +878,31 @@ microVUt(void) mVUallocMFLAGb(int reg, int fInstance) {
 	OR32RtoR(fInstance, reg);
 }
 
+//------------------------------------------------------------------
+// VI Reg Allocators
+//------------------------------------------------------------------
+
+microVUt(void) mVUallocVIa(int GPRreg, int _reg_) {
+	microVU* mVU = mVUx;
+	if (_reg_ == 0)		{ XOR32RtoR(GPRreg, GPRreg); }
+	else if (_reg_ < 9)	{ MOVD32MMXtoR(GPRreg, mmxVI1 + (_reg_ - 1)); }
+	else				{ MOVZX32M16toR(GPRreg, (uptr)&mVU->regs->VI[_reg_].UL); }
+}
+
+microVUt(void) mVUallocVIb(int GPRreg, int _reg_) {
+	microVU* mVU = mVUx;
+	if (_reg_ == 0)		{ return; }
+	else if (_reg_ < 9)	{ MOVD32RtoMMX(mmxVI1 + (_reg_ - 1), GPRreg); }
+	else				{ MOV16RtoM((uptr)&mVU->regs->VI[_reg_].UL, GPRreg); }
+}
+
+//------------------------------------------------------------------
+// P Reg Allocator
+//------------------------------------------------------------------
+
+#define getPreg(reg) {  \
+	mVUunpack_xyzw<vuIndex>(reg, xmmPQ, (2 + writeP));  \
+	/*if (CHECK_VU_EXTRA_OVERFLOW) mVUclamp2<vuIndex>(reg, xmmT1, 15);*/  \
+}
+
 #endif //PCSX2_MICROVU

pcsx2/x86/microVU_Lower.inl

@@ -26,6 +26,99 @@
 microVUf(void) mVU_DIV(){}
 microVUf(void) mVU_SQRT(){}
 microVUf(void) mVU_RSQRT(){}
+
+microVUf(void) mVU_EATAN(){}
+microVUf(void) mVU_EATANxy(){}
+microVUf(void) mVU_EATANxz(){}
+microVUf(void) mVU_EEXP(){}
+microVUf(void) mVU_ELENG(){}
+microVUf(void) mVU_ERCPR(){}
+microVUf(void) mVU_ERLENG(){}
+microVUf(void) mVU_ERSADD(){}
+microVUf(void) mVU_ERSQRT(){}
+microVUf(void) mVU_ESADD(){}
+microVUf(void) mVU_ESIN(){} 
+microVUf(void) mVU_ESQRT(){}
+microVUf(void) mVU_ESUM(){}
+
+microVUf(void) mVU_FCAND(){}
+microVUf(void) mVU_FCEQ(){}
+microVUf(void) mVU_FCOR(){}
+microVUf(void) mVU_FCSET(){}
+microVUf(void) mVU_FCGET(){}
+
+microVUf(void) mVU_FMAND() {
+	microVU* mVU = mVUx;
+	if (recPass == 0) {}
+	else { 
+		mVUallocMFLAGa<vuIndex>(gprT1, fvmInstance);
+		mVUallocVIa<vuIndex>(gprT2, _Fs_);
+		AND16RtoR(gprT1, gprT2);
+		mVUallocVIb<vuIndex>(gprT1, _Ft_);
+	}
+}
+microVUf(void) mVU_FMEQ() {
+	microVU* mVU = mVUx;
+	if (recPass == 0) {}
+	else { 
+		mVUallocMFLAGa<vuIndex>(gprT1, fvmInstance);
+		mVUallocVIa<vuIndex>(gprT2, _Fs_);
+		CMP16RtoR(gprT1, gprT2);
+		SETE8R(gprT1);
+		AND16ItoR(gprT1, 0x1);
+		mVUallocVIb<vuIndex>(gprT1, _Ft_);
+	}
+}
+microVUf(void) mVU_FMOR() {
+	microVU* mVU = mVUx;
+	if (recPass == 0) {}
+	else { 
+		mVUallocMFLAGa<vuIndex>(gprT1, fvmInstance);
+		mVUallocVIa<vuIndex>(gprT2, _Fs_);
+		OR16RtoR(gprT1, gprT2);
+		mVUallocVIb<vuIndex>(gprT1, _Ft_);
+	}
+}
+
+microVUf(void) mVU_FSAND() {
+	microVU* mVU = mVUx;
+	if (recPass == 0) {}
+	else { 
+		mVUallocSFLAGa<vuIndex>(gprT1, fvsInstance);
+		AND16ItoR(gprT1, _Imm12_);
+		mVUallocVIb<vuIndex>(gprT1, _Ft_);
+	}
+}
+microVUf(void) mVU_FSEQ() {
+	microVU* mVU = mVUx;
+	if (recPass == 0) {}
+	else { 
+		mVUallocSFLAGa<vuIndex>(gprT1, fvsInstance);
+		CMP16ItoR(gprT1, _Imm12_);
+		SETE8R(gprT1);
+		AND16ItoR(gprT1, 0x1);
+		mVUallocVIb<vuIndex>(gprT1, _Ft_);
+	}
+}
+microVUf(void) mVU_FSOR() {
+	microVU* mVU = mVUx;
+	if (recPass == 0) {}
+	else { 
+		mVUallocSFLAGa<vuIndex>(gprT1, fvsInstance);
+		OR16ItoR(gprT1, _Imm12_);
+		mVUallocVIb<vuIndex>(gprT1, _Ft_);
+	}
+}
+microVUf(void) mVU_FSSET() {
+	microVU* mVU = mVUx;
+	if (recPass == 0) {}
+	else { 
+		int flagReg;
+		getFlagReg(flagReg, fsInstance);
+		MOV16ItoR(gprT1, (_Imm12_ & 0xfc0));
+	}
+}
+
 microVUf(void) mVU_IADD(){}
 microVUf(void) mVU_IADDI(){}
 microVUf(void) mVU_IADDIU(){}
@@ -33,64 +126,100 @@ microVUf(void) mVU_IAND(){}
 microVUf(void) mVU_IOR(){}
 microVUf(void) mVU_ISUB(){}
 microVUf(void) mVU_ISUBIU(){}
-microVUf(void) mVU_MOVE(){}
+
-microVUf(void) mVU_MFIR(){}
+microVUf(void) mVU_B(){}
-microVUf(void) mVU_MTIR(){}
+microVUf(void) mVU_BAL(){}
-microVUf(void) mVU_MR32(){}
-microVUf(void) mVU_LQ(){}
-microVUf(void) mVU_LQD(){}
-microVUf(void) mVU_LQI(){}
-microVUf(void) mVU_SQ(){}
-microVUf(void) mVU_SQD(){}
-microVUf(void) mVU_SQI(){}
-microVUf(void) mVU_ILW(){}
-microVUf(void) mVU_ISW(){}
-microVUf(void) mVU_ILWR(){}
-microVUf(void) mVU_ISWR(){}
-microVUf(void) mVU_LOI(){}
-microVUf(void) mVU_RINIT(){}
-microVUf(void) mVU_RGET(){}
-microVUf(void) mVU_RNEXT(){}
-microVUf(void) mVU_RXOR(){}
-microVUf(void) mVU_WAITQ(){}
-microVUf(void) mVU_FSAND(){}
-microVUf(void) mVU_FSEQ(){}
-microVUf(void) mVU_FSOR(){}
-microVUf(void) mVU_FSSET(){}
-microVUf(void) mVU_FMAND(){}
-microVUf(void) mVU_FMEQ(){}
-microVUf(void) mVU_FMOR(){}
-microVUf(void) mVU_FCAND(){}
-microVUf(void) mVU_FCEQ(){}
-microVUf(void) mVU_FCOR(){}
-microVUf(void) mVU_FCSET(){}
-microVUf(void) mVU_FCGET(){}
 microVUf(void) mVU_IBEQ(){}
 microVUf(void) mVU_IBGEZ(){}
 microVUf(void) mVU_IBGTZ(){}
 microVUf(void) mVU_IBLTZ(){}
 microVUf(void) mVU_IBLEZ(){}
 microVUf(void) mVU_IBNE(){}
-microVUf(void) mVU_B(){}
-microVUf(void) mVU_BAL(){}
 microVUf(void) mVU_JR(){}
 microVUf(void) mVU_JALR(){}
-microVUf(void) mVU_MFP(){}
+
+microVUf(void) mVU_ILW(){}
+microVUf(void) mVU_ISW(){}
+microVUf(void) mVU_ILWR(){}
+microVUf(void) mVU_ISWR(){}
+
+microVUf(void) mVU_MOVE() {
+	microVU* mVU = mVUx;
+	if (recPass == 0) {}
+	else { 
+		mVUloadReg<vuIndex>(xmmT1, (uptr)&mVU->regs->VF[_Fs_].UL[0], _X_Y_Z_W);
+		mVUsaveReg<vuIndex>(xmmT1, (uptr)&mVU->regs->VF[_Ft_].UL[0], _X_Y_Z_W);
+	}
+}
+microVUf(void) mVU_MFIR() {
+	microVU* mVU = mVUx;
+	if (recPass == 0) {}
+	else { 
+		mVUallocVIa<vuIndex>(gprT1, _Fs_);
+		SHL32ItoR(gprT1, 16);
+		SAR32ItoR(gprT1, 16);
+		SSE2_MOVD_R_to_XMM(xmmT1, gprT1);
+		if (!_XYZW_SS) { mVUunpack_xyzw<vuIndex>(xmmT1, xmmT1, 0); }
+		mVUsaveReg<vuIndex>(xmmT1, (uptr)&mVU->regs->VF[_Ft_].UL[0], _X_Y_Z_W);
+	}
+}
+microVUf(void) mVU_MFP() {
+	microVU* mVU = mVUx;
+	if (recPass == 0) {}
+	else { 
+		getPreg(xmmFt);
+		mVUsaveReg<vuIndex>(xmmFt, (uptr)&mVU->regs->VF[_Ft_].UL[0], _X_Y_Z_W);
+	}
+}
+microVUf(void) mVU_MTIR() {
+	microVU* mVU = mVUx;
+	if (recPass == 0) {}
+	else { 
+		MOVZX32M16toR(gprT1, (uptr)&mVU->regs->VF[_Fs_].UL[_Fsf_]);
+		mVUallocVIb<vuIndex>(gprT1, _Ft_);
+	}
+}
+microVUf(void) mVU_MR32() {
+	microVU* mVU = mVUx;
+	if (recPass == 0) {}
+	else { 
+		mVUloadReg<vuIndex>(xmmT1, (uptr)&mVU->regs->VF[_Fs_].UL[0], (_X_Y_Z_W == 8) ? 4 : 15);
+		if (_X_Y_Z_W != 8) { SSE_SHUFPS_XMM_to_XMM(xmmT1, xmmT1, 0x39); }
+		mVUsaveReg<vuIndex>(xmmT1, (uptr)&mVU->regs->VF[_Ft_].UL[0], _X_Y_Z_W);
+	}
+}
+
+microVUf(void) mVU_LQ(){}
+microVUf(void) mVU_LQD(){}
+microVUf(void) mVU_LQI(){}
+microVUf(void) mVU_SQ(){}
+microVUf(void) mVU_SQD(){}
+microVUf(void) mVU_SQI(){}
+//microVUf(void) mVU_LOI(){}
+
+microVUf(void) mVU_RINIT(){}
+microVUf(void) mVU_RGET(){}
+microVUf(void) mVU_RNEXT(){}
+microVUf(void) mVU_RXOR(){}
+
 microVUf(void) mVU_WAITP(){}
-microVUf(void) mVU_ESADD(){}
+microVUf(void) mVU_WAITQ(){}
-microVUf(void) mVU_ERSADD(){}
+
-microVUf(void) mVU_ELENG(){}
-microVUf(void) mVU_ERLENG(){}
-microVUf(void) mVU_EATANxy(){}
-microVUf(void) mVU_EATANxz(){}
-microVUf(void) mVU_ESUM(){}
-microVUf(void) mVU_ERCPR(){}
-microVUf(void) mVU_ESQRT(){}
-microVUf(void) mVU_ERSQRT(){}
-microVUf(void) mVU_ESIN(){} 
-microVUf(void) mVU_EATAN(){}
-microVUf(void) mVU_EEXP(){}
 microVUf(void) mVU_XGKICK(){}
-microVUf(void) mVU_XTOP(){}
+microVUf(void) mVU_XTOP() {
-microVUf(void) mVU_XITOP(){}
+	microVU* mVU = mVUx;
+	if (recPass == 0) {}
+	else { 
+		MOVZX32M16toR( gprT1, (uptr)&mVU->regs->vifRegs->top);
+		mVUallocVIb<vuIndex>(gprT1, _Ft_);
+	}
+}
+microVUf(void) mVU_XITOP() {
+	microVU* mVU = mVUx;
+	if (recPass == 0) {}
+	else { 
+		MOVZX32M16toR( gprT1, (uptr)&mVU->regs->vifRegs->itop );
+		mVUallocVIb<vuIndex>(gprT1, _Ft_);
+	}
+}
 #endif //PCSX2_MICROVU

pcsx2/x86/microVU_Misc.h

@@ -55,11 +55,12 @@ PCSX2_ALIGNED16_EXTERN(const float mVU_ITOF_15[4]);
 #define _bc_z	((mVU->code & 0x03) == 2)
 #define _bc_w	((mVU->code & 0x03) == 3)
 
-#define _Fsf_ ((mVU->code >> 21) & 0x03)
+#define _Fsf_	((mVU->code >> 21) & 0x03)
-#define _Ftf_ ((mVU->code >> 23) & 0x03)
+#define _Ftf_	((mVU->code >> 23) & 0x03)
 
 #define _Imm11_ 	(s32)(mVU->code & 0x400 ? 0xfffffc00 | (mVU->code & 0x3ff) : mVU->code & 0x3ff)
 #define _UImm11_	(s32)(mVU->code & 0x7ff)
+#define _Imm12_		(((mVU->code >> 21 ) & 0x1) << 11) | (mVU->code & 0x7ff)
 
 #define xmmT1	0 // Temp Reg
 #define xmmFs	1 // Holds the Value of Fs (writes back result Fd)
@@ -70,14 +71,14 @@ PCSX2_ALIGNED16_EXTERN(const float mVU_ITOF_15[4]);
 #define xmmACC3	6 // Holds ACC Instance #3
 #define xmmPQ	7 // Holds the Value and Backup Values of P and Q regs
 
-#define mmxT1	0 // Temp Reg
+#define mmxVI1	0 // Holds VI 1
-#define mmxC	1 // Clip Flag?
+#define mmxVI2	1 // Holds VI 2
-#define mmxVI0	2 // Holds VI 00 to 03?
+#define mmxVI3	2 // Holds VI 3
-#define mmxVI1	3 // Holds VI 04 to 07?
+#define mmxVI4	3 // Holds VI 4
-#define mmxVI2	4 // Holds VI 08 to 11?
+#define mmxVI5	4 // Holds VI 5
-#define mmxVI3	5 // Holds VI 12 to 15?
+#define mmxVI6	5 // Holds VI 6
-#define mmxM	6 // ?
+#define mmxVI7	6 // Holds VI 7
-#define mmxS	7 // ?
+#define mmxVI8	7 // Holds VI 8
 
 #define gprT1	0 // Temp Reg
 #define gprT2	1 // Temp Reg
@@ -103,7 +104,8 @@ PCSX2_ALIGNED16_EXTERN(const float mVU_ITOF_15[4]);
 #define readACC		((mVUallocInfo.info[mVUallocInfo.curPC] & (3<<3)) >> 3)
 #define writeQ		((mVUallocInfo.info[mVUallocInfo.curPC] & (1<<5)) >> 5)
 #define readQ		((mVUallocInfo.info[mVUallocInfo.curPC] & (1<<6)) >> 6)
-//#define setFd		 (mVUallocInfo.info[mVUallocInfo.curPC] & (1<<7))
+#define writeP		((mVUallocInfo.info[mVUallocInfo.curPC] & (1<<7)) >> 7)
+#define readP		((mVUallocInfo.info[mVUallocInfo.curPC] & (1<<7)) >> 7) // same as write
 #define doFlags		 (mVUallocInfo.info[mVUallocInfo.curPC] & (3<<8))
 #define doMac		 (mVUallocInfo.info[mVUallocInfo.curPC] & (1<<8))
 #define doStatus	 (mVUallocInfo.info[mVUallocInfo.curPC] & (1<<9))
@@ -111,6 +113,8 @@ PCSX2_ALIGNED16_EXTERN(const float mVU_ITOF_15[4]);
 #define fsInstance	((mVUallocInfo.info[mVUallocInfo.curPC] & (3<<12)) >> 12)
 #define fpmInstance	(((u8)((mVUallocInfo.info[mVUallocInfo.curPC] & (3<<10)) >> 10) - 1) & 0x3)
 #define fpsInstance	(((u8)((mVUallocInfo.info[mVUallocInfo.curPC] & (3<<12)) >> 12) - 1) & 0x3)
+#define fvmInstance	((mVUallocInfo.info[mVUallocInfo.curPC] & (3<<14)) >> 14)
+#define fvsInstance	((mVUallocInfo.info[mVUallocInfo.curPC] & (3<<16)) >> 16)
 //#define getFs		 (mVUallocInfo.info[mVUallocInfo.curPC] & (1<<13))
 //#define getFt		 (mVUallocInfo.info[mVUallocInfo.curPC] & (1<<14))