mirror of https://github.com/PCSX2/pcsx2.git
microVU's upper instruction implementations (second pass) finished (except for clip instruction)
git-svn-id: http://pcsx2.googlecode.com/svn/trunk@723 96395faa-99c1-11dd-bbfe-3dabce05a288
This commit is contained in:
cottonvibes
parent
0c9abd6765
commit
a44c6f0f83
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@ -42,8 +42,8 @@ struct microAllocInfo {
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// bit 2 = (00 = instance #0, 01 = instance #1, 10 = instance #2, 11 = instance #3)
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// bit 3 = Used with bit 4 to make a 2-bit key for ACC read instance
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// bit 4 = (00 = instance #0, 01 = instance #1, 10 = instance #2, 11 = instance #3)
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// bit 5 = Read Q1/P1 or backup?
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// bit 6 = Write to Q2/P2?
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// bit 5 = Write to Q1 or Q2?
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// bit 6 = Read Q1 or Q2?
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// bit 7 = Write VI(Fd) Result to backup memory?
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// bit 8 = Update Mac Flags?
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// bit 9 = Update Status Flags?
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@ -658,6 +658,189 @@ microVUt(void) mVUallocFMAC19b(int& Fd) {
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mVUallocFMAC9b<vuIndex>(Fd);
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}
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//------------------------------------------------------------------
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// FMAC20 - MADDA FMAC Opcode (I Reg)
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//------------------------------------------------------------------
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microVUt(void) mVUallocFMAC20a(int& ACCw, int&ACCr, int& Fs, int& Ft) {
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microVU* mVU = mVUx;
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getACC(ACCw);
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Fs = (_X_Y_Z_W == 15) ? ACCw : xmmFs;
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Ft = xmmFt;
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ACCr = xmmACC0 + readACC;
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getIreg(Ft);
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if (_XYZW_SS && _X) {
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if (!_Fs_) { getZeroSS(Fs); }
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else { getReg(Fs, _Fs_); }
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}
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else {
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if (!_Fs_) { getZero4(Fs); }
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else { getReg4(Fs, _Fs_); }
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}
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}
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microVUt(void) mVUallocFMAC20b(int& ACCw, int& Fs) {
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mVUallocFMAC14b<vuIndex>(ACCw, Fs);
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}
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//------------------------------------------------------------------
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// FMAC21 - MSUBA FMAC Opcode (I Reg)
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//------------------------------------------------------------------
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microVUt(void) mVUallocFMAC21a(int& ACCw, int&ACCr, int& Fs, int& Ft) {
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mVUallocFMAC20a<vuIndex>(ACCw, ACCr, Fs, Ft);
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SSE_MOVAPS_XMM_to_XMM(xmmT1, ACCr);
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ACCr = xmmT1;
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}
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microVUt(void) mVUallocFMAC21b(int& ACCw, int& ACCr) {
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mVUallocFMAC15b<vuIndex>(ACCw, ACCr);
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}
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//------------------------------------------------------------------
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// FMAC22 - Normal FMAC Opcodes (Q Reg)
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//------------------------------------------------------------------
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#define getQreg(reg) { \
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mVUunpack_xyzw<vuIndex>(reg, xmmPQ, writeQ); \
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/*if (CHECK_VU_EXTRA_OVERFLOW) mVUclamp2<vuIndex>(reg, xmmT1, 15);*/ \
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}
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microVUt(void) mVUallocFMAC22a(int& Fd, int& Fs, int& Ft) {
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microVU* mVU = mVUx;
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Fs = xmmFs;
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Ft = xmmFt;
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Fd = xmmFs;
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getQreg(Ft);
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if (_XYZW_SS) {
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if (!_Fs_) { getZeroSS(Fs); }
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else { getReg(Fs, _Fs_); }
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}
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else {
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if (!_Fs_) { getZero(Fs); }
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else { getReg(Fs, _Fs_); }
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}
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}
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microVUt(void) mVUallocFMAC22b(int& Fd) {
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mVUallocFMAC1b<vuIndex>(Fd);
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}
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//------------------------------------------------------------------
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// FMAC23 - FMAC Opcodes Storing Result to ACC (Q Reg)
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//------------------------------------------------------------------
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microVUt(void) mVUallocFMAC23a(int& ACC, int& Fs, int& Ft) {
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microVU* mVU = mVUx;
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Fs = xmmFs;
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Ft = xmmFt;
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getACC(ACC);
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getQreg(Ft);
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if (_XYZW_SS && _X) {
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if (!_Fs_) { getZeroSS(Fs); }
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else { getReg(Fs, _Fs_); }
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}
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else {
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if (!_Fs_) { getZero4(Fs); }
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else { getReg4(Fs, _Fs_); }
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}
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}
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microVUt(void) mVUallocFMAC23b(int& ACC, int& Fs) {
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mVUallocFMAC4b<vuIndex>(ACC, Fs);
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}
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//------------------------------------------------------------------
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// FMAC24 - MADD FMAC Opcode Storing Result to Fd (Q Reg)
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//------------------------------------------------------------------
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microVUt(void) mVUallocFMAC24a(int& Fd, int&ACC, int& Fs, int& Ft) {
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microVU* mVU = mVUx;
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Fs = xmmFs;
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Ft = xmmFt;
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Fd = xmmFs;
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ACC = xmmACC0 + readACC;
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getQreg(Ft);
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if (_XYZW_SS && _X) {
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if (!_Fs_) { getZeroSS(Fs); }
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else { getReg(Fs, _Fs_); }
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}
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else {
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if (!_Fs_) { getZero4(Fs); }
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else { getReg4(Fs, _Fs_); }
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}
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}
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microVUt(void) mVUallocFMAC24b(int& Fd) {
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mVUallocFMAC8b<vuIndex>(Fd);
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}
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//------------------------------------------------------------------
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// FMAC25 - MSUB FMAC Opcode Storing Result to Fd (Q Reg)
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//------------------------------------------------------------------
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microVUt(void) mVUallocFMAC25a(int& Fd, int&ACC, int& Fs, int& Ft) {
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microVU* mVU = mVUx;
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Fs = xmmFs;
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Ft = xmmFt;
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Fd = xmmT1;
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ACC = xmmT1;
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SSE_MOVAPS_XMM_to_XMM(ACC, xmmACC0 + readACC);
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getQreg(Ft);
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if (_XYZW_SS && _X) {
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if (!_Fs_) { getZeroSS(Fs); }
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else { getReg(Fs, _Fs_); }
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}
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else {
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if (!_Fs_) { getZero4(Fs); }
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else { getReg4(Fs, _Fs_); }
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}
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}
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microVUt(void) mVUallocFMAC25b(int& Fd) {
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mVUallocFMAC9b<vuIndex>(Fd);
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}
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//------------------------------------------------------------------
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// FMAC26 - MADDA FMAC Opcode (Q Reg)
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//------------------------------------------------------------------
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microVUt(void) mVUallocFMAC26a(int& ACCw, int&ACCr, int& Fs, int& Ft) {
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microVU* mVU = mVUx;
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getACC(ACCw);
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Fs = (_X_Y_Z_W == 15) ? ACCw : xmmFs;
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Ft = xmmFt;
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ACCr = xmmACC0 + readACC;
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getQreg(Ft);
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if (_XYZW_SS && _X) {
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if (!_Fs_) { getZeroSS(Fs); }
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else { getReg(Fs, _Fs_); }
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}
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else {
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if (!_Fs_) { getZero4(Fs); }
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else { getReg4(Fs, _Fs_); }
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}
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}
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microVUt(void) mVUallocFMAC26b(int& ACCw, int& Fs) {
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mVUallocFMAC14b<vuIndex>(ACCw, Fs);
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}
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//------------------------------------------------------------------
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// FMAC27 - MSUBA FMAC Opcode (Q Reg)
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//------------------------------------------------------------------
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microVUt(void) mVUallocFMAC27a(int& ACCw, int&ACCr, int& Fs, int& Ft) {
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mVUallocFMAC26a<vuIndex>(ACCw, ACCr, Fs, Ft);
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SSE_MOVAPS_XMM_to_XMM(xmmT1, ACCr);
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ACCr = xmmT1;
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}
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microVUt(void) mVUallocFMAC27b(int& ACCw, int& ACCr) {
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mVUallocFMAC15b<vuIndex>(ACCw, ACCr);
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}
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//------------------------------------------------------------------
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// Flag Allocators
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//------------------------------------------------------------------
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@ -101,6 +101,8 @@ PCSX2_ALIGNED16_EXTERN(const float mVU_ITOF_15[4]);
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#define writeACC ((mVUallocInfo.info[mVUallocInfo.curPC] & (3<<1)) >> 1)
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#define prevACC (((u8)((mVUallocInfo.info[mVUallocInfo.curPC] & (3<<1)) >> 1) - 1) & 0x3)
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#define readACC ((mVUallocInfo.info[mVUallocInfo.curPC] & (3<<3)) >> 3)
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#define writeQ ((mVUallocInfo.info[mVUallocInfo.curPC] & (1<<5)) >> 5)
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#define readQ ((mVUallocInfo.info[mVUallocInfo.curPC] & (1<<6)) >> 6)
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//#define setFd (mVUallocInfo.info[mVUallocInfo.curPC] & (1<<7))
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#define doFlags (mVUallocInfo.info[mVUallocInfo.curPC] & (3<<8))
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#define doMac (mVUallocInfo.info[mVUallocInfo.curPC] & (1<<8))
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@ -79,8 +79,8 @@ microVUx(void) mVUloadReg(int reg, u32 offset, int xyzw) {
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case 4: SSE_MOVSS_M32_to_XMM(reg, offset+4); break; // Y
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case 2: SSE_MOVSS_M32_to_XMM(reg, offset+8); break; // Z
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case 1: SSE_MOVSS_M32_to_XMM(reg, offset+12); break; // W
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case 3: SSE_MOVHPS_M64_to_XMM(reg, offset+8); break; // ZW (not sure if this is faster than default)
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case 12: SSE_MOVLPS_M64_to_XMM(reg, offset); break; // XY (not sure if this is faster than default)
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//case 3: SSE_MOVHPS_M64_to_XMM(reg, offset+8); break; // ZW (not sure if this is faster than default)
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//case 12: SSE_MOVLPS_M64_to_XMM(reg, offset); break; // XY (not sure if this is faster than default)
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default: SSE_MOVAPS_M128_to_XMM(reg, offset); break;
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}
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}
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@ -389,6 +389,154 @@ microVUt(void) mVUupdateFlags(int reg, int regT1, int regT2, int xyzw, bool modX
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} \
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}
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#define mVU_FMAC20(operation) { \
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microVU* mVU = mVUx; \
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if (recPass == 0) {} \
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else { \
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int ACCw, ACCr, Fs, Ft; \
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if (isNOP) return; \
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mVUallocFMAC20a<vuIndex>(ACCw, ACCr, Fs, Ft); \
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if (_XYZW_SS && _X) { \
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SSE_MULSS_XMM_to_XMM(Fs, Ft); \
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SSE_##operation##SS_XMM_to_XMM(Fs, ACCr); \
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} \
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else { \
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SSE_MULPS_XMM_to_XMM(Fs, Ft); \
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SSE_##operation##PS_XMM_to_XMM(Fs, ACCr); \
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} \
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mVUupdateFlags<vuIndex>(Fs, xmmT1, Ft, _X_Y_Z_W, 0); \
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mVUallocFMAC20b<vuIndex>(ACCw, Fs); \
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} \
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}
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#define mVU_FMAC21(operation) { \
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microVU* mVU = mVUx; \
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if (recPass == 0) {} \
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else { \
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int ACCw, ACCr, Fs, Ft; \
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if (isNOP) return; \
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mVUallocFMAC21a<vuIndex>(ACCw, ACCr, Fs, Ft); \
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if (_XYZW_SS && _X) { \
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SSE_MULSS_XMM_to_XMM(Fs, Ft); \
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SSE_##operation##SS_XMM_to_XMM(ACCr, Fs); \
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} \
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else { \
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SSE_MULPS_XMM_to_XMM(Fs, Ft); \
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SSE_##operation##PS_XMM_to_XMM(ACCr, Fs); \
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} \
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mVUupdateFlags<vuIndex>(ACCr, Fs, Ft, _X_Y_Z_W, 0); \
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mVUallocFMAC21b<vuIndex>(ACCw, ACCr); \
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} \
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}
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#define mVU_FMAC22(operation) { \
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microVU* mVU = mVUx; \
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if (recPass == 0) {} \
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else { \
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int Fd, Fs, Ft; \
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if (isNOP) return; \
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mVUallocFMAC22a<vuIndex>(Fd, Fs, Ft); \
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if (_XYZW_SS) SSE_##operation##SS_XMM_to_XMM(Fs, Ft); \
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else SSE_##operation##PS_XMM_to_XMM(Fs, Ft); \
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mVUupdateFlags<vuIndex>(Fd, xmmT1, Ft, _X_Y_Z_W, 1); \
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mVUallocFMAC22b<vuIndex>(Fd); \
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} \
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}
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#define mVU_FMAC23(operation) { \
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microVU* mVU = mVUx; \
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if (recPass == 0) {} \
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else { \
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int ACC, Fs, Ft; \
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if (isNOP) return; \
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mVUallocFMAC23a<vuIndex>(ACC, Fs, Ft); \
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if (_XYZW_SS && _X) SSE_##operation##SS_XMM_to_XMM(Fs, Ft); \
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else SSE_##operation##PS_XMM_to_XMM(Fs, Ft); \
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mVUupdateFlags<vuIndex>(Fs, xmmT1, Ft, _X_Y_Z_W, 0); \
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mVUallocFMAC23b<vuIndex>(ACC, Fs); \
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} \
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}
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#define mVU_FMAC24(operation) { \
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microVU* mVU = mVUx; \
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if (recPass == 0) {} \
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else { \
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int Fd, ACC, Fs, Ft; \
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if (isNOP) return; \
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mVUallocFMAC24a<vuIndex>(Fd, ACC, Fs, Ft); \
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if (_XYZW_SS && _X) { \
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SSE_MULSS_XMM_to_XMM(Fs, Ft); \
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SSE_##operation##SS_XMM_to_XMM(Fs, ACC); \
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} \
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else { \
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SSE_MULPS_XMM_to_XMM(Fs, Ft); \
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SSE_##operation##PS_XMM_to_XMM(Fs, ACC); \
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} \
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mVUupdateFlags<vuIndex>(Fd, xmmT1, Ft, _X_Y_Z_W, 0); \
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mVUallocFMAC24b<vuIndex>(Fd); \
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} \
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}
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#define mVU_FMAC25(operation) { \
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microVU* mVU = mVUx; \
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if (recPass == 0) {} \
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else { \
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int Fd, ACC, Fs, Ft; \
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if (isNOP) return; \
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mVUallocFMAC25a<vuIndex>(Fd, ACC, Fs, Ft); \
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if (_XYZW_SS && _X) { \
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SSE_MULSS_XMM_to_XMM(Fs, Ft); \
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SSE_##operation##SS_XMM_to_XMM(ACC, Fs); \
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} \
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else { \
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SSE_MULPS_XMM_to_XMM(Fs, Ft); \
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SSE_##operation##PS_XMM_to_XMM(ACC, Fs); \
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} \
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mVUupdateFlags<vuIndex>(Fd, Fs, Ft, _X_Y_Z_W, 0); \
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mVUallocFMAC25b<vuIndex>(Fd); \
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} \
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}
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#define mVU_FMAC26(operation) { \
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microVU* mVU = mVUx; \
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if (recPass == 0) {} \
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else { \
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int ACCw, ACCr, Fs, Ft; \
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if (isNOP) return; \
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mVUallocFMAC26a<vuIndex>(ACCw, ACCr, Fs, Ft); \
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if (_XYZW_SS && _X) { \
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SSE_MULSS_XMM_to_XMM(Fs, Ft); \
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SSE_##operation##SS_XMM_to_XMM(Fs, ACCr); \
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} \
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else { \
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SSE_MULPS_XMM_to_XMM(Fs, Ft); \
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SSE_##operation##PS_XMM_to_XMM(Fs, ACCr); \
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} \
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mVUupdateFlags<vuIndex>(Fs, xmmT1, Ft, _X_Y_Z_W, 0); \
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mVUallocFMAC26b<vuIndex>(ACCw, Fs); \
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} \
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}
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#define mVU_FMAC27(operation) { \
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microVU* mVU = mVUx; \
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if (recPass == 0) {} \
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else { \
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int ACCw, ACCr, Fs, Ft; \
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if (isNOP) return; \
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mVUallocFMAC27a<vuIndex>(ACCw, ACCr, Fs, Ft); \
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if (_XYZW_SS && _X) { \
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SSE_MULSS_XMM_to_XMM(Fs, Ft); \
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SSE_##operation##SS_XMM_to_XMM(ACCr, Fs); \
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} \
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else { \
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SSE_MULPS_XMM_to_XMM(Fs, Ft); \
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SSE_##operation##PS_XMM_to_XMM(ACCr, Fs); \
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} \
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mVUupdateFlags<vuIndex>(ACCr, Fs, Ft, _X_Y_Z_W, 0); \
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mVUallocFMAC27b<vuIndex>(ACCw, ACCr); \
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} \
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}
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//------------------------------------------------------------------
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// Micro VU Micromode Upper instructions
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//------------------------------------------------------------------
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@ -406,70 +554,70 @@ microVUf(void) mVU_ABS() {
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}
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microVUf(void) mVU_ADD() { mVU_FMAC1(ADD); }
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microVUf(void) mVU_ADDi() { mVU_FMAC6(ADD); }
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microVUf(void) mVU_ADDq(){}
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microVUf(void) mVU_ADDq() { mVU_FMAC22(ADD); }
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microVUf(void) mVU_ADDx() { mVU_FMAC3(ADD); }
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microVUf(void) mVU_ADDy() { mVU_FMAC3(ADD); }
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microVUf(void) mVU_ADDz() { mVU_FMAC3(ADD); }
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microVUf(void) mVU_ADDw() { mVU_FMAC3(ADD); }
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microVUf(void) mVU_ADDA() { mVU_FMAC4(ADD); }
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microVUf(void) mVU_ADDAi() { mVU_FMAC7(ADD); }
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microVUf(void) mVU_ADDAq(){}
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microVUf(void) mVU_ADDAq() { mVU_FMAC23(ADD); }
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microVUf(void) mVU_ADDAx() { mVU_FMAC5(ADD); }
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microVUf(void) mVU_ADDAy() { mVU_FMAC5(ADD); }
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microVUf(void) mVU_ADDAz() { mVU_FMAC5(ADD); }
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microVUf(void) mVU_ADDAw() { mVU_FMAC5(ADD); }
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microVUf(void) mVU_SUB() { mVU_FMAC1(SUB); }
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microVUf(void) mVU_SUBi() { mVU_FMAC6(SUB); }
|
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microVUf(void) mVU_SUBq(){}
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microVUf(void) mVU_SUBq() { mVU_FMAC22(SUB); }
|
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microVUf(void) mVU_SUBx() { mVU_FMAC3(SUB); }
|
||||
microVUf(void) mVU_SUBy() { mVU_FMAC3(SUB); }
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microVUf(void) mVU_SUBz() { mVU_FMAC3(SUB); }
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microVUf(void) mVU_SUBw() { mVU_FMAC3(SUB); }
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microVUf(void) mVU_SUBA() { mVU_FMAC4(SUB); }
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microVUf(void) mVU_SUBAi() { mVU_FMAC7(SUB); }
|
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microVUf(void) mVU_SUBAq(){}
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||||
microVUf(void) mVU_SUBAq() { mVU_FMAC23(SUB); }
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microVUf(void) mVU_SUBAx() { mVU_FMAC5(SUB); }
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||||
microVUf(void) mVU_SUBAy() { mVU_FMAC5(SUB); }
|
||||
microVUf(void) mVU_SUBAz() { mVU_FMAC5(SUB); }
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microVUf(void) mVU_SUBAw() { mVU_FMAC5(SUB); }
|
||||
microVUf(void) mVU_MUL() { mVU_FMAC1(MUL); }
|
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microVUf(void) mVU_MULi() { mVU_FMAC6(MUL); }
|
||||
microVUf(void) mVU_MULq(){}
|
||||
microVUf(void) mVU_MULq() { mVU_FMAC22(MUL); }
|
||||
microVUf(void) mVU_MULx() { mVU_FMAC3(MUL); }
|
||||
microVUf(void) mVU_MULy() { mVU_FMAC3(MUL); }
|
||||
microVUf(void) mVU_MULz() { mVU_FMAC3(MUL); }
|
||||
microVUf(void) mVU_MULw() { mVU_FMAC3(MUL); }
|
||||
microVUf(void) mVU_MULA() { mVU_FMAC4(MUL); }
|
||||
microVUf(void) mVU_MULAi() { mVU_FMAC7(MUL); }
|
||||
microVUf(void) mVU_MULAq(){}
|
||||
microVUf(void) mVU_MULAq() { mVU_FMAC23(MUL); }
|
||||
microVUf(void) mVU_MULAx() { mVU_FMAC5(MUL); }
|
||||
microVUf(void) mVU_MULAy() { mVU_FMAC5(MUL); }
|
||||
microVUf(void) mVU_MULAz() { mVU_FMAC5(MUL); }
|
||||
microVUf(void) mVU_MULAw() { mVU_FMAC5(MUL); }
|
||||
microVUf(void) mVU_MADD() { mVU_FMAC8(ADD); }
|
||||
microVUf(void) mVU_MADDi() { mVU_FMAC12(ADD); }
|
||||
microVUf(void) mVU_MADDq(){}
|
||||
microVUf(void) mVU_MADDq() { mVU_FMAC24(ADD); }
|
||||
microVUf(void) mVU_MADDx() { mVU_FMAC10(ADD); }
|
||||
microVUf(void) mVU_MADDy() { mVU_FMAC10(ADD); }
|
||||
microVUf(void) mVU_MADDz() { mVU_FMAC10(ADD); }
|
||||
microVUf(void) mVU_MADDw() { mVU_FMAC10(ADD); }
|
||||
microVUf(void) mVU_MADDA() { mVU_FMAC14(ADD); }
|
||||
microVUf(void) mVU_MADDAi(){}
|
||||
microVUf(void) mVU_MADDAq(){}
|
||||
microVUf(void) mVU_MADDAi() { mVU_FMAC20(ADD); }
|
||||
microVUf(void) mVU_MADDAq() { mVU_FMAC26(ADD); }
|
||||
microVUf(void) mVU_MADDAx() { mVU_FMAC16(ADD); }
|
||||
microVUf(void) mVU_MADDAy() { mVU_FMAC16(ADD); }
|
||||
microVUf(void) mVU_MADDAz() { mVU_FMAC16(ADD); }
|
||||
microVUf(void) mVU_MADDAw() { mVU_FMAC16(ADD); }
|
||||
microVUf(void) mVU_MSUB() { mVU_FMAC9(SUB); }
|
||||
microVUf(void) mVU_MSUBi() { mVU_FMAC13(SUB); }
|
||||
microVUf(void) mVU_MSUBq(){}
|
||||
microVUf(void) mVU_MSUBq() { mVU_FMAC25(SUB); }
|
||||
microVUf(void) mVU_MSUBx() { mVU_FMAC11(SUB); }
|
||||
microVUf(void) mVU_MSUBy() { mVU_FMAC11(SUB); }
|
||||
microVUf(void) mVU_MSUBz() { mVU_FMAC11(SUB); }
|
||||
microVUf(void) mVU_MSUBw() { mVU_FMAC11(SUB); }
|
||||
microVUf(void) mVU_MSUBA() { mVU_FMAC14(SUB); }
|
||||
microVUf(void) mVU_MSUBAi(){}
|
||||
microVUf(void) mVU_MSUBAq(){}
|
||||
microVUf(void) mVU_MSUBAi() { mVU_FMAC21(SUB); }
|
||||
microVUf(void) mVU_MSUBAq() { mVU_FMAC27(SUB); }
|
||||
microVUf(void) mVU_MSUBAx() { mVU_FMAC17(SUB); }
|
||||
microVUf(void) mVU_MSUBAy() { mVU_FMAC17(SUB); }
|
||||
microVUf(void) mVU_MSUBAz() { mVU_FMAC17(SUB); }
|
||||
|
|
@ -488,7 +636,11 @@ microVUf(void) mVU_MINIz() { mVU_FMAC3(MIN); }
|
|||
microVUf(void) mVU_MINIw() { mVU_FMAC3(MIN); }
|
||||
microVUf(void) mVU_OPMULA() { mVU_FMAC18(MUL); }
|
||||
microVUf(void) mVU_OPMSUB() { mVU_FMAC19(SUB); }
|
||||
microVUf(void) mVU_NOP(){}
|
||||
microVUf(void) mVU_NOP() {
|
||||
microVU* mVU = mVUx;
|
||||
if (recPass == 0) {}
|
||||
else {}
|
||||
}
|
||||
microVUq(void) mVU_FTOIx(uptr addr) {
|
||||
microVU* mVU = mVUx;
|
||||
if (recPass == 0) {}
|
||||
|
|
|
|||
Loading…
Reference in New Issue