mirror of https://github.com/PCSX2/pcsx2.git
microVU: fixed various typos
git-svn-id: http://pcsx2.googlecode.com/svn/trunk@1017 96395faa-99c1-11dd-bbfe-3dabce05a288
This commit is contained in:
cottonvibes
parent
f32f705d1d
commit
76e8b6586a
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@ -89,7 +89,7 @@ microVUt(void) mVUallocFMAC2b(int& Ft) {
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#define getReg3(reg, _reg_) { \
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mVUloadReg<vuIndex>(reg, (uptr)&mVU->regs->VF[_reg_].UL[0], (1 << (3 - _bc_))); \
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if (CHECK_VU_EXTRA_OVERFLOW) mVUclamp2<vuIndex>(reg, xmmT1, (1 << (3 - _bc_))); \
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mVUunpack_xyzw<vuIndex>(reg, reg, _bc_); \
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mVUunpack_xyzw<vuIndex>(reg, reg, 0); \
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}
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#define getZero3SS(reg) { \
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@ -100,7 +100,7 @@ microVUt(void) mVUallocFMAC2b(int& Ft) {
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#define getZero3(reg) { \
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if (_bc_w) { \
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mVUloadReg<vuIndex>(reg, (uptr)&mVU->regs->VF[0].UL[0], 1); \
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mVUunpack_xyzw<vuIndex>(reg, reg, _bc_); \
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mVUunpack_xyzw<vuIndex>(reg, reg, 0); \
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} \
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else { SSE_XORPS_XMM_to_XMM(reg, reg); } \
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}
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@ -112,7 +112,7 @@ microVUt(void) mVUallocFMAC3a(int& Fd, int& Fs, int& Ft) {
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Fd = xmmFs;
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if (_XYZW_SS) {
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getReg6(Fs, _Fs_);
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if ( (_Ft_ == _Fs_) && ((_X && _bc_x) || (_Y && _bc_y) || (_Z && _bc_w) || (_W && _bc_w)) ) {
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if ( (_Ft_ == _Fs_) && ((_X && _bc_x) || (_Y && _bc_y) || (_Z && _bc_z) || (_W && _bc_w)) ) {
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Ft = Fs;
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}
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else if (!_Ft_) { getZero3SS(Ft); }
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@ -497,7 +497,7 @@ microVUt(void) mVUallocFMAC16b(int& ACCw, int& ACCr) {
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#define getReg9(reg, _reg_) { \
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mVUloadReg<vuIndex>(reg, (uptr)&mVU->regs->VF[_reg_].UL[0], 1); \
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if (CHECK_VU_EXTRA_OVERFLOW) mVUclamp2<vuIndex>(reg, xmmT1, 1); \
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mVUunpack_xyzw<vuIndex>(reg, reg, 3); \
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mVUunpack_xyzw<vuIndex>(reg, reg, 0); \
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}
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microVUt(void) mVUallocFMAC17a(int& Fs, int& Ft) {
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@ -51,7 +51,7 @@
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microVUt(void) mVUanalyzeFMAC1(int Fd, int Fs, int Ft) {
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microVU* mVU = mVUx;
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mVUlog("microVU: FMAC1 Opcode");
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//mVUlog("microVU: FMAC1 Opcode");
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mVUinfo |= _doStatus;
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analyzeReg1(Fs);
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analyzeReg1(Ft);
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@ -64,7 +64,7 @@ microVUt(void) mVUanalyzeFMAC1(int Fd, int Fs, int Ft) {
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microVUt(void) mVUanalyzeFMAC2(int Fs, int Ft) {
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microVU* mVU = mVUx;
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mVUlog("microVU: FMAC2 Opcode");
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//mVUlog("microVU: FMAC2 Opcode");
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analyzeReg1(Fs);
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analyzeReg2(Ft);
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}
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@ -84,7 +84,7 @@ microVUt(void) mVUanalyzeFMAC2(int Fs, int Ft) {
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microVUt(void) mVUanalyzeFMAC3(int Fd, int Fs, int Ft) {
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microVU* mVU = mVUx;
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mVUlog("microVU: FMAC3 Opcode");
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//mVUlog("microVU: FMAC3 Opcode");
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mVUinfo |= _doStatus;
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analyzeReg1(Fs);
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analyzeReg3(Ft);
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@ -101,7 +101,6 @@ microVUt(void) mVUanalyzeFMAC3(int Fd, int Fs, int Ft) {
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microVUt(void) mVUanalyzeFMAC4(int Fs, int Ft) {
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microVU* mVU = mVUx;
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mVUlog("microVU: FMAC4 Opcode");
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analyzeReg1(Fs);
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analyzeReg4(Ft);
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}
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@ -226,7 +225,6 @@ microVUt(void) mVUanalyzeLQ(int Ft, int Is, bool writeIs) {
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microVUt(void) mVUanalyzeSQ(int Fs, int It, bool writeIt) {
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microVU* mVU = mVUx;
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mVUlog("microVU: SQ Opcode");
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analyzeReg1(Fs);
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analyzeVIreg1(It);
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if (writeIt) { analyzeVIreg2(It, 1); }
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@ -296,7 +294,7 @@ microVUt(void) mVUanalyzeMflag(int Is, int It) {
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if (mVUcount < 4) { mVUregs.needExactMatch = 1; }
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int curPC = iPC;
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for (int i = mVUcount, j = 0; i > 1; i--, j++) {
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incPC(-2);
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incPC2(-2);
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if (doStatus) { mVUinfo |= _doMac; if (j >= 3) { break; } }
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}
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iPC = curPC;
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@ -314,7 +312,6 @@ microVUt(void) mVUanalyzeMflag(int Is, int It) {
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microVUt(void) mVUanalyzeXGkick(int Fs, int xCycles) {
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microVU* mVU = mVUx;
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mVUlog("microVU: XGkick Opcode");
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analyzeVIreg1(Fs);
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analyzeXGkick1();
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analyzeXGkick2(xCycles);
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@ -245,6 +245,7 @@ microVUt(void*) __fastcall mVUcompile(u32 startPC, uptr pState) {
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u8* thisPtr = x86Ptr;
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if (startPC > ((vuIndex) ? 0x3fff : 0xfff)) { mVUlog("microVU: invalid startPC"); }
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//startPC &= (vuIndex ? 0x3ff8 : 0xff8);
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//mVUlog("mVUcompile Search");
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// Searches for Existing Compiled Block (if found, then returns; else, compile)
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@ -301,7 +302,7 @@ microVUt(void*) __fastcall mVUcompile(u32 startPC, uptr pState) {
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int x;
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for (x = 0; x < (vuIndex ? (0x3fff/8) : (0xfff/8)); x++) {
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if (isEOB) { x = 0xffff; }
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if (isNOP) { incPC(1); doUpperOp(); if (curI & _Ibit_) { incPC(-1); mVU->iReg = curI; incPC(-1); } }
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if (isNOP) { incPC(1); doUpperOp(); if (curI & _Ibit_) { incPC(-1); mVU->iReg = curI; incPC(1); } }
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else if (!swapOps) { incPC(1); doUpperOp(); incPC(-1); mVUopL<vuIndex, 1>(); incPC(1); }
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else { mVUopL<vuIndex, 1>(); incPC(1); doUpperOp(); }
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@ -721,7 +721,7 @@ microVUf(void) mVU_ILW() {
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else {
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mVUlog("ILW");
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if (!_Fs_) {
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MOVZX32M16toR( gprT1, (uptr)mVU->regs->Mem + getVUmem(_Imm11_) + offsetSS );
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MOVZX32M16toR(gprT1, (uptr)mVU->regs->Mem + getVUmem(_Imm11_) + offsetSS);
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mVUallocVIb<vuIndex>(gprT1, _Ft_);
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}
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else {
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@ -887,6 +887,7 @@ microVUf(void) mVU_SQ() {
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microVU* mVU = mVUx;
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if (!recPass) { mVUanalyzeSQ<vuIndex>(_Fs_, _Ft_, 0); }
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else {
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mVUlog("SQ");
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if (!_Ft_) {
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getReg7(xmmFs, _Fs_);
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mVUsaveReg<vuIndex>(xmmFs, (uptr)mVU->regs->Mem + getVUmem(_Imm11_), _X_Y_Z_W);
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@ -905,6 +906,7 @@ microVUf(void) mVU_SQD() {
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microVU* mVU = mVUx;
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if (!recPass) { mVUanalyzeSQ<vuIndex>(_Fs_, _Ft_, 1); }
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else {
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mVUlog("SQD");
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if (!_Ft_) {
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getReg7(xmmFs, _Fs_);
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mVUsaveReg<vuIndex>(xmmFs, (uptr)mVU->regs->Mem, _X_Y_Z_W);
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@ -924,6 +926,7 @@ microVUf(void) mVU_SQI() {
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microVU* mVU = mVUx;
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if (!recPass) { mVUanalyzeSQ<vuIndex>(_Fs_, _Ft_, 1); }
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else {
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mVUlog("SQI");
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if (!_Ft_) {
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getReg7(xmmFs, _Fs_);
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mVUsaveReg<vuIndex>(xmmFs, (uptr)mVU->regs->Mem, _X_Y_Z_W);
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@ -948,6 +951,7 @@ microVUf(void) mVU_RINIT() {
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microVU* mVU = mVUx;
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if (!recPass) { mVUanalyzeR1<vuIndex>(_Fs_, _Fsf_); }
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else {
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mVUlog("RINIT");
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if (_Fs_ || (_Fsf_ == 3)) {
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getReg8(gprR, _Fs_, _Fsf_);
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AND32ItoR(gprR, 0x007fffff);
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@ -970,13 +974,14 @@ microVUt(void) mVU_RGET_() {
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microVUf(void) mVU_RGET() {
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microVU* mVU = mVUx;
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if (!recPass) { mVUanalyzeR2<vuIndex>(_Ft_, 1); }
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else { mVU_RGET_<vuIndex>(); }
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else { mVUlog("RGET"); mVU_RGET_<vuIndex>(); }
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}
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microVUf(void) mVU_RNEXT() {
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microVU* mVU = mVUx;
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if (!recPass) { mVUanalyzeR2<vuIndex>(_Ft_, 0); }
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else {
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mVUlog("RNEXT");
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// algorithm from www.project-fao.org
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MOV32RtoR(gprT1, gprR);
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SHR32ItoR(gprT1, 4);
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@ -999,6 +1004,7 @@ microVUf(void) mVU_RXOR() {
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microVU* mVU = mVUx;
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if (!recPass) { mVUanalyzeR1<vuIndex>(_Fs_, _Fsf_); }
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else {
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mVUlog("RXOR");
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if (_Fs_ || (_Fsf_ == 3)) {
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getReg8(gprT1, _Fs_, _Fsf_);
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AND32ItoR(gprT1, 0x7fffff);
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@ -1059,6 +1065,7 @@ microVUf(void) mVU_XGKICK() {
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microVU* mVU = mVUx;
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if (!recPass) { mVUanalyzeXGkick<vuIndex>(_Fs_, 4); }
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else {
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mVUlog("XGkick");
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mVUallocVIa<vuIndex>(gprT2, _Fs_); // gprT2 = ECX for __fastcall
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PUSH32R(gprR); // gprR = EDX is volatile so backup
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CALLFunc((uptr)mVU_XGKICK_);
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@ -226,7 +226,7 @@ declareAllVariables
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#define mmVI(_VIreg_) (_VIreg_ - 1)
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#ifdef mVUdebug
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#define mVUlog Console::Notice
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#define mVUlog Console::Status
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#define mVUdebug1() { \
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if (curI & _Ibit_) { SysPrintf("microVU: I-bit set!\n"); } \
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if (curI & _Ebit_) { SysPrintf("microVU: E-bit set!\n"); } \
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@ -747,8 +747,11 @@ microVUf(void) mVULowerOP_T3_00() { doTableStuff(mVULowerOP_T3_00_OPCODE, ((mVUg
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microVUf(void) mVULowerOP_T3_01() { doTableStuff(mVULowerOP_T3_01_OPCODE, ((mVUgetCode >> 6) & 0x1f)); }
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microVUf(void) mVULowerOP_T3_10() { doTableStuff(mVULowerOP_T3_10_OPCODE, ((mVUgetCode >> 6) & 0x1f)); }
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microVUf(void) mVULowerOP_T3_11() { doTableStuff(mVULowerOP_T3_11_OPCODE, ((mVUgetCode >> 6) & 0x1f)); }
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microVUf(void) mVUunknown() { SysPrintf("mVUunknown<%d,%d> : Unknown Micro VU opcode called\n", vuIndex, recPass); }
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microVUf(void) mVUopU() { doTableStuff(mVU_UPPER_OPCODE, (mVUgetCode & 0x3f)); } // Gets Upper Opcode
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microVUf(void) mVUopL() { doTableStuff(mVULOWER_OPCODE, (mVUgetCode >> 25)); } // Gets Lower Opcode
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microVUf(void) mVUunknown() {
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//if (recPass) return;
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SysPrintf("mVUunknown<%d,%d> : Unknown Micro VU opcode called (%x)\n", vuIndex, recPass, mVUgetCode);
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}
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#endif //PCSX2_MICROVU
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@ -52,7 +52,7 @@ microVUt(void) mVUupdateFlags(int reg, int regT1, int regT2, int xyzw, bool modX
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SSE_MOVMSKPS_XMM_to_R32(mReg, regT2); // Move the sign bits of the t1reg
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AND16ItoR(mReg, AND_XYZW ); // Grab "Is Signed" bits from the previous calculation
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AND16ItoR(mReg, AND_XYZW); // Grab "Is Signed" bits from the previous calculation
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pjmp = JZ8(0); // Skip if none are
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if (doMac) SHL16ItoR(mReg, 4 + ADD_XYZW);
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if (doStatus) OR16ItoR(sReg, 0x82); // SS, S flags
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@ -61,7 +61,7 @@ microVUt(void) mVUupdateFlags(int reg, int regT1, int regT2, int xyzw, bool modX
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//-------------------------Check for Zero flags------------------------------
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AND16ItoR(gprT2, AND_XYZW ); // Grab "Is Zero" bits from the previous calculation
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AND16ItoR(gprT2, AND_XYZW); // Grab "Is Zero" bits from the previous calculation
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pjmp = JZ8(0); // Skip if none are
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if (doMac) { SHIFT_XYZW(gprT2); OR32RtoR(mReg, gprT2); }
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if (doStatus) { OR16ItoR(sReg, 0x41); } // ZS, Z flags
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@ -450,100 +450,97 @@ microVUf(void) mVU_ABS() {
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mVUallocFMAC2b<vuIndex>(Ft);
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}
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}
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microVUf(void) mVU_ADD() { mVU_FMAC1(ADD); }
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microVUf(void) mVU_ADDi() { mVU_FMAC6(ADD); }
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microVUf(void) mVU_ADDq() { mVU_FMAC22(ADD); }
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microVUf(void) mVU_ADDx() { mVU_FMAC3(ADD); }
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microVUf(void) mVU_ADDy() { mVU_FMAC3(ADD); }
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microVUf(void) mVU_ADDz() { mVU_FMAC3(ADD); }
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microVUf(void) mVU_ADDw() { mVU_FMAC3(ADD); }
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microVUf(void) mVU_ADDA() { mVU_FMAC4(ADD); }
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microVUf(void) mVU_ADDAi() { mVU_FMAC7(ADD); }
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microVUf(void) mVU_ADDAq() { mVU_FMAC23(ADD); }
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microVUf(void) mVU_ADDAx() { mVU_FMAC5(ADD); }
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microVUf(void) mVU_ADDAy() { mVU_FMAC5(ADD); }
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microVUf(void) mVU_ADDAz() { mVU_FMAC5(ADD); }
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microVUf(void) mVU_ADDAw() { mVU_FMAC5(ADD); }
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microVUf(void) mVU_SUB() { mVU_FMAC1(SUB); }
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microVUf(void) mVU_SUBi() { mVU_FMAC6(SUB); }
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microVUf(void) mVU_SUBq() { mVU_FMAC22(SUB); }
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microVUf(void) mVU_SUBx() { mVU_FMAC3(SUB); }
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microVUf(void) mVU_SUBy() { mVU_FMAC3(SUB); }
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microVUf(void) mVU_SUBz() { mVU_FMAC3(SUB); }
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microVUf(void) mVU_SUBw() { mVU_FMAC3(SUB); }
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microVUf(void) mVU_SUBA() { mVU_FMAC4(SUB); }
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microVUf(void) mVU_SUBAi() { mVU_FMAC7(SUB); }
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microVUf(void) mVU_SUBAq() { mVU_FMAC23(SUB); }
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microVUf(void) mVU_SUBAx() { mVU_FMAC5(SUB); }
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microVUf(void) mVU_SUBAy() { mVU_FMAC5(SUB); }
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microVUf(void) mVU_SUBAz() { mVU_FMAC5(SUB); }
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microVUf(void) mVU_SUBAw() { mVU_FMAC5(SUB); }
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microVUf(void) mVU_MUL() { mVU_FMAC1(MUL); }
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microVUf(void) mVU_MULi() { mVU_FMAC6(MUL); }
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microVUf(void) mVU_MULq() { mVU_FMAC22(MUL); }
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microVUf(void) mVU_MULx() { mVU_FMAC3(MUL); }
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microVUf(void) mVU_MULy() { mVU_FMAC3(MUL); }
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microVUf(void) mVU_MULz() { mVU_FMAC3(MUL); }
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microVUf(void) mVU_MULw() { mVU_FMAC3(MUL); }
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microVUf(void) mVU_MULA() { mVU_FMAC4(MUL); }
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microVUf(void) mVU_MULAi() { mVU_FMAC7(MUL); }
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microVUf(void) mVU_MULAq() { mVU_FMAC23(MUL); }
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microVUf(void) mVU_MULAx() { mVU_FMAC5(MUL); }
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microVUf(void) mVU_MULAy() { mVU_FMAC5(MUL); }
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microVUf(void) mVU_MULAz() { mVU_FMAC5(MUL); }
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microVUf(void) mVU_MULAw() { mVU_FMAC5(MUL); }
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microVUf(void) mVU_MADD() { mVU_FMAC8(ADD); }
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microVUf(void) mVU_MADDi() { mVU_FMAC12(ADD); }
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microVUf(void) mVU_MADDq() { mVU_FMAC24(ADD); }
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microVUf(void) mVU_MADDx() { mVU_FMAC10(ADD); }
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microVUf(void) mVU_MADDy() { mVU_FMAC10(ADD); }
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microVUf(void) mVU_MADDz() { mVU_FMAC10(ADD); }
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microVUf(void) mVU_MADDw() { mVU_FMAC10(ADD); }
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microVUf(void) mVU_MADDA() { mVU_FMAC14(ADD); }
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microVUf(void) mVU_MADDAi() { mVU_FMAC16(ADD); }
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microVUf(void) mVU_MADDAq() { mVU_FMAC26(ADD); }
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microVUf(void) mVU_MADDAx() { mVU_FMAC15(ADD); }
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microVUf(void) mVU_MADDAy() { mVU_FMAC15(ADD); }
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microVUf(void) mVU_MADDAz() { mVU_FMAC15(ADD); }
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microVUf(void) mVU_MADDAw() { mVU_FMAC15(ADD); }
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microVUf(void) mVU_MSUB() { mVU_FMAC9(SUB); }
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microVUf(void) mVU_MSUBi() { mVU_FMAC13(SUB); }
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microVUf(void) mVU_MSUBq() { mVU_FMAC25(SUB); }
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||||
microVUf(void) mVU_MSUBx() { mVU_FMAC11(SUB); }
|
||||
microVUf(void) mVU_MSUBy() { mVU_FMAC11(SUB); }
|
||||
microVUf(void) mVU_MSUBz() { mVU_FMAC11(SUB); }
|
||||
microVUf(void) mVU_MSUBw() { mVU_FMAC11(SUB); }
|
||||
microVUf(void) mVU_MSUBA() { mVU_FMAC14(SUB); }
|
||||
microVUf(void) mVU_MSUBAi() { mVU_FMAC16(SUB); }
|
||||
microVUf(void) mVU_MSUBAq() { mVU_FMAC26(SUB); }
|
||||
microVUf(void) mVU_MSUBAx() { mVU_FMAC15(SUB); }
|
||||
microVUf(void) mVU_MSUBAy() { mVU_FMAC15(SUB); }
|
||||
microVUf(void) mVU_MSUBAz() { mVU_FMAC15(SUB); }
|
||||
microVUf(void) mVU_MSUBAw() { mVU_FMAC15(SUB); }
|
||||
microVUf(void) mVU_MAX() { mVU_FMAC1(MAX); }
|
||||
microVUf(void) mVU_MAXi() { mVU_FMAC6(MAX); }
|
||||
microVUf(void) mVU_MAXx() { mVU_FMAC3(MAX); }
|
||||
microVUf(void) mVU_MAXy() { mVU_FMAC3(MAX); }
|
||||
microVUf(void) mVU_MAXz() { mVU_FMAC3(MAX); }
|
||||
microVUf(void) mVU_MAXw() { mVU_FMAC3(MAX); }
|
||||
microVUf(void) mVU_MINI() { mVU_FMAC1(MIN); }
|
||||
microVUf(void) mVU_MINIi() { mVU_FMAC6(MIN); }
|
||||
microVUf(void) mVU_MINIx() { mVU_FMAC3(MIN); }
|
||||
microVUf(void) mVU_MINIy() { mVU_FMAC3(MIN); }
|
||||
microVUf(void) mVU_MINIz() { mVU_FMAC3(MIN); }
|
||||
microVUf(void) mVU_MINIw() { mVU_FMAC3(MIN); }
|
||||
microVUf(void) mVU_OPMULA() { mVU_FMAC18(MUL); }
|
||||
microVUf(void) mVU_OPMSUB() { mVU_FMAC19(SUB); }
|
||||
microVUf(void) mVU_NOP() {
|
||||
microVU* mVU = mVUx;
|
||||
if (!recPass) {}
|
||||
else {}
|
||||
}
|
||||
microVUf(void) mVU_ADD() { mVU_FMAC1(ADD); mVUlog("ADD"); }
|
||||
microVUf(void) mVU_ADDi() { mVU_FMAC6(ADD); mVUlog("ADDi"); }
|
||||
microVUf(void) mVU_ADDq() { mVU_FMAC22(ADD); mVUlog("ADDq"); }
|
||||
microVUf(void) mVU_ADDx() { mVU_FMAC3(ADD); mVUlog("ADDx"); }
|
||||
microVUf(void) mVU_ADDy() { mVU_FMAC3(ADD); mVUlog("ADDy"); }
|
||||
microVUf(void) mVU_ADDz() { mVU_FMAC3(ADD); mVUlog("ADDz"); }
|
||||
microVUf(void) mVU_ADDw() { mVU_FMAC3(ADD); mVUlog("ADDw"); }
|
||||
microVUf(void) mVU_ADDA() { mVU_FMAC4(ADD); mVUlog("ADDA"); }
|
||||
microVUf(void) mVU_ADDAi() { mVU_FMAC7(ADD); mVUlog("ADDAi"); }
|
||||
microVUf(void) mVU_ADDAq() { mVU_FMAC23(ADD); mVUlog("ADDAq"); }
|
||||
microVUf(void) mVU_ADDAx() { mVU_FMAC5(ADD); mVUlog("ADDAx"); }
|
||||
microVUf(void) mVU_ADDAy() { mVU_FMAC5(ADD); mVUlog("ADDAy"); }
|
||||
microVUf(void) mVU_ADDAz() { mVU_FMAC5(ADD); mVUlog("ADDAz"); }
|
||||
microVUf(void) mVU_ADDAw() { mVU_FMAC5(ADD); mVUlog("ADDAw"); }
|
||||
microVUf(void) mVU_SUB() { mVU_FMAC1(SUB); mVUlog("SUB"); }
|
||||
microVUf(void) mVU_SUBi() { mVU_FMAC6(SUB); mVUlog("SUBi"); }
|
||||
microVUf(void) mVU_SUBq() { mVU_FMAC22(SUB); mVUlog("SUBq"); }
|
||||
microVUf(void) mVU_SUBx() { mVU_FMAC3(SUB); mVUlog("SUBx"); }
|
||||
microVUf(void) mVU_SUBy() { mVU_FMAC3(SUB); mVUlog("SUBy"); }
|
||||
microVUf(void) mVU_SUBz() { mVU_FMAC3(SUB); mVUlog("SUBz"); }
|
||||
microVUf(void) mVU_SUBw() { mVU_FMAC3(SUB); mVUlog("SUBw"); }
|
||||
microVUf(void) mVU_SUBA() { mVU_FMAC4(SUB); mVUlog("SUBA"); }
|
||||
microVUf(void) mVU_SUBAi() { mVU_FMAC7(SUB); mVUlog("SUBAi"); }
|
||||
microVUf(void) mVU_SUBAq() { mVU_FMAC23(SUB); mVUlog("SUBAq"); }
|
||||
microVUf(void) mVU_SUBAx() { mVU_FMAC5(SUB); mVUlog("SUBAx"); }
|
||||
microVUf(void) mVU_SUBAy() { mVU_FMAC5(SUB); mVUlog("SUBAy"); }
|
||||
microVUf(void) mVU_SUBAz() { mVU_FMAC5(SUB); mVUlog("SUBAz"); }
|
||||
microVUf(void) mVU_SUBAw() { mVU_FMAC5(SUB); mVUlog("SUBAw"); }
|
||||
microVUf(void) mVU_MUL() { mVU_FMAC1(MUL); mVUlog("MUL"); }
|
||||
microVUf(void) mVU_MULi() { mVU_FMAC6(MUL); mVUlog("MULi"); }
|
||||
microVUf(void) mVU_MULq() { mVU_FMAC22(MUL); mVUlog("MULq"); }
|
||||
microVUf(void) mVU_MULx() { mVU_FMAC3(MUL); mVUlog("MULx"); }
|
||||
microVUf(void) mVU_MULy() { mVU_FMAC3(MUL); mVUlog("MULy"); }
|
||||
microVUf(void) mVU_MULz() { mVU_FMAC3(MUL); mVUlog("MULz"); }
|
||||
microVUf(void) mVU_MULw() { mVU_FMAC3(MUL); mVUlog("MULw"); }
|
||||
microVUf(void) mVU_MULA() { mVU_FMAC4(MUL); mVUlog("MULA"); }
|
||||
microVUf(void) mVU_MULAi() { mVU_FMAC7(MUL); mVUlog("MULAi"); }
|
||||
microVUf(void) mVU_MULAq() { mVU_FMAC23(MUL); mVUlog("MULAq"); }
|
||||
microVUf(void) mVU_MULAx() { mVU_FMAC5(MUL); mVUlog("MULAx"); }
|
||||
microVUf(void) mVU_MULAy() { mVU_FMAC5(MUL); mVUlog("MULAy"); }
|
||||
microVUf(void) mVU_MULAz() { mVU_FMAC5(MUL); mVUlog("MULAz"); }
|
||||
microVUf(void) mVU_MULAw() { mVU_FMAC5(MUL); mVUlog("MULAw"); }
|
||||
microVUf(void) mVU_MADD() { mVU_FMAC8(ADD); mVUlog("MADD"); }
|
||||
microVUf(void) mVU_MADDi() { mVU_FMAC12(ADD); mVUlog("MADDi"); }
|
||||
microVUf(void) mVU_MADDq() { mVU_FMAC24(ADD); mVUlog("MADDq"); }
|
||||
microVUf(void) mVU_MADDx() { mVU_FMAC10(ADD); mVUlog("MADDx"); }
|
||||
microVUf(void) mVU_MADDy() { mVU_FMAC10(ADD); mVUlog("MADDy"); }
|
||||
microVUf(void) mVU_MADDz() { mVU_FMAC10(ADD); mVUlog("MADDz"); }
|
||||
microVUf(void) mVU_MADDw() { mVU_FMAC10(ADD); mVUlog("MADDw"); }
|
||||
microVUf(void) mVU_MADDA() { mVU_FMAC14(ADD); mVUlog("MADDA"); }
|
||||
microVUf(void) mVU_MADDAi() { mVU_FMAC16(ADD); mVUlog("MADDAi"); }
|
||||
microVUf(void) mVU_MADDAq() { mVU_FMAC26(ADD); mVUlog("MADDAq"); }
|
||||
microVUf(void) mVU_MADDAx() { mVU_FMAC15(ADD); mVUlog("MADDAx"); }
|
||||
microVUf(void) mVU_MADDAy() { mVU_FMAC15(ADD); mVUlog("MADDAy"); }
|
||||
microVUf(void) mVU_MADDAz() { mVU_FMAC15(ADD); mVUlog("MADDAz"); }
|
||||
microVUf(void) mVU_MADDAw() { mVU_FMAC15(ADD); mVUlog("MADDAw"); }
|
||||
microVUf(void) mVU_MSUB() { mVU_FMAC9(SUB); mVUlog("MSUB"); }
|
||||
microVUf(void) mVU_MSUBi() { mVU_FMAC13(SUB); mVUlog("MSUBi"); }
|
||||
microVUf(void) mVU_MSUBq() { mVU_FMAC25(SUB); mVUlog("MSUBq"); }
|
||||
microVUf(void) mVU_MSUBx() { mVU_FMAC11(SUB); mVUlog("MSUBx"); }
|
||||
microVUf(void) mVU_MSUBy() { mVU_FMAC11(SUB); mVUlog("MSUBy"); }
|
||||
microVUf(void) mVU_MSUBz() { mVU_FMAC11(SUB); mVUlog("MSUBz"); }
|
||||
microVUf(void) mVU_MSUBw() { mVU_FMAC11(SUB); mVUlog("MSUBw"); }
|
||||
microVUf(void) mVU_MSUBA() { mVU_FMAC14(SUB); mVUlog("MSUBA"); }
|
||||
microVUf(void) mVU_MSUBAi() { mVU_FMAC16(SUB); mVUlog("MSUBAi"); }
|
||||
microVUf(void) mVU_MSUBAq() { mVU_FMAC26(SUB); mVUlog("MSUBAq"); }
|
||||
microVUf(void) mVU_MSUBAx() { mVU_FMAC15(SUB); mVUlog("MSUBAx"); }
|
||||
microVUf(void) mVU_MSUBAy() { mVU_FMAC15(SUB); mVUlog("MSUBAy"); }
|
||||
microVUf(void) mVU_MSUBAz() { mVU_FMAC15(SUB); mVUlog("MSUBAz"); }
|
||||
microVUf(void) mVU_MSUBAw() { mVU_FMAC15(SUB); mVUlog("MSUBAw"); }
|
||||
microVUf(void) mVU_MAX() { mVU_FMAC1(MAX); mVUlog("MAX"); }
|
||||
microVUf(void) mVU_MAXi() { mVU_FMAC6(MAX); mVUlog("MAXi"); }
|
||||
microVUf(void) mVU_MAXx() { mVU_FMAC3(MAX); mVUlog("MAXq"); }
|
||||
microVUf(void) mVU_MAXy() { mVU_FMAC3(MAX); mVUlog("MAXy"); }
|
||||
microVUf(void) mVU_MAXz() { mVU_FMAC3(MAX); mVUlog("MAXz"); }
|
||||
microVUf(void) mVU_MAXw() { mVU_FMAC3(MAX); mVUlog("MAXw"); }
|
||||
microVUf(void) mVU_MINI() { mVU_FMAC1(MIN); mVUlog("MINI"); }
|
||||
microVUf(void) mVU_MINIi() { mVU_FMAC6(MIN); mVUlog("MINIi"); }
|
||||
microVUf(void) mVU_MINIx() { mVU_FMAC3(MIN); mVUlog("MINIx"); }
|
||||
microVUf(void) mVU_MINIy() { mVU_FMAC3(MIN); mVUlog("MINIy"); }
|
||||
microVUf(void) mVU_MINIz() { mVU_FMAC3(MIN); mVUlog("MINIz"); }
|
||||
microVUf(void) mVU_MINIw() { mVU_FMAC3(MIN); mVUlog("MINIw"); }
|
||||
microVUf(void) mVU_OPMULA() { mVU_FMAC18(MUL); mVUlog("OPMULA"); }
|
||||
microVUf(void) mVU_OPMSUB() { mVU_FMAC19(SUB); mVUlog("OPMSUB"); }
|
||||
microVUf(void) mVU_NOP() { /*mVUlog("NOP");*/ }
|
||||
microVUq(void) mVU_FTOIx(uptr addr) {
|
||||
microVU* mVU = mVUx;
|
||||
if (!recPass) { mVUanalyzeFMAC2<vuIndex>(_Fs_, _Ft_); }
|
||||
else {
|
||||
int Fs, Ft;
|
||||
mVUlog("FTOIx");
|
||||
mVUallocFMAC2a<vuIndex>(Fs, Ft);
|
||||
|
||||
// Note: For help understanding this algorithm see recVUMI_FTOI_Saturate()
|
||||
|
|
@ -569,6 +566,7 @@ microVUq(void) mVU_ITOFx(uptr addr) {
|
|||
if (!recPass) { mVUanalyzeFMAC2<vuIndex>(_Fs_, _Ft_); }
|
||||
else {
|
||||
int Fs, Ft;
|
||||
mVUlog("ITOFx");
|
||||
mVUallocFMAC2a<vuIndex>(Fs, Ft);
|
||||
|
||||
SSE2_CVTDQ2PS_XMM_to_XMM(Ft, Fs);
|
||||
|
|
@ -587,6 +585,7 @@ microVUf(void) mVU_CLIP() {
|
|||
if (!recPass) { mVUanalyzeFMAC4<vuIndex>(_Fs_, _Ft_); mVUlog("clip broken"); }
|
||||
else {
|
||||
int Fs, Ft;
|
||||
mVUlog("CLIP");
|
||||
mVUallocFMAC17a<vuIndex>(Fs, Ft);
|
||||
mVUallocCFLAGa<vuIndex>(gprT1, fpcInstance);
|
||||
SHL32ItoR(gprT1, 6);
|
||||
|
|
|
|||
Loading…
Reference in New Issue