From 76e8b6586aeb51015751ab7079c113093a2c7afb Mon Sep 17 00:00:00 2001 From: cottonvibes Date: Sun, 19 Apr 2009 05:49:16 +0000 Subject: [PATCH] microVU: fixed various typos git-svn-id: http://pcsx2.googlecode.com/svn/trunk@1017 96395faa-99c1-11dd-bbfe-3dabce05a288 --- pcsx2/x86/microVU_Alloc.inl | 8 +- pcsx2/x86/microVU_Analyze.inl | 11 +-- pcsx2/x86/microVU_Compile.inl | 3 +- pcsx2/x86/microVU_Lower.inl | 11 ++- pcsx2/x86/microVU_Misc.h | 2 +- pcsx2/x86/microVU_Tables.inl | 5 +- pcsx2/x86/microVU_Upper.inl | 181 +++++++++++++++++----------------- 7 files changed, 114 insertions(+), 107 deletions(-) diff --git a/pcsx2/x86/microVU_Alloc.inl b/pcsx2/x86/microVU_Alloc.inl index c31522eb88..1591091b3b 100644 --- a/pcsx2/x86/microVU_Alloc.inl +++ b/pcsx2/x86/microVU_Alloc.inl @@ -89,7 +89,7 @@ microVUt(void) mVUallocFMAC2b(int& Ft) { #define getReg3(reg, _reg_) { \ mVUloadReg(reg, (uptr)&mVU->regs->VF[_reg_].UL[0], (1 << (3 - _bc_))); \ if (CHECK_VU_EXTRA_OVERFLOW) mVUclamp2(reg, xmmT1, (1 << (3 - _bc_))); \ - mVUunpack_xyzw(reg, reg, _bc_); \ + mVUunpack_xyzw(reg, reg, 0); \ } #define getZero3SS(reg) { \ @@ -100,7 +100,7 @@ microVUt(void) mVUallocFMAC2b(int& Ft) { #define getZero3(reg) { \ if (_bc_w) { \ mVUloadReg(reg, (uptr)&mVU->regs->VF[0].UL[0], 1); \ - mVUunpack_xyzw(reg, reg, _bc_); \ + mVUunpack_xyzw(reg, reg, 0); \ } \ else { SSE_XORPS_XMM_to_XMM(reg, reg); } \ } @@ -112,7 +112,7 @@ microVUt(void) mVUallocFMAC3a(int& Fd, int& Fs, int& Ft) { Fd = xmmFs; if (_XYZW_SS) { getReg6(Fs, _Fs_); - if ( (_Ft_ == _Fs_) && ((_X && _bc_x) || (_Y && _bc_y) || (_Z && _bc_w) || (_W && _bc_w)) ) { + if ( (_Ft_ == _Fs_) && ((_X && _bc_x) || (_Y && _bc_y) || (_Z && _bc_z) || (_W && _bc_w)) ) { Ft = Fs; } else if (!_Ft_) { getZero3SS(Ft); } @@ -497,7 +497,7 @@ microVUt(void) mVUallocFMAC16b(int& ACCw, int& ACCr) { #define getReg9(reg, _reg_) { \ mVUloadReg(reg, (uptr)&mVU->regs->VF[_reg_].UL[0], 1); \ if (CHECK_VU_EXTRA_OVERFLOW) mVUclamp2(reg, xmmT1, 1); \ - mVUunpack_xyzw(reg, reg, 3); \ + mVUunpack_xyzw(reg, reg, 0); \ } microVUt(void) mVUallocFMAC17a(int& Fs, int& Ft) { diff --git a/pcsx2/x86/microVU_Analyze.inl b/pcsx2/x86/microVU_Analyze.inl index 4581d937fd..506144262b 100644 --- a/pcsx2/x86/microVU_Analyze.inl +++ b/pcsx2/x86/microVU_Analyze.inl @@ -51,7 +51,7 @@ microVUt(void) mVUanalyzeFMAC1(int Fd, int Fs, int Ft) { microVU* mVU = mVUx; - mVUlog("microVU: FMAC1 Opcode"); + //mVUlog("microVU: FMAC1 Opcode"); mVUinfo |= _doStatus; analyzeReg1(Fs); analyzeReg1(Ft); @@ -64,7 +64,7 @@ microVUt(void) mVUanalyzeFMAC1(int Fd, int Fs, int Ft) { microVUt(void) mVUanalyzeFMAC2(int Fs, int Ft) { microVU* mVU = mVUx; - mVUlog("microVU: FMAC2 Opcode"); + //mVUlog("microVU: FMAC2 Opcode"); analyzeReg1(Fs); analyzeReg2(Ft); } @@ -84,7 +84,7 @@ microVUt(void) mVUanalyzeFMAC2(int Fs, int Ft) { microVUt(void) mVUanalyzeFMAC3(int Fd, int Fs, int Ft) { microVU* mVU = mVUx; - mVUlog("microVU: FMAC3 Opcode"); + //mVUlog("microVU: FMAC3 Opcode"); mVUinfo |= _doStatus; analyzeReg1(Fs); analyzeReg3(Ft); @@ -101,7 +101,6 @@ microVUt(void) mVUanalyzeFMAC3(int Fd, int Fs, int Ft) { microVUt(void) mVUanalyzeFMAC4(int Fs, int Ft) { microVU* mVU = mVUx; - mVUlog("microVU: FMAC4 Opcode"); analyzeReg1(Fs); analyzeReg4(Ft); } @@ -226,7 +225,6 @@ microVUt(void) mVUanalyzeLQ(int Ft, int Is, bool writeIs) { microVUt(void) mVUanalyzeSQ(int Fs, int It, bool writeIt) { microVU* mVU = mVUx; - mVUlog("microVU: SQ Opcode"); analyzeReg1(Fs); analyzeVIreg1(It); if (writeIt) { analyzeVIreg2(It, 1); } @@ -296,7 +294,7 @@ microVUt(void) mVUanalyzeMflag(int Is, int It) { if (mVUcount < 4) { mVUregs.needExactMatch = 1; } int curPC = iPC; for (int i = mVUcount, j = 0; i > 1; i--, j++) { - incPC(-2); + incPC2(-2); if (doStatus) { mVUinfo |= _doMac; if (j >= 3) { break; } } } iPC = curPC; @@ -314,7 +312,6 @@ microVUt(void) mVUanalyzeMflag(int Is, int It) { microVUt(void) mVUanalyzeXGkick(int Fs, int xCycles) { microVU* mVU = mVUx; - mVUlog("microVU: XGkick Opcode"); analyzeVIreg1(Fs); analyzeXGkick1(); analyzeXGkick2(xCycles); diff --git a/pcsx2/x86/microVU_Compile.inl b/pcsx2/x86/microVU_Compile.inl index ad468e62f7..15b3a145be 100644 --- a/pcsx2/x86/microVU_Compile.inl +++ b/pcsx2/x86/microVU_Compile.inl @@ -245,6 +245,7 @@ microVUt(void*) __fastcall mVUcompile(u32 startPC, uptr pState) { u8* thisPtr = x86Ptr; if (startPC > ((vuIndex) ? 0x3fff : 0xfff)) { mVUlog("microVU: invalid startPC"); } + //startPC &= (vuIndex ? 0x3ff8 : 0xff8); //mVUlog("mVUcompile Search"); // Searches for Existing Compiled Block (if found, then returns; else, compile) @@ -301,7 +302,7 @@ microVUt(void*) __fastcall mVUcompile(u32 startPC, uptr pState) { int x; for (x = 0; x < (vuIndex ? (0x3fff/8) : (0xfff/8)); x++) { if (isEOB) { x = 0xffff; } - if (isNOP) { incPC(1); doUpperOp(); if (curI & _Ibit_) { incPC(-1); mVU->iReg = curI; incPC(-1); } } + if (isNOP) { incPC(1); doUpperOp(); if (curI & _Ibit_) { incPC(-1); mVU->iReg = curI; incPC(1); } } else if (!swapOps) { incPC(1); doUpperOp(); incPC(-1); mVUopL(); incPC(1); } else { mVUopL(); incPC(1); doUpperOp(); } diff --git a/pcsx2/x86/microVU_Lower.inl b/pcsx2/x86/microVU_Lower.inl index 7c00a6b7a6..c70ce5f6aa 100644 --- a/pcsx2/x86/microVU_Lower.inl +++ b/pcsx2/x86/microVU_Lower.inl @@ -721,7 +721,7 @@ microVUf(void) mVU_ILW() { else { mVUlog("ILW"); if (!_Fs_) { - MOVZX32M16toR( gprT1, (uptr)mVU->regs->Mem + getVUmem(_Imm11_) + offsetSS ); + MOVZX32M16toR(gprT1, (uptr)mVU->regs->Mem + getVUmem(_Imm11_) + offsetSS); mVUallocVIb(gprT1, _Ft_); } else { @@ -887,6 +887,7 @@ microVUf(void) mVU_SQ() { microVU* mVU = mVUx; if (!recPass) { mVUanalyzeSQ(_Fs_, _Ft_, 0); } else { + mVUlog("SQ"); if (!_Ft_) { getReg7(xmmFs, _Fs_); mVUsaveReg(xmmFs, (uptr)mVU->regs->Mem + getVUmem(_Imm11_), _X_Y_Z_W); @@ -905,6 +906,7 @@ microVUf(void) mVU_SQD() { microVU* mVU = mVUx; if (!recPass) { mVUanalyzeSQ(_Fs_, _Ft_, 1); } else { + mVUlog("SQD"); if (!_Ft_) { getReg7(xmmFs, _Fs_); mVUsaveReg(xmmFs, (uptr)mVU->regs->Mem, _X_Y_Z_W); @@ -924,6 +926,7 @@ microVUf(void) mVU_SQI() { microVU* mVU = mVUx; if (!recPass) { mVUanalyzeSQ(_Fs_, _Ft_, 1); } else { + mVUlog("SQI"); if (!_Ft_) { getReg7(xmmFs, _Fs_); mVUsaveReg(xmmFs, (uptr)mVU->regs->Mem, _X_Y_Z_W); @@ -948,6 +951,7 @@ microVUf(void) mVU_RINIT() { microVU* mVU = mVUx; if (!recPass) { mVUanalyzeR1(_Fs_, _Fsf_); } else { + mVUlog("RINIT"); if (_Fs_ || (_Fsf_ == 3)) { getReg8(gprR, _Fs_, _Fsf_); AND32ItoR(gprR, 0x007fffff); @@ -970,13 +974,14 @@ microVUt(void) mVU_RGET_() { microVUf(void) mVU_RGET() { microVU* mVU = mVUx; if (!recPass) { mVUanalyzeR2(_Ft_, 1); } - else { mVU_RGET_(); } + else { mVUlog("RGET"); mVU_RGET_(); } } microVUf(void) mVU_RNEXT() { microVU* mVU = mVUx; if (!recPass) { mVUanalyzeR2(_Ft_, 0); } else { + mVUlog("RNEXT"); // algorithm from www.project-fao.org MOV32RtoR(gprT1, gprR); SHR32ItoR(gprT1, 4); @@ -999,6 +1004,7 @@ microVUf(void) mVU_RXOR() { microVU* mVU = mVUx; if (!recPass) { mVUanalyzeR1(_Fs_, _Fsf_); } else { + mVUlog("RXOR"); if (_Fs_ || (_Fsf_ == 3)) { getReg8(gprT1, _Fs_, _Fsf_); AND32ItoR(gprT1, 0x7fffff); @@ -1059,6 +1065,7 @@ microVUf(void) mVU_XGKICK() { microVU* mVU = mVUx; if (!recPass) { mVUanalyzeXGkick(_Fs_, 4); } else { + mVUlog("XGkick"); mVUallocVIa(gprT2, _Fs_); // gprT2 = ECX for __fastcall PUSH32R(gprR); // gprR = EDX is volatile so backup CALLFunc((uptr)mVU_XGKICK_); diff --git a/pcsx2/x86/microVU_Misc.h b/pcsx2/x86/microVU_Misc.h index 7937d2990b..2f0ea1c8ad 100644 --- a/pcsx2/x86/microVU_Misc.h +++ b/pcsx2/x86/microVU_Misc.h @@ -226,7 +226,7 @@ declareAllVariables #define mmVI(_VIreg_) (_VIreg_ - 1) #ifdef mVUdebug -#define mVUlog Console::Notice +#define mVUlog Console::Status #define mVUdebug1() { \ if (curI & _Ibit_) { SysPrintf("microVU: I-bit set!\n"); } \ if (curI & _Ebit_) { SysPrintf("microVU: E-bit set!\n"); } \ diff --git a/pcsx2/x86/microVU_Tables.inl b/pcsx2/x86/microVU_Tables.inl index d79cd3c74a..c6e76ab38e 100644 --- a/pcsx2/x86/microVU_Tables.inl +++ b/pcsx2/x86/microVU_Tables.inl @@ -747,8 +747,11 @@ microVUf(void) mVULowerOP_T3_00() { doTableStuff(mVULowerOP_T3_00_OPCODE, ((mVUg microVUf(void) mVULowerOP_T3_01() { doTableStuff(mVULowerOP_T3_01_OPCODE, ((mVUgetCode >> 6) & 0x1f)); } microVUf(void) mVULowerOP_T3_10() { doTableStuff(mVULowerOP_T3_10_OPCODE, ((mVUgetCode >> 6) & 0x1f)); } microVUf(void) mVULowerOP_T3_11() { doTableStuff(mVULowerOP_T3_11_OPCODE, ((mVUgetCode >> 6) & 0x1f)); } -microVUf(void) mVUunknown() { SysPrintf("mVUunknown<%d,%d> : Unknown Micro VU opcode called\n", vuIndex, recPass); } microVUf(void) mVUopU() { doTableStuff(mVU_UPPER_OPCODE, (mVUgetCode & 0x3f)); } // Gets Upper Opcode microVUf(void) mVUopL() { doTableStuff(mVULOWER_OPCODE, (mVUgetCode >> 25)); } // Gets Lower Opcode +microVUf(void) mVUunknown() { + //if (recPass) return; + SysPrintf("mVUunknown<%d,%d> : Unknown Micro VU opcode called (%x)\n", vuIndex, recPass, mVUgetCode); +} #endif //PCSX2_MICROVU diff --git a/pcsx2/x86/microVU_Upper.inl b/pcsx2/x86/microVU_Upper.inl index 94582273f9..dcbc757a13 100644 --- a/pcsx2/x86/microVU_Upper.inl +++ b/pcsx2/x86/microVU_Upper.inl @@ -52,7 +52,7 @@ microVUt(void) mVUupdateFlags(int reg, int regT1, int regT2, int xyzw, bool modX SSE_MOVMSKPS_XMM_to_R32(mReg, regT2); // Move the sign bits of the t1reg - AND16ItoR(mReg, AND_XYZW ); // Grab "Is Signed" bits from the previous calculation + AND16ItoR(mReg, AND_XYZW); // Grab "Is Signed" bits from the previous calculation pjmp = JZ8(0); // Skip if none are if (doMac) SHL16ItoR(mReg, 4 + ADD_XYZW); if (doStatus) OR16ItoR(sReg, 0x82); // SS, S flags @@ -61,7 +61,7 @@ microVUt(void) mVUupdateFlags(int reg, int regT1, int regT2, int xyzw, bool modX //-------------------------Check for Zero flags------------------------------ - AND16ItoR(gprT2, AND_XYZW ); // Grab "Is Zero" bits from the previous calculation + AND16ItoR(gprT2, AND_XYZW); // Grab "Is Zero" bits from the previous calculation pjmp = JZ8(0); // Skip if none are if (doMac) { SHIFT_XYZW(gprT2); OR32RtoR(mReg, gprT2); } if (doStatus) { OR16ItoR(sReg, 0x41); } // ZS, Z flags @@ -450,100 +450,97 @@ microVUf(void) mVU_ABS() { mVUallocFMAC2b(Ft); } } -microVUf(void) mVU_ADD() { mVU_FMAC1(ADD); } -microVUf(void) mVU_ADDi() { mVU_FMAC6(ADD); } -microVUf(void) mVU_ADDq() { mVU_FMAC22(ADD); } -microVUf(void) mVU_ADDx() { mVU_FMAC3(ADD); } -microVUf(void) mVU_ADDy() { mVU_FMAC3(ADD); } -microVUf(void) mVU_ADDz() { mVU_FMAC3(ADD); } -microVUf(void) mVU_ADDw() { mVU_FMAC3(ADD); } -microVUf(void) mVU_ADDA() { mVU_FMAC4(ADD); } -microVUf(void) mVU_ADDAi() { mVU_FMAC7(ADD); } -microVUf(void) mVU_ADDAq() { mVU_FMAC23(ADD); } -microVUf(void) mVU_ADDAx() { mVU_FMAC5(ADD); } -microVUf(void) mVU_ADDAy() { mVU_FMAC5(ADD); } -microVUf(void) mVU_ADDAz() { mVU_FMAC5(ADD); } -microVUf(void) mVU_ADDAw() { mVU_FMAC5(ADD); } -microVUf(void) mVU_SUB() { mVU_FMAC1(SUB); } -microVUf(void) mVU_SUBi() { mVU_FMAC6(SUB); } -microVUf(void) mVU_SUBq() { mVU_FMAC22(SUB); } -microVUf(void) mVU_SUBx() { mVU_FMAC3(SUB); } -microVUf(void) mVU_SUBy() { mVU_FMAC3(SUB); } -microVUf(void) mVU_SUBz() { mVU_FMAC3(SUB); } -microVUf(void) mVU_SUBw() { mVU_FMAC3(SUB); } -microVUf(void) mVU_SUBA() { mVU_FMAC4(SUB); } -microVUf(void) mVU_SUBAi() { mVU_FMAC7(SUB); } -microVUf(void) mVU_SUBAq() { mVU_FMAC23(SUB); } -microVUf(void) mVU_SUBAx() { mVU_FMAC5(SUB); } -microVUf(void) mVU_SUBAy() { mVU_FMAC5(SUB); } -microVUf(void) mVU_SUBAz() { mVU_FMAC5(SUB); } -microVUf(void) mVU_SUBAw() { mVU_FMAC5(SUB); } -microVUf(void) mVU_MUL() { mVU_FMAC1(MUL); } -microVUf(void) mVU_MULi() { mVU_FMAC6(MUL); } -microVUf(void) mVU_MULq() { mVU_FMAC22(MUL); } -microVUf(void) mVU_MULx() { mVU_FMAC3(MUL); } -microVUf(void) mVU_MULy() { mVU_FMAC3(MUL); } -microVUf(void) mVU_MULz() { mVU_FMAC3(MUL); } -microVUf(void) mVU_MULw() { mVU_FMAC3(MUL); } -microVUf(void) mVU_MULA() { mVU_FMAC4(MUL); } -microVUf(void) mVU_MULAi() { mVU_FMAC7(MUL); } -microVUf(void) mVU_MULAq() { mVU_FMAC23(MUL); } -microVUf(void) mVU_MULAx() { mVU_FMAC5(MUL); } -microVUf(void) mVU_MULAy() { mVU_FMAC5(MUL); } -microVUf(void) mVU_MULAz() { mVU_FMAC5(MUL); } -microVUf(void) mVU_MULAw() { mVU_FMAC5(MUL); } -microVUf(void) mVU_MADD() { mVU_FMAC8(ADD); } -microVUf(void) mVU_MADDi() { mVU_FMAC12(ADD); } -microVUf(void) mVU_MADDq() { mVU_FMAC24(ADD); } -microVUf(void) mVU_MADDx() { mVU_FMAC10(ADD); } -microVUf(void) mVU_MADDy() { mVU_FMAC10(ADD); } -microVUf(void) mVU_MADDz() { mVU_FMAC10(ADD); } -microVUf(void) mVU_MADDw() { mVU_FMAC10(ADD); } -microVUf(void) mVU_MADDA() { mVU_FMAC14(ADD); } -microVUf(void) mVU_MADDAi() { mVU_FMAC16(ADD); } -microVUf(void) mVU_MADDAq() { mVU_FMAC26(ADD); } -microVUf(void) mVU_MADDAx() { mVU_FMAC15(ADD); } -microVUf(void) mVU_MADDAy() { mVU_FMAC15(ADD); } -microVUf(void) mVU_MADDAz() { mVU_FMAC15(ADD); } -microVUf(void) mVU_MADDAw() { mVU_FMAC15(ADD); } -microVUf(void) mVU_MSUB() { mVU_FMAC9(SUB); } -microVUf(void) mVU_MSUBi() { mVU_FMAC13(SUB); } -microVUf(void) mVU_MSUBq() { mVU_FMAC25(SUB); } -microVUf(void) mVU_MSUBx() { mVU_FMAC11(SUB); } -microVUf(void) mVU_MSUBy() { mVU_FMAC11(SUB); } -microVUf(void) mVU_MSUBz() { mVU_FMAC11(SUB); } -microVUf(void) mVU_MSUBw() { mVU_FMAC11(SUB); } -microVUf(void) mVU_MSUBA() { mVU_FMAC14(SUB); } -microVUf(void) mVU_MSUBAi() { mVU_FMAC16(SUB); } -microVUf(void) mVU_MSUBAq() { mVU_FMAC26(SUB); } -microVUf(void) mVU_MSUBAx() { mVU_FMAC15(SUB); } -microVUf(void) mVU_MSUBAy() { mVU_FMAC15(SUB); } -microVUf(void) mVU_MSUBAz() { mVU_FMAC15(SUB); } -microVUf(void) mVU_MSUBAw() { mVU_FMAC15(SUB); } -microVUf(void) mVU_MAX() { mVU_FMAC1(MAX); } -microVUf(void) mVU_MAXi() { mVU_FMAC6(MAX); } -microVUf(void) mVU_MAXx() { mVU_FMAC3(MAX); } -microVUf(void) mVU_MAXy() { mVU_FMAC3(MAX); } -microVUf(void) mVU_MAXz() { mVU_FMAC3(MAX); } -microVUf(void) mVU_MAXw() { mVU_FMAC3(MAX); } -microVUf(void) mVU_MINI() { mVU_FMAC1(MIN); } -microVUf(void) mVU_MINIi() { mVU_FMAC6(MIN); } -microVUf(void) mVU_MINIx() { mVU_FMAC3(MIN); } -microVUf(void) mVU_MINIy() { mVU_FMAC3(MIN); } -microVUf(void) mVU_MINIz() { mVU_FMAC3(MIN); } -microVUf(void) mVU_MINIw() { mVU_FMAC3(MIN); } -microVUf(void) mVU_OPMULA() { mVU_FMAC18(MUL); } -microVUf(void) mVU_OPMSUB() { mVU_FMAC19(SUB); } -microVUf(void) mVU_NOP() { - microVU* mVU = mVUx; - if (!recPass) {} - else {} -} +microVUf(void) mVU_ADD() { mVU_FMAC1(ADD); mVUlog("ADD"); } +microVUf(void) mVU_ADDi() { mVU_FMAC6(ADD); mVUlog("ADDi"); } +microVUf(void) mVU_ADDq() { mVU_FMAC22(ADD); mVUlog("ADDq"); } +microVUf(void) mVU_ADDx() { mVU_FMAC3(ADD); mVUlog("ADDx"); } +microVUf(void) mVU_ADDy() { mVU_FMAC3(ADD); mVUlog("ADDy"); } +microVUf(void) mVU_ADDz() { mVU_FMAC3(ADD); mVUlog("ADDz"); } +microVUf(void) mVU_ADDw() { mVU_FMAC3(ADD); mVUlog("ADDw"); } +microVUf(void) mVU_ADDA() { mVU_FMAC4(ADD); mVUlog("ADDA"); } +microVUf(void) mVU_ADDAi() { mVU_FMAC7(ADD); mVUlog("ADDAi"); } +microVUf(void) mVU_ADDAq() { mVU_FMAC23(ADD); mVUlog("ADDAq"); } +microVUf(void) mVU_ADDAx() { mVU_FMAC5(ADD); mVUlog("ADDAx"); } +microVUf(void) mVU_ADDAy() { mVU_FMAC5(ADD); mVUlog("ADDAy"); } +microVUf(void) mVU_ADDAz() { mVU_FMAC5(ADD); mVUlog("ADDAz"); } +microVUf(void) mVU_ADDAw() { mVU_FMAC5(ADD); mVUlog("ADDAw"); } +microVUf(void) mVU_SUB() { mVU_FMAC1(SUB); mVUlog("SUB"); } +microVUf(void) mVU_SUBi() { mVU_FMAC6(SUB); mVUlog("SUBi"); } +microVUf(void) mVU_SUBq() { mVU_FMAC22(SUB); mVUlog("SUBq"); } +microVUf(void) mVU_SUBx() { mVU_FMAC3(SUB); mVUlog("SUBx"); } +microVUf(void) mVU_SUBy() { mVU_FMAC3(SUB); mVUlog("SUBy"); } +microVUf(void) mVU_SUBz() { mVU_FMAC3(SUB); mVUlog("SUBz"); } +microVUf(void) mVU_SUBw() { mVU_FMAC3(SUB); mVUlog("SUBw"); } +microVUf(void) mVU_SUBA() { mVU_FMAC4(SUB); mVUlog("SUBA"); } +microVUf(void) mVU_SUBAi() { mVU_FMAC7(SUB); mVUlog("SUBAi"); } +microVUf(void) mVU_SUBAq() { mVU_FMAC23(SUB); mVUlog("SUBAq"); } +microVUf(void) mVU_SUBAx() { mVU_FMAC5(SUB); mVUlog("SUBAx"); } +microVUf(void) mVU_SUBAy() { mVU_FMAC5(SUB); mVUlog("SUBAy"); } +microVUf(void) mVU_SUBAz() { mVU_FMAC5(SUB); mVUlog("SUBAz"); } +microVUf(void) mVU_SUBAw() { mVU_FMAC5(SUB); mVUlog("SUBAw"); } +microVUf(void) mVU_MUL() { mVU_FMAC1(MUL); mVUlog("MUL"); } +microVUf(void) mVU_MULi() { mVU_FMAC6(MUL); mVUlog("MULi"); } +microVUf(void) mVU_MULq() { mVU_FMAC22(MUL); mVUlog("MULq"); } +microVUf(void) mVU_MULx() { mVU_FMAC3(MUL); mVUlog("MULx"); } +microVUf(void) mVU_MULy() { mVU_FMAC3(MUL); mVUlog("MULy"); } +microVUf(void) mVU_MULz() { mVU_FMAC3(MUL); mVUlog("MULz"); } +microVUf(void) mVU_MULw() { mVU_FMAC3(MUL); mVUlog("MULw"); } +microVUf(void) mVU_MULA() { mVU_FMAC4(MUL); mVUlog("MULA"); } +microVUf(void) mVU_MULAi() { mVU_FMAC7(MUL); mVUlog("MULAi"); } +microVUf(void) mVU_MULAq() { mVU_FMAC23(MUL); mVUlog("MULAq"); } +microVUf(void) mVU_MULAx() { mVU_FMAC5(MUL); mVUlog("MULAx"); } +microVUf(void) mVU_MULAy() { mVU_FMAC5(MUL); mVUlog("MULAy"); } +microVUf(void) mVU_MULAz() { mVU_FMAC5(MUL); mVUlog("MULAz"); } +microVUf(void) mVU_MULAw() { mVU_FMAC5(MUL); mVUlog("MULAw"); } +microVUf(void) mVU_MADD() { mVU_FMAC8(ADD); mVUlog("MADD"); } +microVUf(void) mVU_MADDi() { mVU_FMAC12(ADD); mVUlog("MADDi"); } +microVUf(void) mVU_MADDq() { mVU_FMAC24(ADD); mVUlog("MADDq"); } +microVUf(void) mVU_MADDx() { mVU_FMAC10(ADD); mVUlog("MADDx"); } +microVUf(void) mVU_MADDy() { mVU_FMAC10(ADD); mVUlog("MADDy"); } +microVUf(void) mVU_MADDz() { mVU_FMAC10(ADD); mVUlog("MADDz"); } +microVUf(void) mVU_MADDw() { mVU_FMAC10(ADD); mVUlog("MADDw"); } +microVUf(void) mVU_MADDA() { mVU_FMAC14(ADD); mVUlog("MADDA"); } +microVUf(void) mVU_MADDAi() { mVU_FMAC16(ADD); mVUlog("MADDAi"); } +microVUf(void) mVU_MADDAq() { mVU_FMAC26(ADD); mVUlog("MADDAq"); } +microVUf(void) mVU_MADDAx() { mVU_FMAC15(ADD); mVUlog("MADDAx"); } +microVUf(void) mVU_MADDAy() { mVU_FMAC15(ADD); mVUlog("MADDAy"); } +microVUf(void) mVU_MADDAz() { mVU_FMAC15(ADD); mVUlog("MADDAz"); } +microVUf(void) mVU_MADDAw() { mVU_FMAC15(ADD); mVUlog("MADDAw"); } +microVUf(void) mVU_MSUB() { mVU_FMAC9(SUB); mVUlog("MSUB"); } +microVUf(void) mVU_MSUBi() { mVU_FMAC13(SUB); mVUlog("MSUBi"); } +microVUf(void) mVU_MSUBq() { mVU_FMAC25(SUB); mVUlog("MSUBq"); } +microVUf(void) mVU_MSUBx() { mVU_FMAC11(SUB); mVUlog("MSUBx"); } +microVUf(void) mVU_MSUBy() { mVU_FMAC11(SUB); mVUlog("MSUBy"); } +microVUf(void) mVU_MSUBz() { mVU_FMAC11(SUB); mVUlog("MSUBz"); } +microVUf(void) mVU_MSUBw() { mVU_FMAC11(SUB); mVUlog("MSUBw"); } +microVUf(void) mVU_MSUBA() { mVU_FMAC14(SUB); mVUlog("MSUBA"); } +microVUf(void) mVU_MSUBAi() { mVU_FMAC16(SUB); mVUlog("MSUBAi"); } +microVUf(void) mVU_MSUBAq() { mVU_FMAC26(SUB); mVUlog("MSUBAq"); } +microVUf(void) mVU_MSUBAx() { mVU_FMAC15(SUB); mVUlog("MSUBAx"); } +microVUf(void) mVU_MSUBAy() { mVU_FMAC15(SUB); mVUlog("MSUBAy"); } +microVUf(void) mVU_MSUBAz() { mVU_FMAC15(SUB); mVUlog("MSUBAz"); } +microVUf(void) mVU_MSUBAw() { mVU_FMAC15(SUB); mVUlog("MSUBAw"); } +microVUf(void) mVU_MAX() { mVU_FMAC1(MAX); mVUlog("MAX"); } +microVUf(void) mVU_MAXi() { mVU_FMAC6(MAX); mVUlog("MAXi"); } +microVUf(void) mVU_MAXx() { mVU_FMAC3(MAX); mVUlog("MAXq"); } +microVUf(void) mVU_MAXy() { mVU_FMAC3(MAX); mVUlog("MAXy"); } +microVUf(void) mVU_MAXz() { mVU_FMAC3(MAX); mVUlog("MAXz"); } +microVUf(void) mVU_MAXw() { mVU_FMAC3(MAX); mVUlog("MAXw"); } +microVUf(void) mVU_MINI() { mVU_FMAC1(MIN); mVUlog("MINI"); } +microVUf(void) mVU_MINIi() { mVU_FMAC6(MIN); mVUlog("MINIi"); } +microVUf(void) mVU_MINIx() { mVU_FMAC3(MIN); mVUlog("MINIx"); } +microVUf(void) mVU_MINIy() { mVU_FMAC3(MIN); mVUlog("MINIy"); } +microVUf(void) mVU_MINIz() { mVU_FMAC3(MIN); mVUlog("MINIz"); } +microVUf(void) mVU_MINIw() { mVU_FMAC3(MIN); mVUlog("MINIw"); } +microVUf(void) mVU_OPMULA() { mVU_FMAC18(MUL); mVUlog("OPMULA"); } +microVUf(void) mVU_OPMSUB() { mVU_FMAC19(SUB); mVUlog("OPMSUB"); } +microVUf(void) mVU_NOP() { /*mVUlog("NOP");*/ } microVUq(void) mVU_FTOIx(uptr addr) { microVU* mVU = mVUx; if (!recPass) { mVUanalyzeFMAC2(_Fs_, _Ft_); } else { int Fs, Ft; + mVUlog("FTOIx"); mVUallocFMAC2a(Fs, Ft); // Note: For help understanding this algorithm see recVUMI_FTOI_Saturate() @@ -569,6 +566,7 @@ microVUq(void) mVU_ITOFx(uptr addr) { if (!recPass) { mVUanalyzeFMAC2(_Fs_, _Ft_); } else { int Fs, Ft; + mVUlog("ITOFx"); mVUallocFMAC2a(Fs, Ft); SSE2_CVTDQ2PS_XMM_to_XMM(Ft, Fs); @@ -587,6 +585,7 @@ microVUf(void) mVU_CLIP() { if (!recPass) { mVUanalyzeFMAC4(_Fs_, _Ft_); mVUlog("clip broken"); } else { int Fs, Ft; + mVUlog("CLIP"); mVUallocFMAC17a(Fs, Ft); mVUallocCFLAGa(gprT1, fpcInstance); SHL32ItoR(gprT1, 6);