Fixed up Soul Calibur 3 regression in r1400. It was a test bit of code, which is obviously wrong :P

git-svn-id: http://pcsx2.googlecode.com/svn/trunk@1410 96395faa-99c1-11dd-bbfe-3dabce05a288
This commit is contained in:
refraction 2009-06-20 13:26:52 +00:00
parent 3ad38e99cb
commit 7266dd12d2
2 changed files with 9 additions and 11 deletions

View File

@ -338,13 +338,13 @@ static __forceinline void VSyncStart(u32 sCycle)
if ((CSRw & 0x8))
{
GSCSRr|= 0x8;
if (!(GSIMR&0x800))
{
gsIrq();
}
CSRw &= ~0x8; //Disable the interrupt from triggering twice
GSCSRr|= 0x8;
}
hwIntcIrq(INTC_VBLANK_S);
@ -414,13 +414,13 @@ __forceinline void rcntUpdate_hScanline()
else { //HBLANK END / HRENDER Begin
if (CSRw & 0x4)
{
GSCSRr |= 4; // signal
if (!(GSIMR&0x400))
{
gsIrq();
}
CSRw &= ~0x4; //Disable the interrupt from triggering twice
GSCSRr |= 4; // signal
}
if (gates) rcntEndGate(false, hsyncCounter.sCycle);
if (psxhblankgate) psxCheckEndGate16(0);

View File

@ -139,13 +139,12 @@ static void RegHandlerSIGNAL(const u32* data)
if ((CSRw & 0x1))
{
GSCSRr |= 1; // signal
if (!(GSIMR&0x100) )
{
gsIrq();
}
CSRw &= ~0x1; //Disable the interrupt from triggering twice
GSCSRr |= 1; // signal
}
}
@ -155,11 +154,10 @@ static void RegHandlerFINISH(const u32* data)
if ((CSRw & 0x2))
{
GSCSRr |= 2; // finish
if (!(GSIMR&0x200) )
if (!(GSIMR&0x200))
gsIrq();
CSRw &= ~0x2; //Disable the interrupt from triggering twice
GSCSRr |= 2; // finish
}
}