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pcsx2:gsdx:spu2x: use parenthesis around macro parameters 

For safety reasons.
This commit is contained in:
Gregory Hainaut 2016-09-07 19:38:18 +02:00
parent b3d31869d6
commit 6e6eae7844
6 changed files with 36 additions and 36 deletions
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4
pcsx2/IPU/yuv2rgb.cpp
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@ -31,8 +31,8 @@
#define IPU_Y_BIAS 16 #define IPU_Y_BIAS 16
#define IPU_C_BIAS 128 #define IPU_C_BIAS 128
#define IPU_Y_COEFF 0x95 // 1.1640625 #define IPU_Y_COEFF 0x95 // 1.1640625
#define IPU_GCR_COEFF -0x68 // -0.8125 #define IPU_GCR_COEFF (-0x68) // -0.8125
#define IPU_GCB_COEFF -0x32 // -0.390625 #define IPU_GCB_COEFF (-0x32) // -0.390625
#define IPU_RCR_COEFF 0xcc // 1.59375 #define IPU_RCR_COEFF 0xcc // 1.59375
#define IPU_BCB_COEFF 0x102 // 2.015625 #define IPU_BCB_COEFF 0x102 // 2.015625

4
pcsx2/IopGte.cpp
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@ -425,8 +425,8 @@ __inline s32 FNC_OVERFLOW4(s64 x) {
} }
#define _LIMX(negv, posv, flagb) { \ #define _LIMX(negv, posv, flagb) { \
if (x < (negv)) { x = (negv); gteFLAG |= (1<<flagb); } else \ if (x < (negv)) { x = (negv); gteFLAG |= (1<<(flagb)); } else \
if (x > (posv)) { x = (posv); gteFLAG |= (1<<flagb); } return (x); \ if (x > (posv)) { x = (posv); gteFLAG |= (1<<(flagb)); } return (x); \
} }
__inline double limA1S(double x) { _LIMX(-32768.0, 32767.0, 24); } __inline double limA1S(double x) { _LIMX(-32768.0, 32767.0, 24); }

30
pcsx2/VUops.cpp
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@ -2240,7 +2240,7 @@ static __ri void _vuRegs##OP(const VURegs* VU, _VURegsNum *VUregsn) { \
VUregsn->VFr0xyzw= _XYZW; \ VUregsn->VFr0xyzw= _XYZW; \
VUregsn->VFread1 = 0; \ VUregsn->VFread1 = 0; \
VUregsn->VIwrite = 0; \ VUregsn->VIwrite = 0; \
VUregsn->VIread = (1 << REG_I)|(ACC?(1<<REG_ACC_FLAG):0)|GET_VF0_FLAG(_Fs_); \ VUregsn->VIread = (1 << REG_I)|((ACC)?(1<<REG_ACC_FLAG):0)|GET_VF0_FLAG(_Fs_); \
} }
#define VUREGS_FDFSQ(OP, ACC) \ #define VUREGS_FDFSQ(OP, ACC) \
@ -2252,7 +2252,7 @@ static __ri void _vuRegs##OP(const VURegs* VU, _VURegsNum *VUregsn) { \
VUregsn->VFr0xyzw= _XYZW; \ VUregsn->VFr0xyzw= _XYZW; \
VUregsn->VFread1 = 0; \ VUregsn->VFread1 = 0; \
VUregsn->VIwrite = 0; \ VUregsn->VIwrite = 0; \
VUregsn->VIread = (1 << REG_Q)|(ACC?(1<<REG_ACC_FLAG):0)|GET_VF0_FLAG(_Fs_); \ VUregsn->VIread = (1 << REG_Q)|((ACC)?(1<<REG_ACC_FLAG):0)|GET_VF0_FLAG(_Fs_); \
} }
#define VUREGS_FDFSFT(OP, ACC) \ #define VUREGS_FDFSFT(OP, ACC) \
@ -2265,7 +2265,7 @@ static __ri void _vuRegs##OP(const VURegs* VU, _VURegsNum *VUregsn) { \
VUregsn->VFread1 = _Ft_; \ VUregsn->VFread1 = _Ft_; \
VUregsn->VFr1xyzw= _XYZW; \ VUregsn->VFr1xyzw= _XYZW; \
VUregsn->VIwrite = 0; \ VUregsn->VIwrite = 0; \
VUregsn->VIread = (ACC?(1<<REG_ACC_FLAG):0)|GET_VF0_FLAG(_Fs_)|GET_VF0_FLAG(_Ft_); \ VUregsn->VIread = ((ACC)?(1<<REG_ACC_FLAG):0)|GET_VF0_FLAG(_Fs_)|GET_VF0_FLAG(_Ft_); \
} }
#define VUREGS_FDFSFTxyzw(OP, xyzw, ACC) \ #define VUREGS_FDFSFTxyzw(OP, xyzw, ACC) \
@ -2278,7 +2278,7 @@ static __ri void _vuRegs##OP(const VURegs* VU, _VURegsNum *VUregsn) { \
VUregsn->VFread1 = _Ft_; \ VUregsn->VFread1 = _Ft_; \
VUregsn->VFr1xyzw= xyzw; \ VUregsn->VFr1xyzw= xyzw; \
VUregsn->VIwrite = 0; \ VUregsn->VIwrite = 0; \
VUregsn->VIread = (ACC?(1<<REG_ACC_FLAG):0)|GET_VF0_FLAG(_Fs_)|GET_VF0_FLAG(_Ft_); \ VUregsn->VIread = ((ACC)?(1<<REG_ACC_FLAG):0)|GET_VF0_FLAG(_Fs_)|GET_VF0_FLAG(_Ft_); \
} }
#define VUREGS_FDFSFTx(OP, ACC) VUREGS_FDFSFTxyzw(OP, 8, ACC) #define VUREGS_FDFSFTx(OP, ACC) VUREGS_FDFSFTxyzw(OP, 8, ACC)
@ -2296,7 +2296,7 @@ static __ri void _vuRegs##OP(const VURegs* VU, _VURegsNum *VUregsn) { \
VUregsn->VFr0xyzw= _XYZW; \ VUregsn->VFr0xyzw= _XYZW; \
VUregsn->VFread1 = 0; \ VUregsn->VFread1 = 0; \
VUregsn->VIwrite = (1<<REG_ACC_FLAG); \ VUregsn->VIwrite = (1<<REG_ACC_FLAG); \
VUregsn->VIread = (1 << REG_I)|GET_VF0_FLAG(_Fs_)|((readacc||_XYZW!=15)?(1<<REG_ACC_FLAG):0); \ VUregsn->VIread = (1 << REG_I)|GET_VF0_FLAG(_Fs_)|(((readacc)||_XYZW!=15)?(1<<REG_ACC_FLAG):0); \
} }
#define VUREGS_ACCFSQ(OP, readacc) \ #define VUREGS_ACCFSQ(OP, readacc) \
@ -2308,7 +2308,7 @@ static __ri void _vuRegs##OP(const VURegs* VU, _VURegsNum *VUregsn) { \
VUregsn->VFr0xyzw= _XYZW; \ VUregsn->VFr0xyzw= _XYZW; \
VUregsn->VFread1 = 0; \ VUregsn->VFread1 = 0; \
VUregsn->VIwrite = (1<<REG_ACC_FLAG); \ VUregsn->VIwrite = (1<<REG_ACC_FLAG); \
VUregsn->VIread = (1 << REG_Q)|GET_VF0_FLAG(_Fs_)|((readacc||_XYZW!=15)?(1<<REG_ACC_FLAG):0); \ VUregsn->VIread = (1 << REG_Q)|GET_VF0_FLAG(_Fs_)|(((readacc)||_XYZW!=15)?(1<<REG_ACC_FLAG):0); \
} }
#define VUREGS_ACCFSFT(OP, readacc) \ #define VUREGS_ACCFSFT(OP, readacc) \
@ -2321,7 +2321,7 @@ static __ri void _vuRegs##OP(const VURegs* VU, _VURegsNum *VUregsn) { \
VUregsn->VFread1 = _Ft_; \ VUregsn->VFread1 = _Ft_; \
VUregsn->VFr1xyzw= _XYZW; \ VUregsn->VFr1xyzw= _XYZW; \
VUregsn->VIwrite = (1<<REG_ACC_FLAG); \ VUregsn->VIwrite = (1<<REG_ACC_FLAG); \
VUregsn->VIread = GET_VF0_FLAG(_Fs_)|GET_VF0_FLAG(_Ft_)|((readacc||_XYZW!=15)?(1<<REG_ACC_FLAG):0); \ VUregsn->VIread = GET_VF0_FLAG(_Fs_)|GET_VF0_FLAG(_Ft_)|(((readacc)||_XYZW!=15)?(1<<REG_ACC_FLAG):0); \
} }
#define VUREGS_ACCFSFTxyzw(OP, xyzw, readacc) \ #define VUREGS_ACCFSFTxyzw(OP, xyzw, readacc) \
@ -2334,7 +2334,7 @@ static __ri void _vuRegs##OP(const VURegs* VU, _VURegsNum *VUregsn) { \
VUregsn->VFread1 = _Ft_; \ VUregsn->VFread1 = _Ft_; \
VUregsn->VFr1xyzw= xyzw; \ VUregsn->VFr1xyzw= xyzw; \
VUregsn->VIwrite = (1<<REG_ACC_FLAG); \ VUregsn->VIwrite = (1<<REG_ACC_FLAG); \
VUregsn->VIread = GET_VF0_FLAG(_Fs_)|GET_VF0_FLAG(_Ft_)|((readacc||_XYZW!=15)?(1<<REG_ACC_FLAG):0); \ VUregsn->VIread = GET_VF0_FLAG(_Fs_)|GET_VF0_FLAG(_Ft_)|(((readacc)||_XYZW!=15)?(1<<REG_ACC_FLAG):0); \
} }
#define VUREGS_ACCFSFTx(OP, readacc) VUREGS_ACCFSFTxyzw(OP, 8, readacc) #define VUREGS_ACCFSFTx(OP, readacc) VUREGS_ACCFSFTxyzw(OP, 8, readacc)
@ -2437,27 +2437,27 @@ VUREGS_ACCFSFTw(SUBAw, 0);
#define VUREGS_FDFSFTxyzw_MUL(OP, ACC, xyzw) \ #define VUREGS_FDFSFTxyzw_MUL(OP, ACC, xyzw) \
static __ri void _vuRegs##OP(const VURegs* VU, _VURegsNum *VUregsn) { \ static __ri void _vuRegs##OP(const VURegs* VU, _VURegsNum *VUregsn) { \
if( _Ft_ == 0 && xyzw > 1 && _XYZW == 0xf ) { /* resetting to 0 */ \ if( _Ft_ == 0 && (xyzw) > 1 && _XYZW == 0xf ) { /* resetting to 0 */ \
VUregsn->pipe = VUPIPE_FMAC; \ VUregsn->pipe = VUPIPE_FMAC; \
VUregsn->VFwrite = ACC?0:_Fd_; \ VUregsn->VFwrite = (ACC)?0:_Fd_; \
VUregsn->VFwxyzw = _XYZW; \ VUregsn->VFwxyzw = _XYZW; \
VUregsn->VFread0 = 0; \ VUregsn->VFread0 = 0; \
VUregsn->VFr0xyzw= _XYZW; \ VUregsn->VFr0xyzw= _XYZW; \
VUregsn->VFread1 = 0; \ VUregsn->VFread1 = 0; \
VUregsn->VFr1xyzw= xyzw; \ VUregsn->VFr1xyzw= xyzw; \
VUregsn->VIwrite = (ACC?(1<<REG_ACC_FLAG):0); \ VUregsn->VIwrite = ((ACC)?(1<<REG_ACC_FLAG):0); \
VUregsn->VIread = (ACC&&(_XYZW!=15))?(1<<REG_ACC_FLAG):0; \ VUregsn->VIread = ((ACC)&&(_XYZW!=15))?(1<<REG_ACC_FLAG):0; \
} \ } \
else { \ else { \
VUregsn->pipe = VUPIPE_FMAC; \ VUregsn->pipe = VUPIPE_FMAC; \
VUregsn->VFwrite = ACC?0:_Fd_; \ VUregsn->VFwrite = (ACC)?0:_Fd_; \
VUregsn->VFwxyzw = _XYZW; \ VUregsn->VFwxyzw = _XYZW; \
VUregsn->VFread0 = _Fs_; \ VUregsn->VFread0 = _Fs_; \
VUregsn->VFr0xyzw= _XYZW; \ VUregsn->VFr0xyzw= _XYZW; \
VUregsn->VFread1 = _Ft_; \ VUregsn->VFread1 = _Ft_; \
VUregsn->VFr1xyzw= xyzw; \ VUregsn->VFr1xyzw= xyzw; \
VUregsn->VIwrite = (ACC?(1<<REG_ACC_FLAG):0); \ VUregsn->VIwrite = ((ACC)?(1<<REG_ACC_FLAG):0); \
VUregsn->VIread = GET_VF0_FLAG(_Fs_)|((ACC&&(_XYZW!=15))?(1<<REG_ACC_FLAG):0); \ VUregsn->VIread = GET_VF0_FLAG(_Fs_)|(((ACC)&&(_XYZW!=15))?(1<<REG_ACC_FLAG):0); \
} \ } \
} }

6
pcsx2/x86/iFPUd.cpp
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@ -285,19 +285,19 @@ void SetMaxValue(int regd)
if( info & PROCESS_EE_S ) xMOVSS(xRegisterSSE(sreg), xRegisterSSE(EEREC_S)); \ if( info & PROCESS_EE_S ) xMOVSS(xRegisterSSE(sreg), xRegisterSSE(EEREC_S)); \
else xMOVSSZX(xRegisterSSE(sreg), ptr[&fpuRegs.fpr[_Fs_]]); } else xMOVSSZX(xRegisterSSE(sreg), ptr[&fpuRegs.fpr[_Fs_]]); }
#define ALLOC_S(sreg) { sreg = _allocTempXMMreg(XMMT_FPS, -1); GET_S(sreg); } #define ALLOC_S(sreg) { (sreg) = _allocTempXMMreg(XMMT_FPS, -1); GET_S(sreg); }
#define GET_T(treg) { \ #define GET_T(treg) { \
if( info & PROCESS_EE_T ) xMOVSS(xRegisterSSE(treg), xRegisterSSE(EEREC_T)); \ if( info & PROCESS_EE_T ) xMOVSS(xRegisterSSE(treg), xRegisterSSE(EEREC_T)); \
else xMOVSSZX(xRegisterSSE(treg), ptr[&fpuRegs.fpr[_Ft_]]); } else xMOVSSZX(xRegisterSSE(treg), ptr[&fpuRegs.fpr[_Ft_]]); }
#define ALLOC_T(treg) { treg = _allocTempXMMreg(XMMT_FPS, -1); GET_T(treg); } #define ALLOC_T(treg) { (treg) = _allocTempXMMreg(XMMT_FPS, -1); GET_T(treg); }
#define GET_ACC(areg) { \ #define GET_ACC(areg) { \
if( info & PROCESS_EE_ACC ) xMOVSS(xRegisterSSE(areg), xRegisterSSE(EEREC_ACC)); \ if( info & PROCESS_EE_ACC ) xMOVSS(xRegisterSSE(areg), xRegisterSSE(EEREC_ACC)); \
else xMOVSSZX(xRegisterSSE(areg), ptr[&fpuRegs.ACC]); } else xMOVSSZX(xRegisterSSE(areg), ptr[&fpuRegs.ACC]); }
#define ALLOC_ACC(areg) { areg = _allocTempXMMreg(XMMT_FPS, -1); GET_ACC(areg); } #define ALLOC_ACC(areg) { (areg) = _allocTempXMMreg(XMMT_FPS, -1); GET_ACC(areg); }
#define CLEAR_OU_FLAGS { xAND(ptr32[&fpuRegs.fprc[31]], ~(FPUflagO | FPUflagU)); } #define CLEAR_OU_FLAGS { xAND(ptr32[&fpuRegs.fprc[31]], ~(FPUflagO | FPUflagU)); }

14
plugins/GSdx/GSLocalMemory.cpp
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@ -28,20 +28,20 @@
#include "GSLocalMemory.h" #include "GSLocalMemory.h"
#define ASSERT_BLOCK(r, w, h) \ #define ASSERT_BLOCK(r, w, h) \
ASSERT((r).width() >= w && (r).height() >= h && !((r).left & (w - 1)) && !((r).top & (h - 1)) && !((r).right & (w - 1)) && !((r).bottom & (h - 1))); \ ASSERT((r).width() >= (w) && (r).height() >= (h) && !((r).left & ((w) - 1)) && !((r).top & ((h) - 1)) && !((r).right & ((w) - 1)) && !((r).bottom & ((h) - 1))); \
#define FOREACH_BLOCK_START(r, w, h, bpp) \ #define FOREACH_BLOCK_START(r, w, h, bpp) \
ASSERT_BLOCK(r, w, h); \ ASSERT_BLOCK(r, w, h); \
GSVector4i _r = r >> 3; \ GSVector4i _r = (r) >> 3; \
uint8* _dst = dst - _r.left * bpp; \ uint8* _dst = dst - _r.left * (bpp); \
int _offset = dstpitch * h; \ int _offset = dstpitch * (h); \
for(int y = _r.top; y < _r.bottom; y += h >> 3, _dst += _offset) \ for(int y = _r.top; y < _r.bottom; y += (h) >> 3, _dst += _offset) \
{ \ { \
uint32 _base = off->block.row[y]; \ uint32 _base = off->block.row[y]; \
for(int x = _r.left; x < _r.right; x += w >> 3) \ for(int x = _r.left; x < _r.right; x += (w) >> 3) \
{ \ { \
const uint8* src = BlockPtr(_base + off->block.col[x]); \ const uint8* src = BlockPtr(_base + off->block.col[x]); \
uint8* read_dst = &_dst[x * bpp]; \ uint8* read_dst = &_dst[x * (bpp)]; \
#define FOREACH_BLOCK_END }} #define FOREACH_BLOCK_END }}

8
plugins/spu2-x/src/spu2sys.cpp
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@ -990,8 +990,8 @@ static void __fastcall RegWrite_Core( u16 value )
SetLoWord( thiscore.Regs.reg_out, value ); \ SetLoWord( thiscore.Regs.reg_out, value ); \
if( result == thiscore.Regs.reg_out ) break; \ if( result == thiscore.Regs.reg_out ) break; \
\ \
const uint start_bit = hiword ? 16 : 0; \ const uint start_bit = (hiword) ? 16 : 0; \
const uint end_bit = hiword ? 24 : 16; \ const uint end_bit = (hiword) ? 24 : 16; \
for (uint vc=start_bit, vx=1; vc<end_bit; ++vc, vx<<=1) \ for (uint vc=start_bit, vx=1; vc<end_bit; ++vc, vx<<=1) \
thiscore.VoiceGates[vc].mask_out = (value & vx) ? -1 : 0; \ thiscore.VoiceGates[vc].mask_out = (value & vx) ? -1 : 0; \
} }
@ -1264,10 +1264,10 @@ static void __fastcall RegWrite_Null( u16 value )
#define CoreParamsPair( core, omem ) \ #define CoreParamsPair( core, omem ) \
RegWrite_Core<core, omem>, RegWrite_Core<core, (omem+2)> RegWrite_Core<core, omem>, RegWrite_Core<core, ((omem)+2)>
#define ReverbPair( core, mem ) \ #define ReverbPair( core, mem ) \
RegWrite_Reverb<core, mem>, RegWrite_Core<core, (mem+2)> RegWrite_Reverb<core, mem>, RegWrite_Core<core, ((mem)+2)>
#define REGRAW(addr) RegWrite_Raw<addr> #define REGRAW(addr) RegWrite_Raw<addr>