From 6e6eae7844e794917d61a72bd583755ab622c1ef Mon Sep 17 00:00:00 2001 From: Gregory Hainaut Date: Wed, 7 Sep 2016 19:38:18 +0200 Subject: [PATCH] pcsx2:gsdx:spu2x: use parenthesis around macro parameters For safety reasons. --- pcsx2/IPU/yuv2rgb.cpp | 10 +++++----- pcsx2/IopGte.cpp | 4 ++-- pcsx2/VUops.cpp | 30 +++++++++++++++--------------- pcsx2/x86/iFPUd.cpp | 6 +++--- plugins/GSdx/GSLocalMemory.cpp | 14 +++++++------- plugins/spu2-x/src/spu2sys.cpp | 8 ++++---- 6 files changed, 36 insertions(+), 36 deletions(-) diff --git a/pcsx2/IPU/yuv2rgb.cpp b/pcsx2/IPU/yuv2rgb.cpp index 46c196b8b3..7cab056784 100644 --- a/pcsx2/IPU/yuv2rgb.cpp +++ b/pcsx2/IPU/yuv2rgb.cpp @@ -28,11 +28,11 @@ // faster or "more accurate" implementation, but this is the precise documented integer method used by // the hardware and is fast enough with SSE2. -#define IPU_Y_BIAS 16 -#define IPU_C_BIAS 128 -#define IPU_Y_COEFF 0x95 // 1.1640625 -#define IPU_GCR_COEFF -0x68 // -0.8125 -#define IPU_GCB_COEFF -0x32 // -0.390625 +#define IPU_Y_BIAS 16 +#define IPU_C_BIAS 128 +#define IPU_Y_COEFF 0x95 // 1.1640625 +#define IPU_GCR_COEFF (-0x68) // -0.8125 +#define IPU_GCB_COEFF (-0x32) // -0.390625 #define IPU_RCR_COEFF 0xcc // 1.59375 #define IPU_BCB_COEFF 0x102 // 2.015625 diff --git a/pcsx2/IopGte.cpp b/pcsx2/IopGte.cpp index 3e7b4fa4d0..c766ae1f29 100644 --- a/pcsx2/IopGte.cpp +++ b/pcsx2/IopGte.cpp @@ -425,8 +425,8 @@ __inline s32 FNC_OVERFLOW4(s64 x) { } #define _LIMX(negv, posv, flagb) { \ - if (x < (negv)) { x = (negv); gteFLAG |= (1< (posv)) { x = (posv); gteFLAG |= (1< (posv)) { x = (posv); gteFLAG |= (1<<(flagb)); } return (x); \ } __inline double limA1S(double x) { _LIMX(-32768.0, 32767.0, 24); } diff --git a/pcsx2/VUops.cpp b/pcsx2/VUops.cpp index e25ca41b56..bdac364857 100644 --- a/pcsx2/VUops.cpp +++ b/pcsx2/VUops.cpp @@ -2240,7 +2240,7 @@ static __ri void _vuRegs##OP(const VURegs* VU, _VURegsNum *VUregsn) { \ VUregsn->VFr0xyzw= _XYZW; \ VUregsn->VFread1 = 0; \ VUregsn->VIwrite = 0; \ - VUregsn->VIread = (1 << REG_I)|(ACC?(1<VIread = (1 << REG_I)|((ACC)?(1<VFr0xyzw= _XYZW; \ VUregsn->VFread1 = 0; \ VUregsn->VIwrite = 0; \ - VUregsn->VIread = (1 << REG_Q)|(ACC?(1<VIread = (1 << REG_Q)|((ACC)?(1<VFread1 = _Ft_; \ VUregsn->VFr1xyzw= _XYZW; \ VUregsn->VIwrite = 0; \ - VUregsn->VIread = (ACC?(1<VIread = ((ACC)?(1<VFread1 = _Ft_; \ VUregsn->VFr1xyzw= xyzw; \ VUregsn->VIwrite = 0; \ - VUregsn->VIread = (ACC?(1<VIread = ((ACC)?(1<VFr0xyzw= _XYZW; \ VUregsn->VFread1 = 0; \ VUregsn->VIwrite = (1<VIread = (1 << REG_I)|GET_VF0_FLAG(_Fs_)|((readacc||_XYZW!=15)?(1<VIread = (1 << REG_I)|GET_VF0_FLAG(_Fs_)|(((readacc)||_XYZW!=15)?(1<VFr0xyzw= _XYZW; \ VUregsn->VFread1 = 0; \ VUregsn->VIwrite = (1<VIread = (1 << REG_Q)|GET_VF0_FLAG(_Fs_)|((readacc||_XYZW!=15)?(1<VIread = (1 << REG_Q)|GET_VF0_FLAG(_Fs_)|(((readacc)||_XYZW!=15)?(1<VFread1 = _Ft_; \ VUregsn->VFr1xyzw= _XYZW; \ VUregsn->VIwrite = (1<VIread = GET_VF0_FLAG(_Fs_)|GET_VF0_FLAG(_Ft_)|((readacc||_XYZW!=15)?(1<VIread = GET_VF0_FLAG(_Fs_)|GET_VF0_FLAG(_Ft_)|(((readacc)||_XYZW!=15)?(1<VFread1 = _Ft_; \ VUregsn->VFr1xyzw= xyzw; \ VUregsn->VIwrite = (1<VIread = GET_VF0_FLAG(_Fs_)|GET_VF0_FLAG(_Ft_)|((readacc||_XYZW!=15)?(1<VIread = GET_VF0_FLAG(_Fs_)|GET_VF0_FLAG(_Ft_)|(((readacc)||_XYZW!=15)?(1< 1 && _XYZW == 0xf ) { /* resetting to 0 */ \ + if( _Ft_ == 0 && (xyzw) > 1 && _XYZW == 0xf ) { /* resetting to 0 */ \ VUregsn->pipe = VUPIPE_FMAC; \ - VUregsn->VFwrite = ACC?0:_Fd_; \ + VUregsn->VFwrite = (ACC)?0:_Fd_; \ VUregsn->VFwxyzw = _XYZW; \ VUregsn->VFread0 = 0; \ VUregsn->VFr0xyzw= _XYZW; \ VUregsn->VFread1 = 0; \ VUregsn->VFr1xyzw= xyzw; \ - VUregsn->VIwrite = (ACC?(1<VIread = (ACC&&(_XYZW!=15))?(1<VIwrite = ((ACC)?(1<VIread = ((ACC)&&(_XYZW!=15))?(1<pipe = VUPIPE_FMAC; \ - VUregsn->VFwrite = ACC?0:_Fd_; \ + VUregsn->VFwrite = (ACC)?0:_Fd_; \ VUregsn->VFwxyzw = _XYZW; \ VUregsn->VFread0 = _Fs_; \ VUregsn->VFr0xyzw= _XYZW; \ VUregsn->VFread1 = _Ft_; \ VUregsn->VFr1xyzw= xyzw; \ - VUregsn->VIwrite = (ACC?(1<VIread = GET_VF0_FLAG(_Fs_)|((ACC&&(_XYZW!=15))?(1<VIwrite = ((ACC)?(1<VIread = GET_VF0_FLAG(_Fs_)|(((ACC)&&(_XYZW!=15))?(1<= w && (r).height() >= h && !((r).left & (w - 1)) && !((r).top & (h - 1)) && !((r).right & (w - 1)) && !((r).bottom & (h - 1))); \ + ASSERT((r).width() >= (w) && (r).height() >= (h) && !((r).left & ((w) - 1)) && !((r).top & ((h) - 1)) && !((r).right & ((w) - 1)) && !((r).bottom & ((h) - 1))); \ #define FOREACH_BLOCK_START(r, w, h, bpp) \ ASSERT_BLOCK(r, w, h); \ - GSVector4i _r = r >> 3; \ - uint8* _dst = dst - _r.left * bpp; \ - int _offset = dstpitch * h; \ - for(int y = _r.top; y < _r.bottom; y += h >> 3, _dst += _offset) \ + GSVector4i _r = (r) >> 3; \ + uint8* _dst = dst - _r.left * (bpp); \ + int _offset = dstpitch * (h); \ + for(int y = _r.top; y < _r.bottom; y += (h) >> 3, _dst += _offset) \ { \ uint32 _base = off->block.row[y]; \ - for(int x = _r.left; x < _r.right; x += w >> 3) \ + for(int x = _r.left; x < _r.right; x += (w) >> 3) \ { \ const uint8* src = BlockPtr(_base + off->block.col[x]); \ - uint8* read_dst = &_dst[x * bpp]; \ + uint8* read_dst = &_dst[x * (bpp)]; \ #define FOREACH_BLOCK_END }} diff --git a/plugins/spu2-x/src/spu2sys.cpp b/plugins/spu2-x/src/spu2sys.cpp index 494cf946bc..db12e90124 100644 --- a/plugins/spu2-x/src/spu2sys.cpp +++ b/plugins/spu2-x/src/spu2sys.cpp @@ -990,8 +990,8 @@ static void __fastcall RegWrite_Core( u16 value ) SetLoWord( thiscore.Regs.reg_out, value ); \ if( result == thiscore.Regs.reg_out ) break; \ \ - const uint start_bit = hiword ? 16 : 0; \ - const uint end_bit = hiword ? 24 : 16; \ + const uint start_bit = (hiword) ? 16 : 0; \ + const uint end_bit = (hiword) ? 24 : 16; \ for (uint vc=start_bit, vx=1; vc, RegWrite_Core + RegWrite_Core, RegWrite_Core #define ReverbPair( core, mem ) \ - RegWrite_Reverb, RegWrite_Core + RegWrite_Reverb, RegWrite_Core #define REGRAW(addr) RegWrite_Raw