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EE Rec/Int: Removed micro optimisation in QFSRV/MSTAB/MSTAH. Reverted functionality to match the documentation. There were some scenarios that weren't really accounted for, like developers doing what they're told not to do.

This commit is contained in:
refractionpcsx2 2018-07-15 13:14:46 +01:00
parent 46662b0436
commit 69888e5ab0
4 changed files with 11 additions and 9 deletions
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2
pcsx2/MMI.cpp
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@ -1001,7 +1001,7 @@ void QFSRV() { // JayteeMaster: changed a bit to avoid screw up
GPR_reg Rd; GPR_reg Rd;
if (!_Rd_) return; if (!_Rd_) return;
u32 sa_amt = cpuRegs.sa << 3; u32 sa_amt = cpuRegs.sa;
if (sa_amt == 0) { if (sa_amt == 0) {
cpuRegs.GPR.r[_Rd_].UD[0] = cpuRegs.GPR.r[_Rt_].UD[0]; cpuRegs.GPR.r[_Rd_].UD[0] = cpuRegs.GPR.r[_Rt_].UD[0];
cpuRegs.GPR.r[_Rd_].UD[1] = cpuRegs.GPR.r[_Rt_].UD[1]; cpuRegs.GPR.r[_Rd_].UD[1] = cpuRegs.GPR.r[_Rt_].UD[1];

6
pcsx2/R5900OpcodeImpl.cpp
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@ -1004,7 +1004,7 @@ void MFSA() {
} }
void MTSA() { void MTSA() {
cpuRegs.sa = (s32)cpuRegs.GPR.r[_Rs_].SD[0] & 0xf; cpuRegs.sa = (s32)cpuRegs.GPR.r[_Rs_].SD[0];
} }
// SNY supports three basic modes, two which synchronize memory accesses (related // SNY supports three basic modes, two which synchronize memory accesses (related
@ -1060,11 +1060,11 @@ void TLTIU() { if (cpuRegs.GPR.r[_Rs_].UD[0] < (u64)_Imm_) trap(); }
*********************************************************/ *********************************************************/
void MTSAB() { void MTSAB() {
cpuRegs.sa = ((cpuRegs.GPR.r[_Rs_].UL[0] & 0xF) ^ (_Imm_ & 0xF)); cpuRegs.sa = ((cpuRegs.GPR.r[_Rs_].UL[0] & 0xF) ^ (_Imm_ & 0xF)) << 3;
} }
void MTSAH() { void MTSAH() {
cpuRegs.sa = ((cpuRegs.GPR.r[_Rs_].UL[0] & 0x7) ^ (_Imm_ & 0x7)) << 1; cpuRegs.sa = ((cpuRegs.GPR.r[_Rs_].UL[0] & 0x7) ^ (_Imm_ & 0x7)) << 4;
} }
} } } // end namespace R5900::Interpreter::OpcodeImpl } } } // end namespace R5900::Interpreter::OpcodeImpl

2
pcsx2/x86/iMMI.cpp
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@ -1500,6 +1500,7 @@ void recQFSRV()
int info = eeRecompileCodeXMM(XMMINFO_WRITED); int info = eeRecompileCodeXMM(XMMINFO_WRITED);
xMOV(eax, ptr32[&cpuRegs.sa]); xMOV(eax, ptr32[&cpuRegs.sa]);
xSHR(eax, 3);
xMOVDQU(xRegisterSSE(EEREC_D), ptr32[eax + &cpuRegs.GPR.r[_Rt_]]); xMOVDQU(xRegisterSSE(EEREC_D), ptr32[eax + &cpuRegs.GPR.r[_Rt_]]);
return; return;
} }
@ -1507,6 +1508,7 @@ void recQFSRV()
int info = eeRecompileCodeXMM( XMMINFO_READS | XMMINFO_READT | XMMINFO_WRITED ); int info = eeRecompileCodeXMM( XMMINFO_READS | XMMINFO_READT | XMMINFO_WRITED );
xMOV(eax, ptr32[&cpuRegs.sa]); xMOV(eax, ptr32[&cpuRegs.sa]);
xSHR(eax, 3);
xMOVDQA(ptr32[&tempqw[0]], xRegisterSSE(EEREC_T)); xMOVDQA(ptr32[&tempqw[0]], xRegisterSSE(EEREC_T));
xMOVDQA(ptr32[&tempqw[4]], xRegisterSSE(EEREC_S)); xMOVDQA(ptr32[&tempqw[4]], xRegisterSSE(EEREC_S));
xMOVDQU(xRegisterSSE(EEREC_D), ptr32[eax + &tempqw]); xMOVDQU(xRegisterSSE(EEREC_D), ptr32[eax + &tempqw]);

10
pcsx2/x86/iR5900Misc.cpp
View File

@ -110,7 +110,7 @@ void recMFSA()
void recMTSA() void recMTSA()
{ {
if( GPR_IS_CONST1(_Rs_) ) { if( GPR_IS_CONST1(_Rs_) ) {
xMOV(ptr32[&cpuRegs.sa], g_cpuConstRegs[_Rs_].UL[0] & 0xf ); xMOV(ptr32[&cpuRegs.sa], g_cpuConstRegs[_Rs_].UL[0] /*& 0xf*/ );
} }
else { else {
int mmreg; int mmreg;
@ -122,19 +122,19 @@ void recMTSA()
xMOV(eax, ptr[&cpuRegs.GPR.r[_Rs_].UL[0]]); xMOV(eax, ptr[&cpuRegs.GPR.r[_Rs_].UL[0]]);
xMOV(ptr[&cpuRegs.sa], eax); xMOV(ptr[&cpuRegs.sa], eax);
} }
xAND(ptr32[&cpuRegs.sa], 0xf);
} }
} }
void recMTSAB() void recMTSAB()
{ {
if( GPR_IS_CONST1(_Rs_) ) { if( GPR_IS_CONST1(_Rs_) ) {
xMOV(ptr32[&cpuRegs.sa], ((g_cpuConstRegs[_Rs_].UL[0] & 0xF) ^ (_Imm_ & 0xF)) ); xMOV(ptr32[&cpuRegs.sa], ((g_cpuConstRegs[_Rs_].UL[0] & 0xF) ^ (_Imm_ & 0xF)) << 3);
} }
else { else {
_eeMoveGPRtoR(eax, _Rs_); _eeMoveGPRtoR(eax, _Rs_);
xAND(eax, 0xF); xAND(eax, 0xF);
xXOR(eax, _Imm_&0xf); xXOR(eax, _Imm_&0xf);
xSHL(eax, 3);
xMOV(ptr[&cpuRegs.sa], eax); xMOV(ptr[&cpuRegs.sa], eax);
} }
} }
@ -142,13 +142,13 @@ void recMTSAB()
void recMTSAH() void recMTSAH()
{ {
if( GPR_IS_CONST1(_Rs_) ) { if( GPR_IS_CONST1(_Rs_) ) {
xMOV(ptr32[&cpuRegs.sa], ((g_cpuConstRegs[_Rs_].UL[0] & 0x7) ^ (_Imm_ & 0x7)) << 1); xMOV(ptr32[&cpuRegs.sa], ((g_cpuConstRegs[_Rs_].UL[0] & 0x7) ^ (_Imm_ & 0x7)) << 4);
} }
else { else {
_eeMoveGPRtoR(eax, _Rs_); _eeMoveGPRtoR(eax, _Rs_);
xAND(eax, 0x7); xAND(eax, 0x7);
xXOR(eax, _Imm_&0x7); xXOR(eax, _Imm_&0x7);
xSHL(eax, 1); xSHL(eax, 4);
xMOV(ptr[&cpuRegs.sa], eax); xMOV(ptr[&cpuRegs.sa], eax);
} }
} }