From 69888e5ab037fec83807edbdcd3afdcad1072025 Mon Sep 17 00:00:00 2001
From: refractionpcsx2 <refraction@gmail.com>
Date: Sun, 15 Jul 2018 13:14:46 +0100
Subject: [PATCH] EE Rec/Int: Removed micro optimisation in QFSRV/MSTAB/MSTAH.
 Reverted functionality to match the documentation. There were some scenarios
 that weren't really accounted for, like developers doing what they're told
 not to do.

---
 pcsx2/MMI.cpp             |  2 +-
 pcsx2/R5900OpcodeImpl.cpp |  6 +++---
 pcsx2/x86/iMMI.cpp        |  2 ++
 pcsx2/x86/iR5900Misc.cpp  | 10 +++++-----
 4 files changed, 11 insertions(+), 9 deletions(-)

diff --git a/pcsx2/MMI.cpp b/pcsx2/MMI.cpp
index 60da636e4e..33d417f63d 100644
--- a/pcsx2/MMI.cpp
+++ b/pcsx2/MMI.cpp
@@ -1001,7 +1001,7 @@ void QFSRV() {				// JayteeMaster: changed a bit to avoid screw up
 	GPR_reg Rd;
 	if (!_Rd_) return;
 
-	u32 sa_amt = cpuRegs.sa << 3;
+	u32 sa_amt = cpuRegs.sa;
 	if (sa_amt == 0) {
 		cpuRegs.GPR.r[_Rd_].UD[0] = cpuRegs.GPR.r[_Rt_].UD[0];
 		cpuRegs.GPR.r[_Rd_].UD[1] = cpuRegs.GPR.r[_Rt_].UD[1];
diff --git a/pcsx2/R5900OpcodeImpl.cpp b/pcsx2/R5900OpcodeImpl.cpp
index b66a679e2f..a47b6f6ef4 100644
--- a/pcsx2/R5900OpcodeImpl.cpp
+++ b/pcsx2/R5900OpcodeImpl.cpp
@@ -1004,7 +1004,7 @@ void MFSA() {
 }
 
 void MTSA() {
-	cpuRegs.sa = (s32)cpuRegs.GPR.r[_Rs_].SD[0] & 0xf;
+	cpuRegs.sa = (s32)cpuRegs.GPR.r[_Rs_].SD[0];
 }
 
 // SNY supports three basic modes, two which synchronize memory accesses (related
@@ -1060,11 +1060,11 @@ void TLTIU() { if (cpuRegs.GPR.r[_Rs_].UD[0] <  (u64)_Imm_) trap(); }
 *********************************************************/
 
 void MTSAB() {
- 	cpuRegs.sa = ((cpuRegs.GPR.r[_Rs_].UL[0] & 0xF) ^ (_Imm_ & 0xF));
+ 	cpuRegs.sa = ((cpuRegs.GPR.r[_Rs_].UL[0] & 0xF) ^ (_Imm_ & 0xF)) << 3;
 }
 
 void MTSAH() {
-    cpuRegs.sa = ((cpuRegs.GPR.r[_Rs_].UL[0] & 0x7) ^ (_Imm_ & 0x7)) << 1;
+    cpuRegs.sa = ((cpuRegs.GPR.r[_Rs_].UL[0] & 0x7) ^ (_Imm_ & 0x7)) << 4;
 }
 
 } }	} // end namespace R5900::Interpreter::OpcodeImpl
diff --git a/pcsx2/x86/iMMI.cpp b/pcsx2/x86/iMMI.cpp
index a127e614ba..7293eac4bc 100644
--- a/pcsx2/x86/iMMI.cpp
+++ b/pcsx2/x86/iMMI.cpp
@@ -1500,6 +1500,7 @@ void recQFSRV()
 		int info = eeRecompileCodeXMM(XMMINFO_WRITED);
 
 		xMOV(eax, ptr32[&cpuRegs.sa]);
+		xSHR(eax, 3);
 		xMOVDQU(xRegisterSSE(EEREC_D), ptr32[eax + &cpuRegs.GPR.r[_Rt_]]);
 		return;
 	}
@@ -1507,6 +1508,7 @@ void recQFSRV()
 	int info = eeRecompileCodeXMM( XMMINFO_READS | XMMINFO_READT | XMMINFO_WRITED );
 
 	xMOV(eax, ptr32[&cpuRegs.sa]);
+	xSHR(eax, 3);
 	xMOVDQA(ptr32[&tempqw[0]], xRegisterSSE(EEREC_T));
 	xMOVDQA(ptr32[&tempqw[4]], xRegisterSSE(EEREC_S));
 	xMOVDQU(xRegisterSSE(EEREC_D), ptr32[eax + &tempqw]);
diff --git a/pcsx2/x86/iR5900Misc.cpp b/pcsx2/x86/iR5900Misc.cpp
index 690a555db0..f328099ab5 100644
--- a/pcsx2/x86/iR5900Misc.cpp
+++ b/pcsx2/x86/iR5900Misc.cpp
@@ -110,7 +110,7 @@ void recMFSA()
 void recMTSA()
 {
 	if( GPR_IS_CONST1(_Rs_) ) {
-		xMOV(ptr32[&cpuRegs.sa], g_cpuConstRegs[_Rs_].UL[0] & 0xf );
+		xMOV(ptr32[&cpuRegs.sa], g_cpuConstRegs[_Rs_].UL[0] /*& 0xf*/ );
 	}
 	else {
 		int mmreg;
@@ -122,19 +122,19 @@ void recMTSA()
 			xMOV(eax, ptr[&cpuRegs.GPR.r[_Rs_].UL[0]]);
 			xMOV(ptr[&cpuRegs.sa], eax);
 		}
-		xAND(ptr32[&cpuRegs.sa], 0xf);
 	}
 }
 
 void recMTSAB()
 {
 	if( GPR_IS_CONST1(_Rs_) ) {
-		xMOV(ptr32[&cpuRegs.sa], ((g_cpuConstRegs[_Rs_].UL[0] & 0xF) ^ (_Imm_ & 0xF)) );
+		xMOV(ptr32[&cpuRegs.sa], ((g_cpuConstRegs[_Rs_].UL[0] & 0xF) ^ (_Imm_ & 0xF)) << 3);
 	}
 	else {
 		_eeMoveGPRtoR(eax, _Rs_);
 		xAND(eax, 0xF);
 		xXOR(eax, _Imm_&0xf);
+		xSHL(eax, 3);
 		xMOV(ptr[&cpuRegs.sa], eax);
 	}
 }
@@ -142,13 +142,13 @@ void recMTSAB()
 void recMTSAH()
 {
 	if( GPR_IS_CONST1(_Rs_) ) {
-		xMOV(ptr32[&cpuRegs.sa], ((g_cpuConstRegs[_Rs_].UL[0] & 0x7) ^ (_Imm_ & 0x7)) << 1);
+		xMOV(ptr32[&cpuRegs.sa], ((g_cpuConstRegs[_Rs_].UL[0] & 0x7) ^ (_Imm_ & 0x7)) << 4);
 	}
 	else {
 		_eeMoveGPRtoR(eax, _Rs_);
 		xAND(eax, 0x7);
 		xXOR(eax, _Imm_&0x7);
-		xSHL(eax, 1);
+		xSHL(eax, 4);
 		xMOV(ptr[&cpuRegs.sa], eax);
 	}
 }