mirror of https://github.com/PCSX2/pcsx2.git
the document i was reading had incorrect information for the ORI opcode (said it should be a sign-extended immediate, but its really supposed to be zero-extended) took me hours to figure out the problem ><
anyways, I fixed the opcodes correctly... git-svn-id: http://pcsx2-playground.googlecode.com/svn/trunk@175 a6443dda-0b58-4228-96e9-037be469359c
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@ -147,9 +147,9 @@ void ADDI() { if (!_Rt_) return; cpuRegs.GPR.r[_Rt_].UD[0] = cpuRegs.GPR.r[_Rs_
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void ADDIU() { if (!_Rt_) return; cpuRegs.GPR.r[_Rt_].UD[0] = cpuRegs.GPR.r[_Rs_].SL[0] + _Imm_; }// Rt = Rs + Im signed !!!
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void DADDI() { if (!_Rt_) return; cpuRegs.GPR.r[_Rt_].UD[0] = cpuRegs.GPR.r[_Rs_].SD[0] + _Imm_; }// Rt = Rs + Im
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void DADDIU() { if (!_Rt_) return; cpuRegs.GPR.r[_Rt_].UD[0] = cpuRegs.GPR.r[_Rs_].SD[0] + _Imm_; }// Rt = Rs + Im
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void ANDI() { if (!_Rt_) return; cpuRegs.GPR.r[_Rt_].UD[0] = cpuRegs.GPR.r[_Rs_].UD[0] & (u64)_ImmU_; } // Rt = Rs And Im (zero-extended)
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void ORI() { if (!_Rt_) return; cpuRegs.GPR.r[_Rt_].UD[0] = cpuRegs.GPR.r[_Rs_].UD[0] | (s64)_ImmU_; } // Rt = Rs Or Im (sign-extended)
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void XORI() { if (!_Rt_) return; cpuRegs.GPR.r[_Rt_].UD[0] = cpuRegs.GPR.r[_Rs_].UD[0] ^ (u64)_ImmU_; } // Rt = Rs Xor Im (zero-extended)
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void ANDI() { if (!_Rt_) return; cpuRegs.GPR.r[_Rt_].UD[0] = cpuRegs.GPR.r[_Rs_].UD[0] & (u64)_ImmU_; } // Rt = Rs And Im (zero-extended)
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void ORI() { if (!_Rt_) return; cpuRegs.GPR.r[_Rt_].UD[0] = cpuRegs.GPR.r[_Rs_].UD[0] | (u64)_ImmU_; } // Rt = Rs Or Im (zero-extended)
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void XORI() { if (!_Rt_) return; cpuRegs.GPR.r[_Rt_].UD[0] = cpuRegs.GPR.r[_Rs_].UD[0] ^ (u64)_ImmU_; } // Rt = Rs Xor Im (zero-extended)
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void SLTI() { if (!_Rt_) return; cpuRegs.GPR.r[_Rt_].UD[0] = cpuRegs.GPR.r[_Rs_].SD[0] < (s64)(_Imm_); } // Rt = Rs < Im (signed)
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void SLTIU() { if (!_Rt_) return; cpuRegs.GPR.r[_Rt_].UD[0] = cpuRegs.GPR.r[_Rs_].UD[0] < (u64)(_Imm_); } // Rt = Rs < Im (unsigned)
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@ -340,7 +340,7 @@ EERECOMPILE_CODEX(eeRecompileCode1, SLTI);
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//// ANDI
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void recANDI_const()
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{
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g_cpuConstRegs[_Rt_].UD[0] = g_cpuConstRegs[_Rs_].UD[0] & (u64)_ImmU_; // should be zero-extended
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g_cpuConstRegs[_Rt_].UD[0] = g_cpuConstRegs[_Rs_].UD[0] & (u64)_ImmU_; // Zero-extended Immediate
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}
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extern void LogicalOpRtoR(x86MMXRegType to, x86MMXRegType from, int op);
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@ -356,8 +356,9 @@ void recLogicalOpI(int info, int op)
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SetMMXstate();
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if( _ImmU_ != 0 ) {
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u64* ptempmem = recAllocStackMem(8, 8);
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*ptempmem = (op == 1) ? (s64)_ImmU_ : (u64)_ImmU_; // for ORI, IMM is sign-extended, for the others its zero-extended
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u32* ptempmem = recAllocStackMem(8, 8);
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ptempmem[0] = _ImmU_;
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ptempmem[1] = 0;
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if( EEREC_T != EEREC_S ) MOVQRtoR(EEREC_T, EEREC_S);
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LogicalOpMtoR(EEREC_T, (u32)ptempmem, op);
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@ -375,9 +376,9 @@ void recLogicalOpI(int info, int op)
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if( op == 0 ) {
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if ( _ImmU_ != 0 ) {
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u64* ptempmem = recAllocStackMem(8, 8);
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*ptempmem = (u64)_ImmU_; // for ANDI, IMM is zero-extended
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u32* ptempmem = recAllocStackMem(8, 8);
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ptempmem[0] = _ImmU_;
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ptempmem[1] = 0;
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MOVDMtoMMX(rtreg, (int)&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ]);
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PANDMtoR(rtreg, (u32)ptempmem);
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}
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@ -386,41 +387,32 @@ void recLogicalOpI(int info, int op)
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else {
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MOVQMtoR(rtreg, (int)&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ]);
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if ( _ImmU_ != 0 ) {
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u64* ptempmem = recAllocStackMem(8, 8);
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*ptempmem = (op == 1) ? (s64)_ImmU_ : (u64)_ImmU_; // for ORI, IMM is sign-extended, for the others its zero-extended
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u32* ptempmem = recAllocStackMem(8, 8);
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ptempmem[0] = _ImmU_;
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ptempmem[1] = 0;
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LogicalOpMtoR(rtreg, (u32)ptempmem, op);
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}
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}
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}
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else {
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//SysPrintf("recLogicalOpI\n");
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if ( _ImmU_ != 0 )
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{
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if( _Rt_ == _Rs_ ) {
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LogicalOp32ItoM((int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ], _ImmU_, op);
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if (op == 0) {
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if ( EEINST_ISLIVE1(_Rt_) ) MOV32ItoM( (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 1 ], 0 );
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else EEINST_RESETHASLIVE1(_Rt_);
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}
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else if ( EEINST_ISLIVE1(_Rt_) && _ImmSB_ && (op == 1) ) MOV32ItoM( (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 1 ], 0xffffffff );
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}
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else {
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MOV32MtoR( EAX, (int)&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ] );
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if( op != 0 && EEINST_ISLIVE1(_Rt_) )
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MOV32MtoR( EDX, (int)&cpuRegs.GPR.r[ _Rs_ ].UL[ 1 ] );
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LogicalOp32ItoR( EAX, _ImmU_, op);
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if( op != 0 && EEINST_ISLIVE1(_Rt_) )
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MOV32RtoM( (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 1 ], EDX );
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MOV32RtoM( (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ], EAX );
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}
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if (op == 0) {
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if ( EEINST_ISLIVE1(_Rt_) ) MOV32ItoM( (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 1 ], 0 );
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else EEINST_RESETHASLIVE1(_Rt_);
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}
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else if ( EEINST_ISLIVE1(_Rt_) ) {
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if (_ImmSB_ && (op == 1)) MOV32ItoM( (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 1 ], 0xffffffff );
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else {
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MOV32MtoR( EAX, (int)&cpuRegs.GPR.r[ _Rs_ ].UL[ 1 ] );
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MOV32RtoM( (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 1 ], EAX );
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}
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}
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if( op == 0 ) {
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if( EEINST_ISLIVE1(_Rt_ ) ) MOV32ItoM( (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 1 ], 0 );
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else EEINST_RESETHASLIVE1(_Rt_);
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}
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}
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else
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@ -433,11 +425,11 @@ void recLogicalOpI(int info, int op)
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else {
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if( _Rt_ != _Rs_ ) {
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MOV32MtoR(EAX, (int)&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ] );
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if( EEINST_ISLIVE1(_Rt_ ) )
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MOV32MtoR(EDX, (int)&cpuRegs.GPR.r[ _Rs_ ].UL[ 1 ] );
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MOV32RtoM((int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ], EAX );
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if( EEINST_ISLIVE1(_Rt_ ) ) {
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MOV32MtoR(EAX, (int)&cpuRegs.GPR.r[ _Rs_ ].UL[ 1 ] );
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MOV32RtoM((int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 1 ], EAX );
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}
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if( EEINST_ISLIVE1(_Rt_ ) )
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MOV32RtoM((int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 1 ], EDX );
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}
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}
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@ -456,7 +448,7 @@ EERECOMPILE_CODEX(eeRecompileCode1, ANDI);
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////////////////////////////////////////////////////
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void recORI_const()
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{
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g_cpuConstRegs[_Rt_].UD[0] = g_cpuConstRegs[_Rs_].UD[0] | (s64)_ImmU_;
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g_cpuConstRegs[_Rt_].UD[0] = g_cpuConstRegs[_Rs_].UD[0] | (u64)_ImmU_; // Zero-extended Immediate
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}
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void recORI_(int info)
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@ -469,7 +461,7 @@ EERECOMPILE_CODEX(eeRecompileCode1, ORI);
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////////////////////////////////////////////////////
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void recXORI_const()
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{
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g_cpuConstRegs[_Rt_].UD[0] = g_cpuConstRegs[_Rs_].UD[0] ^ (u64)_ImmU_; // should be zero-extended
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g_cpuConstRegs[_Rt_].UD[0] = g_cpuConstRegs[_Rs_].UD[0] ^ (u64)_ImmU_; // Zero-extended Immediate
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}
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void recXORI_(int info)
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