From 60f42192e9441bff95e9ea2911cc955ae0b084c7 Mon Sep 17 00:00:00 2001 From: cottonvibes Date: Tue, 7 Oct 2008 22:44:48 +0000 Subject: [PATCH] the document i was reading had incorrect information for the ORI opcode (said it should be a sign-extended immediate, but its really supposed to be zero-extended) took me hours to figure out the problem >< anyways, I fixed the opcodes correctly... git-svn-id: http://pcsx2-playground.googlecode.com/svn/trunk@175 a6443dda-0b58-4228-96e9-037be469359c --- pcsx2/Interpreter.c | 6 ++-- pcsx2/x86/ix86-32/iR5900AritImm.c | 56 +++++++++++++------------------ 2 files changed, 27 insertions(+), 35 deletions(-) diff --git a/pcsx2/Interpreter.c b/pcsx2/Interpreter.c index 0d1dcfe393..b674cfcbc2 100644 --- a/pcsx2/Interpreter.c +++ b/pcsx2/Interpreter.c @@ -147,9 +147,9 @@ void ADDI() { if (!_Rt_) return; cpuRegs.GPR.r[_Rt_].UD[0] = cpuRegs.GPR.r[_Rs_ void ADDIU() { if (!_Rt_) return; cpuRegs.GPR.r[_Rt_].UD[0] = cpuRegs.GPR.r[_Rs_].SL[0] + _Imm_; }// Rt = Rs + Im signed !!! void DADDI() { if (!_Rt_) return; cpuRegs.GPR.r[_Rt_].UD[0] = cpuRegs.GPR.r[_Rs_].SD[0] + _Imm_; }// Rt = Rs + Im void DADDIU() { if (!_Rt_) return; cpuRegs.GPR.r[_Rt_].UD[0] = cpuRegs.GPR.r[_Rs_].SD[0] + _Imm_; }// Rt = Rs + Im -void ANDI() { if (!_Rt_) return; cpuRegs.GPR.r[_Rt_].UD[0] = cpuRegs.GPR.r[_Rs_].UD[0] & (u64)_ImmU_; } // Rt = Rs And Im (zero-extended) -void ORI() { if (!_Rt_) return; cpuRegs.GPR.r[_Rt_].UD[0] = cpuRegs.GPR.r[_Rs_].UD[0] | (s64)_ImmU_; } // Rt = Rs Or Im (sign-extended) -void XORI() { if (!_Rt_) return; cpuRegs.GPR.r[_Rt_].UD[0] = cpuRegs.GPR.r[_Rs_].UD[0] ^ (u64)_ImmU_; } // Rt = Rs Xor Im (zero-extended) +void ANDI() { if (!_Rt_) return; cpuRegs.GPR.r[_Rt_].UD[0] = cpuRegs.GPR.r[_Rs_].UD[0] & (u64)_ImmU_; } // Rt = Rs And Im (zero-extended) +void ORI() { if (!_Rt_) return; cpuRegs.GPR.r[_Rt_].UD[0] = cpuRegs.GPR.r[_Rs_].UD[0] | (u64)_ImmU_; } // Rt = Rs Or Im (zero-extended) +void XORI() { if (!_Rt_) return; cpuRegs.GPR.r[_Rt_].UD[0] = cpuRegs.GPR.r[_Rs_].UD[0] ^ (u64)_ImmU_; } // Rt = Rs Xor Im (zero-extended) void SLTI() { if (!_Rt_) return; cpuRegs.GPR.r[_Rt_].UD[0] = cpuRegs.GPR.r[_Rs_].SD[0] < (s64)(_Imm_); } // Rt = Rs < Im (signed) void SLTIU() { if (!_Rt_) return; cpuRegs.GPR.r[_Rt_].UD[0] = cpuRegs.GPR.r[_Rs_].UD[0] < (u64)(_Imm_); } // Rt = Rs < Im (unsigned) diff --git a/pcsx2/x86/ix86-32/iR5900AritImm.c b/pcsx2/x86/ix86-32/iR5900AritImm.c index 155911300b..fe6b8ae01d 100644 --- a/pcsx2/x86/ix86-32/iR5900AritImm.c +++ b/pcsx2/x86/ix86-32/iR5900AritImm.c @@ -340,7 +340,7 @@ EERECOMPILE_CODEX(eeRecompileCode1, SLTI); //// ANDI void recANDI_const() { - g_cpuConstRegs[_Rt_].UD[0] = g_cpuConstRegs[_Rs_].UD[0] & (u64)_ImmU_; // should be zero-extended + g_cpuConstRegs[_Rt_].UD[0] = g_cpuConstRegs[_Rs_].UD[0] & (u64)_ImmU_; // Zero-extended Immediate } extern void LogicalOpRtoR(x86MMXRegType to, x86MMXRegType from, int op); @@ -356,8 +356,9 @@ void recLogicalOpI(int info, int op) SetMMXstate(); if( _ImmU_ != 0 ) { - u64* ptempmem = recAllocStackMem(8, 8); - *ptempmem = (op == 1) ? (s64)_ImmU_ : (u64)_ImmU_; // for ORI, IMM is sign-extended, for the others its zero-extended + u32* ptempmem = recAllocStackMem(8, 8); + ptempmem[0] = _ImmU_; + ptempmem[1] = 0; if( EEREC_T != EEREC_S ) MOVQRtoR(EEREC_T, EEREC_S); LogicalOpMtoR(EEREC_T, (u32)ptempmem, op); @@ -375,9 +376,9 @@ void recLogicalOpI(int info, int op) if( op == 0 ) { if ( _ImmU_ != 0 ) { - u64* ptempmem = recAllocStackMem(8, 8); - *ptempmem = (u64)_ImmU_; // for ANDI, IMM is zero-extended - + u32* ptempmem = recAllocStackMem(8, 8); + ptempmem[0] = _ImmU_; + ptempmem[1] = 0; MOVDMtoMMX(rtreg, (int)&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ]); PANDMtoR(rtreg, (u32)ptempmem); } @@ -386,41 +387,32 @@ void recLogicalOpI(int info, int op) else { MOVQMtoR(rtreg, (int)&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ]); if ( _ImmU_ != 0 ) { - u64* ptempmem = recAllocStackMem(8, 8); - *ptempmem = (op == 1) ? (s64)_ImmU_ : (u64)_ImmU_; // for ORI, IMM is sign-extended, for the others its zero-extended - + u32* ptempmem = recAllocStackMem(8, 8); + ptempmem[0] = _ImmU_; + ptempmem[1] = 0; LogicalOpMtoR(rtreg, (u32)ptempmem, op); } } } else { - //SysPrintf("recLogicalOpI\n"); if ( _ImmU_ != 0 ) { if( _Rt_ == _Rs_ ) { LogicalOp32ItoM((int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ], _ImmU_, op); - if (op == 0) { - if ( EEINST_ISLIVE1(_Rt_) ) MOV32ItoM( (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 1 ], 0 ); - else EEINST_RESETHASLIVE1(_Rt_); - } - else if ( EEINST_ISLIVE1(_Rt_) && _ImmSB_ && (op == 1) ) MOV32ItoM( (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 1 ], 0xffffffff ); } else { MOV32MtoR( EAX, (int)&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ] ); + if( op != 0 && EEINST_ISLIVE1(_Rt_) ) + MOV32MtoR( EDX, (int)&cpuRegs.GPR.r[ _Rs_ ].UL[ 1 ] ); LogicalOp32ItoR( EAX, _ImmU_, op); + if( op != 0 && EEINST_ISLIVE1(_Rt_) ) + MOV32RtoM( (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 1 ], EDX ); MOV32RtoM( (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ], EAX ); + } - if (op == 0) { - if ( EEINST_ISLIVE1(_Rt_) ) MOV32ItoM( (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 1 ], 0 ); - else EEINST_RESETHASLIVE1(_Rt_); - } - else if ( EEINST_ISLIVE1(_Rt_) ) { - if (_ImmSB_ && (op == 1)) MOV32ItoM( (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 1 ], 0xffffffff ); - else { - MOV32MtoR( EAX, (int)&cpuRegs.GPR.r[ _Rs_ ].UL[ 1 ] ); - MOV32RtoM( (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 1 ], EAX ); - } - } + if( op == 0 ) { + if( EEINST_ISLIVE1(_Rt_ ) ) MOV32ItoM( (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 1 ], 0 ); + else EEINST_RESETHASLIVE1(_Rt_); } } else @@ -433,11 +425,11 @@ void recLogicalOpI(int info, int op) else { if( _Rt_ != _Rs_ ) { MOV32MtoR(EAX, (int)&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ] ); + if( EEINST_ISLIVE1(_Rt_ ) ) + MOV32MtoR(EDX, (int)&cpuRegs.GPR.r[ _Rs_ ].UL[ 1 ] ); MOV32RtoM((int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ], EAX ); - if( EEINST_ISLIVE1(_Rt_ ) ) { - MOV32MtoR(EAX, (int)&cpuRegs.GPR.r[ _Rs_ ].UL[ 1 ] ); - MOV32RtoM((int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 1 ], EAX ); - } + if( EEINST_ISLIVE1(_Rt_ ) ) + MOV32RtoM((int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 1 ], EDX ); } } @@ -456,7 +448,7 @@ EERECOMPILE_CODEX(eeRecompileCode1, ANDI); //////////////////////////////////////////////////// void recORI_const() { - g_cpuConstRegs[_Rt_].UD[0] = g_cpuConstRegs[_Rs_].UD[0] | (s64)_ImmU_; + g_cpuConstRegs[_Rt_].UD[0] = g_cpuConstRegs[_Rs_].UD[0] | (u64)_ImmU_; // Zero-extended Immediate } void recORI_(int info) @@ -469,7 +461,7 @@ EERECOMPILE_CODEX(eeRecompileCode1, ORI); //////////////////////////////////////////////////// void recXORI_const() { - g_cpuConstRegs[_Rt_].UD[0] = g_cpuConstRegs[_Rs_].UD[0] ^ (u64)_ImmU_; // should be zero-extended + g_cpuConstRegs[_Rt_].UD[0] = g_cpuConstRegs[_Rs_].UD[0] ^ (u64)_ImmU_; // Zero-extended Immediate } void recXORI_(int info)