mirror of https://github.com/PCSX2/pcsx2.git
dmac: madr msb bit is fixed to 0 in 8/9 channels
Fix another dmac tests :)
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@ -374,6 +374,20 @@ __fi bool dmacWrite32( u32 mem, mem32_t& value )
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return false;
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return false;
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}
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}
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icase(fromSPR_MADR)
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{
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// SPR bit is fixed at 0 for this channel
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psHu32(mem) = value & 0x7FFFFFFF;
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return false;
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}
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icase(toSPR_MADR)
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{
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// SPR bit is fixed at 0 for this channel
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psHu32(mem) = value & 0x7FFFFFFF;
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return false;
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}
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icase(fromSPR_SADR)
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icase(fromSPR_SADR)
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{
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{
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// Address must be QW aligned and fit in the 16K range of SPR
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// Address must be QW aligned and fit in the 16K range of SPR
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