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EE/COP2: Check for likely zero clears in COP2 synced ops

This commit is contained in:
refractionpcsx2 2023-04-09 02:00:28 +01:00
parent 8b32382e1b
commit 5e27c65615
1 changed files with 3 additions and 1 deletions
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4
pcsx2/x86/iR5900Analysis.cpp
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@ -275,6 +275,8 @@ void COP2MicroFinishPass::Run(u32 start, u32 end, EEINST* inst_cache)
// //
const bool is_lqc_sqc = (_Opcode_ == 066 || _Opcode_ == 076); const bool is_lqc_sqc = (_Opcode_ == 066 || _Opcode_ == 076);
const bool is_non_interlocked_move = (_Opcode_ == 022 && _Rs_ < 020 && ((cpuRegs.code & 1) == 0)); const bool is_non_interlocked_move = (_Opcode_ == 022 && _Rs_ < 020 && ((cpuRegs.code & 1) == 0));
// Moving zero to the VU registers, so likely removing a loop/lock.
const bool likely_clear = _Opcode_ == 022 && _Rs_ > 004 && _Rt_ == 000;
if (needs_vu0_sync && (is_lqc_sqc || is_non_interlocked_move)) if (needs_vu0_sync && (is_lqc_sqc || is_non_interlocked_move))
{ {
bool following_needs_finish = false; bool following_needs_finish = false;
@ -304,7 +306,7 @@ void COP2MicroFinishPass::Run(u32 start, u32 end, EEINST* inst_cache)
else else
{ {
inst->info |= EEINST_COP2_FLUSH_VU0_REGISTERS | EEINST_COP2_SYNC_VU0; inst->info |= EEINST_COP2_FLUSH_VU0_REGISTERS | EEINST_COP2_SYNC_VU0;
needs_vu0_sync = block_interlocked; needs_vu0_sync = block_interlocked || (is_non_interlocked_move && likely_clear);
needs_vu0_finish = true; needs_vu0_finish = true;
} }