From 5e27c6561541c48d6a0722f4db15331feb649b37 Mon Sep 17 00:00:00 2001 From: refractionpcsx2 Date: Sun, 9 Apr 2023 02:00:28 +0100 Subject: [PATCH] EE/COP2: Check for likely zero clears in COP2 synced ops --- pcsx2/x86/iR5900Analysis.cpp | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/pcsx2/x86/iR5900Analysis.cpp b/pcsx2/x86/iR5900Analysis.cpp index f48cc99378..4a894423f8 100644 --- a/pcsx2/x86/iR5900Analysis.cpp +++ b/pcsx2/x86/iR5900Analysis.cpp @@ -275,6 +275,8 @@ void COP2MicroFinishPass::Run(u32 start, u32 end, EEINST* inst_cache) // const bool is_lqc_sqc = (_Opcode_ == 066 || _Opcode_ == 076); const bool is_non_interlocked_move = (_Opcode_ == 022 && _Rs_ < 020 && ((cpuRegs.code & 1) == 0)); + // Moving zero to the VU registers, so likely removing a loop/lock. + const bool likely_clear = _Opcode_ == 022 && _Rs_ > 004 && _Rt_ == 000; if (needs_vu0_sync && (is_lqc_sqc || is_non_interlocked_move)) { bool following_needs_finish = false; @@ -304,7 +306,7 @@ void COP2MicroFinishPass::Run(u32 start, u32 end, EEINST* inst_cache) else { inst->info |= EEINST_COP2_FLUSH_VU0_REGISTERS | EEINST_COP2_SYNC_VU0; - needs_vu0_sync = block_interlocked; + needs_vu0_sync = block_interlocked || (is_non_interlocked_move && likely_clear); needs_vu0_finish = true; }