mirror of https://github.com/PCSX2/pcsx2.git
x86emitter: remove MMX support
This commit is contained in:
Gregory Hainaut
parent
0f81482ed1
commit
5140a2e107
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@ -30,11 +30,7 @@ struct _SimdShiftHelper
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void operator()( const xRegisterSSE& to, const xRegisterSSE& from ) const;
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void operator()( const xRegisterSSE& to, const xIndirectVoid& from ) const;
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void operator()( const xRegisterMMX& to, const xRegisterMMX& from ) const;
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void operator()( const xRegisterMMX& to, const xIndirectVoid& from ) const;
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void operator()( const xRegisterSSE& to, u8 imm8 ) const;
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void operator()( const xRegisterMMX& to, u8 imm8 ) const;
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};
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// --------------------------------------------------------------------------------------
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@ -96,12 +96,10 @@ struct xImplSimd_PMinMax
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{
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// Compare packed unsigned byte integers in dest to src and store packed min/max
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// values in dest.
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// Operation can be performed on either MMX or SSE operands.
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const xImplSimd_DestRegEither UB;
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// Compare packed signed word integers in dest to src and store packed min/max
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// values in dest.
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// Operation can be performed on either MMX or SSE operands.
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const xImplSimd_DestRegEither SW;
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// [SSE-4.1] Compare packed signed byte integers in dest to src and store
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@ -56,17 +56,8 @@ struct xImplSimd_DestSSE_CmpImm
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void operator()( const xRegisterSSE& to, const xIndirectVoid& from, SSE2_ComparisonType imm ) const;
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};
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struct xImplSimd_DestRegImmMMX
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{
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u8 Prefix;
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u16 Opcode;
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void operator()( const xRegisterMMX& to, const xRegisterMMX& from, u8 imm ) const;
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void operator()( const xRegisterMMX& to, const xIndirectVoid& from, u8 imm ) const;
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};
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// ------------------------------------------------------------------------
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// For implementing MMX/SSE operations that have reg,reg/rm forms only,
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// For implementing SSE operations that have reg,reg/rm forms only,
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// but accept either MM or XMM destinations (most PADD/PSUB and other P arithmetic ops).
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//
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struct xImplSimd_DestRegEither
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@ -76,9 +67,6 @@ struct xImplSimd_DestRegEither
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void operator()( const xRegisterSSE& to, const xRegisterSSE& from ) const;
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void operator()( const xRegisterSSE& to, const xIndirectVoid& from ) const;
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void operator()( const xRegisterMMX& to, const xRegisterMMX& from ) const;
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void operator()( const xRegisterMMX& to, const xIndirectVoid& from ) const;
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};
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} // end namespace x86Emitter
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@ -36,10 +36,6 @@ struct xImplSimd_Shuffle
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// --------------------------------------------------------------------------------------
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struct xImplSimd_PShuffle
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{
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// Copies words from src and inserts them into dest at word locations selected with
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// the order operand (8 bit immediate).
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const xImplSimd_DestRegImmMMX W;
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// Copies doublewords from src and inserts them into dest at dword locations selected
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// with the order operand (8 bit immediate).
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const xImplSimd_DestRegImmSSE D;
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@ -61,7 +57,6 @@ struct xImplSimd_PShuffle
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// byte in dest. The value of each index is the least significant 4 bits (128-bit
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// operation) or 3 bits (64-bit operation) of the shuffle control byte.
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//
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// Operands can be MMX or XMM registers.
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const xImplSimd_DestRegEither B;
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// below is my test bed for a new system, free of subclasses. Was supposed to improve intellisense
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@ -70,8 +65,6 @@ struct xImplSimd_PShuffle
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#if 0
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// Copies words from src and inserts them into dest at word locations selected with
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// the order operand (8 bit immediate).
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void W( const xRegisterMMX& to, const xRegisterMMX& from, u8 imm ) const { xOpWrite0F( 0x70, to, from, imm ); }
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void W( const xRegisterMMX& to, const xIndirectVoid& from, u8 imm ) const { xOpWrite0F( 0x70, to, from, imm ); }
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// Copies doublewords from src and inserts them into dest at dword locations selected
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// with the order operand (8 bit immediate).
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@ -97,11 +90,8 @@ struct xImplSimd_PShuffle
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// byte in dest. The value of each index is the least significant 4 bits (128-bit
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// operation) or 3 bits (64-bit operation) of the shuffle control byte.
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//
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// Operands can be MMX or XMM registers.
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void B( const xRegisterSSE& to, const xRegisterSSE& from ) const { OpWriteSSE( 0x66, 0x0038 ); }
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void B( const xRegisterSSE& to, const xIndirectVoid& from ) const { OpWriteSSE( 0x66, 0x0038 ); }
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void B( const xRegisterMMX& to, const xRegisterMMX& from ) const { OpWriteSSE( 0x00, 0x0038 ); }
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void B( const xRegisterMMX& to, const xIndirectVoid& from ) const { OpWriteSSE( 0x00, 0x0038 ); }
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#endif
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};
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@ -214,9 +204,6 @@ struct xImplSimd_PInsert
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void W( const xRegisterSSE& to, const xRegister32& from, u8 imm8 ) const;
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void W( const xRegisterSSE& to, const xIndirectVoid& from, u8 imm8 ) const;
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void W( const xRegisterMMX& to, const xRegister32& from, u8 imm8 ) const;
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void W( const xRegisterMMX& to, const xIndirectVoid& from, u8 imm8 ) const;
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// [SSE-4.1] Allowed with SSE registers only (MMX regs are invalid)
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xImplSimd_InsertExtractHelper B;
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@ -239,7 +226,6 @@ struct SimdImpl_PExtract
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// [SSE-4.1] Note: Indirect memory forms of this instruction are an SSE-4.1 extension!
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//
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void W( const xRegister32& to, const xRegisterSSE& from, u8 imm8 ) const;
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void W( const xRegister32& to, const xRegisterMMX& from, u8 imm8 ) const;
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void W( const xIndirectVoid& dest, const xRegisterSSE& from, u8 imm8 ) const;
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// [SSE-4.1] Copies the byte element specified by imm8 from src to dest. The upper bits
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@ -339,22 +339,10 @@ namespace x86Emitter
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extern void xMOVDZX( const xRegisterSSE& to, const xRegister32or64& from );
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extern void xMOVDZX( const xRegisterSSE& to, const xIndirectVoid& src );
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extern void xMOVDZX( const xRegisterMMX& to, const xRegister32or64& from );
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extern void xMOVDZX( const xRegisterMMX& to, const xIndirectVoid& src );
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extern void xMOVD( const xRegister32or64& to, const xRegisterSSE& from );
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extern void xMOVD( const xIndirectVoid& dest, const xRegisterSSE& from );
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extern void xMOVD( const xRegister32or64& to, const xRegisterMMX& from );
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extern void xMOVD( const xIndirectVoid& dest, const xRegisterMMX& from );
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extern void xMOVQ( const xRegisterMMX& to, const xRegisterMMX& from );
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extern void xMOVQ( const xRegisterMMX& to, const xRegisterSSE& from );
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extern void xMOVQ( const xRegisterSSE& to, const xRegisterMMX& from );
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extern void xMOVQ( const xIndirectVoid& dest, const xRegisterSSE& from );
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extern void xMOVQ( const xIndirectVoid& dest, const xRegisterMMX& from );
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extern void xMOVQ( const xRegisterMMX& to, const xIndirectVoid& src );
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extern void xMOVQZX( const xRegisterSSE& to, const xIndirectVoid& src );
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extern void xMOVQZX( const xRegisterSSE& to, const xRegisterSSE& from );
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@ -372,17 +360,13 @@ namespace x86Emitter
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extern void xMOVNTPD( const xIndirectVoid& to, const xRegisterSSE& from );
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extern void xMOVNTPS( const xIndirectVoid& to, const xRegisterSSE& from );
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extern void xMOVNTQ( const xIndirectVoid& to, const xRegisterMMX& from );
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extern void xMOVMSKPS( const xRegister32or64& to, const xRegisterSSE& from );
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extern void xMOVMSKPD( const xRegister32or64& to, const xRegisterSSE& from );
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extern void xMASKMOV( const xRegisterSSE& to, const xRegisterSSE& from );
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extern void xMASKMOV( const xRegisterMMX& to, const xRegisterMMX& from );
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extern void xPMOVMSKB( const xRegister32or64& to, const xRegisterSSE& from );
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extern void xPMOVMSKB( const xRegister32or64& to, const xRegisterMMX& from );
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extern void xPALIGNR( const xRegisterSSE& to, const xRegisterSSE& from, u8 imm8 );
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extern void xPALIGNR( const xRegisterMMX& to, const xRegisterMMX& from, u8 imm8 );
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// ------------------------------------------------------------------------
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@ -455,29 +439,21 @@ namespace x86Emitter
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extern void xCVTPD2DQ( const xRegisterSSE& to, const xRegisterSSE& from );
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extern void xCVTPD2DQ( const xRegisterSSE& to, const xIndirect128& from );
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extern void xCVTPD2PI( const xRegisterMMX& to, const xRegisterSSE& from );
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extern void xCVTPD2PI( const xRegisterMMX& to, const xIndirect128& from );
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extern void xCVTPD2PS( const xRegisterSSE& to, const xRegisterSSE& from );
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extern void xCVTPD2PS( const xRegisterSSE& to, const xIndirect128& from );
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extern void xCVTPI2PD( const xRegisterSSE& to, const xRegisterMMX& from );
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extern void xCVTPI2PD( const xRegisterSSE& to, const xIndirect64& from );
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extern void xCVTPI2PS( const xRegisterSSE& to, const xRegisterMMX& from );
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extern void xCVTPI2PS( const xRegisterSSE& to, const xIndirect64& from );
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extern void xCVTPS2DQ( const xRegisterSSE& to, const xRegisterSSE& from );
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extern void xCVTPS2DQ( const xRegisterSSE& to, const xIndirect128& from );
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extern void xCVTPS2PD( const xRegisterSSE& to, const xRegisterSSE& from );
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extern void xCVTPS2PD( const xRegisterSSE& to, const xIndirect64& from );
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extern void xCVTPS2PI( const xRegisterMMX& to, const xRegisterSSE& from );
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extern void xCVTPS2PI( const xRegisterMMX& to, const xIndirect64& from );
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extern void xCVTSD2SI( const xRegister32or64& to, const xRegisterSSE& from );
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extern void xCVTSD2SI( const xRegister32or64& to, const xIndirect64& from );
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extern void xCVTSD2SS( const xRegisterSSE& to, const xRegisterSSE& from );
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extern void xCVTSD2SS( const xRegisterSSE& to, const xIndirect64& from );
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extern void xCVTSI2SD( const xRegisterMMX& to, const xRegister32or64& from );
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extern void xCVTSI2SD( const xRegisterMMX& to, const xIndirect32& from );
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extern void xCVTSI2SS( const xRegisterSSE& to, const xRegister32or64& from );
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extern void xCVTSI2SS( const xRegisterSSE& to, const xIndirect32& from );
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@ -488,12 +464,8 @@ namespace x86Emitter
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extern void xCVTTPD2DQ( const xRegisterSSE& to, const xRegisterSSE& from );
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extern void xCVTTPD2DQ( const xRegisterSSE& to, const xIndirect128& from );
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extern void xCVTTPD2PI( const xRegisterMMX& to, const xRegisterSSE& from );
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extern void xCVTTPD2PI( const xRegisterMMX& to, const xIndirect128& from );
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extern void xCVTTPS2DQ( const xRegisterSSE& to, const xRegisterSSE& from );
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extern void xCVTTPS2DQ( const xRegisterSSE& to, const xIndirect128& from );
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extern void xCVTTPS2PI( const xRegisterMMX& to, const xRegisterSSE& from );
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extern void xCVTTPS2PI( const xRegisterMMX& to, const xIndirect64& from );
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extern void xCVTTSD2SI( const xRegister32or64& to, const xRegisterSSE& from );
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extern void xCVTTSD2SI( const xRegister32or64& to, const xIndirect64& from );
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@ -21,5 +21,4 @@
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// general types
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typedef int x86IntRegType;
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typedef int x86MMXRegType;
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typedef int x86SSERegType;
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@ -18,12 +18,10 @@
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#ifdef __x86_64__
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static const uint iREGCNT_XMM = 16;
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static const uint iREGCNT_GPR = 16;
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static const uint iREGCNT_MMX = 8; // FIXME: port the code and remove MMX
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#else
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// Register counts for x86/32 mode:
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static const uint iREGCNT_XMM = 8;
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static const uint iREGCNT_GPR = 8;
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static const uint iREGCNT_MMX = 8;
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#endif
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enum XMMSSEType
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@ -233,7 +231,7 @@ template< typename T > void xWrite( T val );
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// --------------------------------------------------------------------------------------
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// xRegisterBase - type-unsafe x86 register representation.
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// --------------------------------------------------------------------------------------
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// Unless doing some fundamental stuff, use the friendly xRegister32/16/8 and xRegisterSSE/MMX
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// Unless doing some fundamental stuff, use the friendly xRegister32/16/8 and xRegisterSSE
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// instead, which are built using this class and provide strict register type safety when
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// passed into emitter instructions.
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//
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@ -264,14 +262,13 @@ template< typename T > void xWrite( T val );
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// Returns true if the register is a valid accumulator: Eax, Ax, Al, XMM0.
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bool IsAccumulator() const { return Id == 0; }
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// IsSIMD: returns true if the register is a valid MMX or XMM register.
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// IsSIMD: returns true if the register is a valid XMM register.
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bool IsSIMD() const { return GetOperandSize() == 16; }
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// IsWide: return true if the register is 64 bits (requires a wide op on the rex prefix)
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#ifdef __x86_64__
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// No MMX on 64 bits, let's directly uses GPR
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bool IsSIMD() const { return GetOperandSize() == 16; }
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bool IsWide() const { return GetOperandSize() == 8; }
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#else
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bool IsSIMD() const { return GetOperandSize() == 8 || GetOperandSize() == 16; }
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bool IsWide() const { return false; } // no 64 bits GPR
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#endif
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// return true if the register is a valid YMM register
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@ -359,29 +356,10 @@ template< typename T > void xWrite( T val );
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};
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// --------------------------------------------------------------------------------------
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// xRegisterMMX/SSE - Represents either a 64 bit or 128 bit SIMD register
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// xRegisterSSE - Represents either a 64 bit or 128 bit SIMD register
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// --------------------------------------------------------------------------------------
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// This register type is provided to allow legal syntax for instructions that accept either
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// an XMM or MMX register as a parameter, but do not allow for a GPR.
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class xRegisterMMX : public xRegisterBase
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{
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typedef xRegisterBase _parent;
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public:
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xRegisterMMX(): _parent() {
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#ifdef __x86_64__
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pxAssert(0); // Sorry but code must be ported
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#endif
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}
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//xRegisterMMX( const xRegisterBase& src ) : _parent( src ) {}
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explicit xRegisterMMX( int regId ) : _parent( regId ) {}
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virtual uint GetOperandSize() const { return 8; }
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bool operator==( const xRegisterMMX& src ) const { return this->Id == src.Id; }
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bool operator!=( const xRegisterMMX& src ) const { return this->Id != src.Id; }
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};
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// This register type is provided to allow legal syntax for instructions that accept
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// an XMM register as a parameter, but do not allow for a GPR.
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class xRegisterSSE : public xRegisterBase
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{
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@ -473,12 +451,6 @@ template< typename T > void xWrite( T val );
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return xRegister16( xRegId_Empty );
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}
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// FIXME remove it in x86 64
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operator xRegisterMMX() const
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{
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return xRegisterMMX( xRegId_Empty );
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}
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operator xRegisterSSE() const
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{
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return xRegisterSSE( xRegId_Empty );
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@ -551,10 +523,6 @@ template< typename T > void xWrite( T val );
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xmm8, xmm9, xmm10, xmm11,
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xmm12, xmm13, xmm14, xmm15;
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extern const xRegisterMMX
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mm0, mm1, mm2, mm3,
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mm4, mm5, mm6, mm7;
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extern const xAddressReg
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rax, rbx, rcx, rdx,
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rsi, rdi, rbp, rsp,
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@ -943,7 +911,6 @@ template< typename T > void xWrite( T val );
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typedef xDirectOrIndirect<xRegister8,xIndirect8> xDirectOrIndirect8;
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typedef xDirectOrIndirect<xRegister16,xIndirect16> xDirectOrIndirect16;
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typedef xDirectOrIndirect<xRegister32,xIndirect32> xDirectOrIndirect32;
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typedef xDirectOrIndirect<xRegisterMMX,xIndirect64> xDirectOrIndirect64;
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typedef xDirectOrIndirect<xRegisterSSE,xIndirect128> xDirectOrIndirect128;
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#endif
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@ -145,29 +145,21 @@ __fi void xCVTDQ2PS( const xRegisterSSE& to, const xIndirect128& from ) { OpWri
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__fi void xCVTPD2DQ( const xRegisterSSE& to, const xRegisterSSE& from ) { OpWriteSSE( 0xf2, 0xe6 ); }
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__fi void xCVTPD2DQ( const xRegisterSSE& to, const xIndirect128& from ) { OpWriteSSE( 0xf2, 0xe6 ); }
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__fi void xCVTPD2PI( const xRegisterMMX& to, const xRegisterSSE& from ) { OpWriteSSE( 0x66, 0x2d ); }
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__fi void xCVTPD2PI( const xRegisterMMX& to, const xIndirect128& from ) { OpWriteSSE( 0x66, 0x2d ); }
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__fi void xCVTPD2PS( const xRegisterSSE& to, const xRegisterSSE& from ) { OpWriteSSE( 0x66, 0x5a ); }
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__fi void xCVTPD2PS( const xRegisterSSE& to, const xIndirect128& from ) { OpWriteSSE( 0x66, 0x5a ); }
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__fi void xCVTPI2PD( const xRegisterSSE& to, const xRegisterMMX& from ) { OpWriteSSE( 0x66, 0x2a ); }
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__fi void xCVTPI2PD( const xRegisterSSE& to, const xIndirect64& from ) { OpWriteSSE( 0x66, 0x2a ); }
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__fi void xCVTPI2PS( const xRegisterSSE& to, const xRegisterMMX& from ) { OpWriteSSE( 0x00, 0x2a ); }
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__fi void xCVTPI2PS( const xRegisterSSE& to, const xIndirect64& from ) { OpWriteSSE( 0x00, 0x2a ); }
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__fi void xCVTPS2DQ( const xRegisterSSE& to, const xRegisterSSE& from ) { OpWriteSSE( 0x66, 0x5b ); }
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__fi void xCVTPS2DQ( const xRegisterSSE& to, const xIndirect128& from ) { OpWriteSSE( 0x66, 0x5b ); }
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__fi void xCVTPS2PD( const xRegisterSSE& to, const xRegisterSSE& from ) { OpWriteSSE( 0x00, 0x5a ); }
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__fi void xCVTPS2PD( const xRegisterSSE& to, const xIndirect64& from ) { OpWriteSSE( 0x00, 0x5a ); }
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__fi void xCVTPS2PI( const xRegisterMMX& to, const xRegisterSSE& from ) { OpWriteSSE( 0x00, 0x2d ); }
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__fi void xCVTPS2PI( const xRegisterMMX& to, const xIndirect64& from ) { OpWriteSSE( 0x00, 0x2d ); }
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__fi void xCVTSD2SI( const xRegister32or64& to, const xRegisterSSE& from ) { OpWriteSSE( 0xf2, 0x2d ); }
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__fi void xCVTSD2SI( const xRegister32or64& to, const xIndirect64& from ) { OpWriteSSE( 0xf2, 0x2d ); }
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__fi void xCVTSD2SS( const xRegisterSSE& to, const xRegisterSSE& from ) { OpWriteSSE( 0xf2, 0x5a ); }
|
||||
__fi void xCVTSD2SS( const xRegisterSSE& to, const xIndirect64& from ) { OpWriteSSE( 0xf2, 0x5a ); }
|
||||
__fi void xCVTSI2SD( const xRegisterMMX& to, const xRegister32or64& from ) { OpWriteSSE( 0xf2, 0x2a ); }
|
||||
__fi void xCVTSI2SD( const xRegisterMMX& to, const xIndirect32& from ) { OpWriteSSE( 0xf2, 0x2a ); }
|
||||
__fi void xCVTSI2SS( const xRegisterSSE& to, const xRegister32or64& from ) { OpWriteSSE( 0xf3, 0x2a ); }
|
||||
__fi void xCVTSI2SS( const xRegisterSSE& to, const xIndirect32& from ) { OpWriteSSE( 0xf3, 0x2a ); }
|
||||
|
||||
|
|
@ -178,12 +170,8 @@ __fi void xCVTSS2SI( const xRegister32or64& to, const xIndirect32& from ) { Op
|
|||
|
||||
__fi void xCVTTPD2DQ( const xRegisterSSE& to, const xRegisterSSE& from ) { OpWriteSSE( 0x66, 0xe6 ); }
|
||||
__fi void xCVTTPD2DQ( const xRegisterSSE& to, const xIndirect128& from ) { OpWriteSSE( 0x66, 0xe6 ); }
|
||||
__fi void xCVTTPD2PI( const xRegisterMMX& to, const xRegisterSSE& from ) { OpWriteSSE( 0x66, 0x2c ); }
|
||||
__fi void xCVTTPD2PI( const xRegisterMMX& to, const xIndirect128& from ) { OpWriteSSE( 0x66, 0x2c ); }
|
||||
__fi void xCVTTPS2DQ( const xRegisterSSE& to, const xRegisterSSE& from ) { OpWriteSSE( 0xf3, 0x5b ); }
|
||||
__fi void xCVTTPS2DQ( const xRegisterSSE& to, const xIndirect128& from ) { OpWriteSSE( 0xf3, 0x5b ); }
|
||||
__fi void xCVTTPS2PI( const xRegisterMMX& to, const xRegisterSSE& from ) { OpWriteSSE( 0x00, 0x2c ); }
|
||||
__fi void xCVTTPS2PI( const xRegisterMMX& to, const xIndirect64& from ) { OpWriteSSE( 0x00, 0x2c ); }
|
||||
|
||||
__fi void xCVTTSD2SI( const xRegister32or64& to, const xRegisterSSE& from ) { OpWriteSSE( 0xf2, 0x2c ); }
|
||||
__fi void xCVTTSD2SI( const xRegister32or64& to, const xIndirect64& from ) { OpWriteSSE( 0xf2, 0x2c ); }
|
||||
|
|
@ -199,14 +187,10 @@ void xImplSimd_DestRegSSE::operator()( const xRegisterSSE& to, const xIndirectVo
|
|||
void xImplSimd_DestRegImmSSE::operator()( const xRegisterSSE& to, const xRegisterSSE& from, u8 imm ) const { xOpWrite0F( Prefix, Opcode, to, from, imm ); }
|
||||
void xImplSimd_DestRegImmSSE::operator()( const xRegisterSSE& to, const xIndirectVoid& from, u8 imm ) const { xOpWrite0F( Prefix, Opcode, to, from, imm ); }
|
||||
|
||||
void xImplSimd_DestRegImmMMX::operator()( const xRegisterMMX& to, const xRegisterMMX& from, u8 imm ) const { xOpWrite0F( Opcode, to, from, imm ); }
|
||||
void xImplSimd_DestRegImmMMX::operator()( const xRegisterMMX& to, const xIndirectVoid& from, u8 imm ) const { xOpWrite0F( Opcode, to, from, imm ); }
|
||||
|
||||
void xImplSimd_DestRegEither::operator()( const xRegisterSSE& to, const xRegisterSSE& from ) const { OpWriteSSE( Prefix, Opcode ); }
|
||||
void xImplSimd_DestRegEither::operator()( const xRegisterSSE& to, const xIndirectVoid& from ) const { OpWriteSSE( Prefix, Opcode ); }
|
||||
|
||||
void xImplSimd_DestRegEither::operator()( const xRegisterMMX& to, const xRegisterMMX& from ) const { OpWriteSSE( 0x00, Opcode ); }
|
||||
void xImplSimd_DestRegEither::operator()( const xRegisterMMX& to, const xIndirectVoid& from ) const { OpWriteSSE( 0x00, Opcode ); }
|
||||
|
||||
void xImplSimd_DestSSE_CmpImm::operator()( const xRegisterSSE& to, const xRegisterSSE& from, SSE2_ComparisonType imm ) const { xOpWrite0F( Prefix, Opcode, to, from, imm ); }
|
||||
void xImplSimd_DestSSE_CmpImm::operator()( const xRegisterSSE& to, const xIndirectVoid& from, SSE2_ComparisonType imm ) const { xOpWrite0F( Prefix, Opcode, to, from, imm ); }
|
||||
|
|
@ -218,8 +202,6 @@ void xImplSimd_DestSSE_CmpImm::operator()( const xRegisterSSE& to, const xIndire
|
|||
void _SimdShiftHelper::operator()( const xRegisterSSE& to, const xRegisterSSE& from ) const { OpWriteSSE( Prefix, Opcode ); }
|
||||
void _SimdShiftHelper::operator()( const xRegisterSSE& to, const xIndirectVoid& from ) const { OpWriteSSE( Prefix, Opcode ); }
|
||||
|
||||
void _SimdShiftHelper::operator()( const xRegisterMMX& to, const xRegisterMMX& from ) const { OpWriteSSE( 0x00, Opcode ); }
|
||||
void _SimdShiftHelper::operator()( const xRegisterMMX& to, const xIndirectVoid& from ) const { OpWriteSSE( 0x00, Opcode ); }
|
||||
|
||||
void _SimdShiftHelper::operator()( const xRegisterSSE& to, u8 imm8 ) const
|
||||
{
|
||||
|
|
@ -227,12 +209,6 @@ void _SimdShiftHelper::operator()( const xRegisterSSE& to, u8 imm8 ) const
|
|||
xWrite8( imm8 );
|
||||
}
|
||||
|
||||
void _SimdShiftHelper::operator()( const xRegisterMMX& to, u8 imm8 ) const
|
||||
{
|
||||
xOpWrite0F( 0x00, OpcodeImm, (int)Modcode, to );
|
||||
xWrite8( imm8 );
|
||||
}
|
||||
|
||||
void xImplSimd_Shift::DQ( const xRegisterSSE& to, u8 imm8 ) const
|
||||
{
|
||||
xOpWrite0F( 0x66, 0x73, (int)Q.Modcode+1, to, imm8 );
|
||||
|
|
@ -495,18 +471,14 @@ void xImplSimd_InsertExtractHelper::operator()( const xRegisterSSE& to, const xI
|
|||
|
||||
void xImplSimd_PInsert::W( const xRegisterSSE& to, const xRegister32& from, u8 imm8 ) const { xOpWrite0F( 0x66, 0xc4, to, from, imm8 ); }
|
||||
void xImplSimd_PInsert::W( const xRegisterSSE& to, const xIndirectVoid& from, u8 imm8 ) const { xOpWrite0F( 0x66, 0xc4, to, from, imm8 ); }
|
||||
void xImplSimd_PInsert::W( const xRegisterMMX& to, const xRegister32& from, u8 imm8 ) const { xOpWrite0F( 0xc4, to, from, imm8 ); }
|
||||
void xImplSimd_PInsert::W( const xRegisterMMX& to, const xIndirectVoid& from, u8 imm8 ) const { xOpWrite0F( 0xc4, to, from, imm8 ); }
|
||||
|
||||
void SimdImpl_PExtract::W( const xRegister32& to, const xRegisterSSE& from, u8 imm8 ) const { xOpWrite0F( 0x66, 0xc5, to, from, imm8 ); }
|
||||
void SimdImpl_PExtract::W( const xRegister32& to, const xRegisterMMX& from, u8 imm8 ) const { xOpWrite0F( 0xc5, to, from, imm8 ); }
|
||||
void SimdImpl_PExtract::W( const xIndirectVoid& dest, const xRegisterSSE& from, u8 imm8 ) const { xOpWrite0F( 0x66, 0x153a, from, dest, imm8 ); }
|
||||
|
||||
const xImplSimd_Shuffle xSHUF = { };
|
||||
|
||||
const xImplSimd_PShuffle xPSHUF =
|
||||
{
|
||||
{ 0x00, 0x70 }, // W
|
||||
{ 0x66, 0x70 }, // D
|
||||
{ 0xf2, 0x70 }, // LW
|
||||
{ 0xf3, 0x70 }, // HW
|
||||
|
|
@ -689,16 +661,9 @@ const xImplSimd_DestRegSSE xMOVSHDUP = { 0xf3,0x16 };
|
|||
__fi void xMOVDZX( const xRegisterSSE& to, const xRegister32or64& from ) { xOpWrite0F( 0x66, 0x6e, to, from ); }
|
||||
__fi void xMOVDZX( const xRegisterSSE& to, const xIndirectVoid& src ) { xOpWrite0F( 0x66, 0x6e, to, src ); }
|
||||
|
||||
__fi void xMOVDZX( const xRegisterMMX& to, const xRegister32or64& from ) { xOpWrite0F( 0x6e, to, from ); }
|
||||
__fi void xMOVDZX( const xRegisterMMX& to, const xIndirectVoid& src ) { xOpWrite0F( 0x6e, to, src ); }
|
||||
|
||||
__fi void xMOVD( const xRegister32or64& to, const xRegisterSSE& from ) { xOpWrite0F( 0x66, 0x7e, from, to ); }
|
||||
__fi void xMOVD( const xIndirectVoid& dest, const xRegisterSSE& from ) { xOpWrite0F( 0x66, 0x7e, from, dest ); }
|
||||
|
||||
__fi void xMOVD( const xRegister32or64& to, const xRegisterMMX& from ) { xOpWrite0F( 0x7e, from, to ); }
|
||||
__fi void xMOVD( const xIndirectVoid& dest, const xRegisterMMX& from ) { xOpWrite0F( 0x7e, from, dest ); }
|
||||
|
||||
|
||||
// Moves from XMM to XMM, with the *upper 64 bits* of the destination register
|
||||
// being cleared to zero.
|
||||
__fi void xMOVQZX( const xRegisterSSE& to, const xRegisterSSE& from ) { xOpWrite0F( 0xf3, 0x7e, to, from ); }
|
||||
|
|
@ -714,23 +679,6 @@ __fi void xMOVQZX( const xRegisterSSE& to, const void* src ) { xOpWrite0F( 0xf
|
|||
// Moves lower quad of XMM to ptr64 (no bits are cleared)
|
||||
__fi void xMOVQ( const xIndirectVoid& dest, const xRegisterSSE& from ) { xOpWrite0F( 0x66, 0xd6, from, dest ); }
|
||||
|
||||
__fi void xMOVQ( const xRegisterMMX& to, const xRegisterMMX& from ) { if( to != from ) xOpWrite0F( 0x6f, to, from ); }
|
||||
__fi void xMOVQ( const xRegisterMMX& to, const xIndirectVoid& src ) { xOpWrite0F( 0x6f, to, src ); }
|
||||
__fi void xMOVQ( const xIndirectVoid& dest, const xRegisterMMX& from ) { xOpWrite0F( 0x7f, from, dest ); }
|
||||
|
||||
// This form of xMOVQ is Intel's adeptly named 'MOVQ2DQ'
|
||||
__fi void xMOVQ( const xRegisterSSE& to, const xRegisterMMX& from ) { xOpWrite0F( 0xf3, 0xd6, to, from ); }
|
||||
|
||||
// This form of xMOVQ is Intel's adeptly named 'MOVDQ2Q'
|
||||
__fi void xMOVQ( const xRegisterMMX& to, const xRegisterSSE& from )
|
||||
{
|
||||
// Manual implementation of this form of MOVQ, since its parameters are unique in a way
|
||||
// that breaks the template inference of writeXMMop();
|
||||
|
||||
SimdPrefix( 0xf2, 0xd6 );
|
||||
EmitSibMagic( to, from );
|
||||
}
|
||||
|
||||
//////////////////////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
|
||||
|
|
@ -756,8 +704,6 @@ __fi void xMOVNTDQA( const xIndirectVoid& to, const xRegisterSSE& from ) { xOpWr
|
|||
__fi void xMOVNTPD( const xIndirectVoid& to, const xRegisterSSE& from ) { xOpWrite0F( 0x66, 0x2b, from, to ); }
|
||||
__fi void xMOVNTPS( const xIndirectVoid& to, const xRegisterSSE& from ) { xOpWrite0F( 0x2b, from, to ); }
|
||||
|
||||
__fi void xMOVNTQ( const xIndirectVoid& to, const xRegisterMMX& from ) { xOpWrite0F( 0xe7, from, to ); }
|
||||
|
||||
// ------------------------------------------------------------------------
|
||||
|
||||
__fi void xMOVMSKPS( const xRegister32or64& to, const xRegisterSSE& from) { xOpWrite0F( 0x50, to, from ); }
|
||||
|
|
@ -769,7 +715,6 @@ __fi void xMOVMSKPD( const xRegister32or64& to, const xRegisterSSE& from) { xOpW
|
|||
// of the mask operand determines whether the corresponding byte in the source operand is
|
||||
// written to the corresponding byte location in memory.
|
||||
__fi void xMASKMOV( const xRegisterSSE& to, const xRegisterSSE& from ) { xOpWrite0F( 0x66, 0xf7, to, from ); }
|
||||
__fi void xMASKMOV( const xRegisterMMX& to, const xRegisterMMX& from ) { xOpWrite0F( 0xf7, to, from ); }
|
||||
|
||||
// xPMOVMSKB:
|
||||
// Creates a mask made up of the most significant bit of each byte of the source
|
||||
|
|
@ -780,14 +725,12 @@ __fi void xMASKMOV( const xRegisterMMX& to, const xRegisterMMX& from ) { xOpWri
|
|||
// 128-bit (SSE) source, the byte mask is 16-bits.
|
||||
//
|
||||
__fi void xPMOVMSKB( const xRegister32or64& to, const xRegisterSSE& from ) { xOpWrite0F( 0x66, 0xd7, to, from ); }
|
||||
__fi void xPMOVMSKB( const xRegister32or64& to, const xRegisterMMX& from ) { xOpWrite0F( 0xd7, to, from ); }
|
||||
|
||||
// [sSSE-3] Concatenates dest and source operands into an intermediate composite,
|
||||
// shifts the composite at byte granularity to the right by a constant immediate,
|
||||
// and extracts the right-aligned result into the destination.
|
||||
//
|
||||
__fi void xPALIGNR( const xRegisterSSE& to, const xRegisterSSE& from, u8 imm8 ) { xOpWrite0F( 0x66, 0x0f3a, to, from, imm8 ); }
|
||||
__fi void xPALIGNR( const xRegisterMMX& to, const xRegisterMMX& from, u8 imm8 ) { xOpWrite0F( 0x0f3a, to, from, imm8 ); }
|
||||
|
||||
|
||||
// --------------------------------------------------------------------------------------
|
||||
|
|
@ -824,11 +767,6 @@ __emitinline void xEXTRACTPS( const xIndirect32& dest, const xRegisterSSE& from,
|
|||
// Ungrouped Instructions!
|
||||
// =====================================================================================================
|
||||
|
||||
// Converts from MMX register mode to FPU register mode. The cpu enters MMX register mode
|
||||
// when ever MMX instructions are run, and if FPU instructions are run without using EMMS,
|
||||
// the FPU results will be invalid.
|
||||
__fi void xEMMS() { xWrite16( 0x770F ); }
|
||||
|
||||
|
||||
// Store Streaming SIMD Extension Control/Status to Mem32.
|
||||
__emitinline void xSTMXCSR( const xIndirect32& dest )
|
||||
|
|
|
|||
|
|
@ -116,12 +116,6 @@ const xRegisterSSE
|
|||
xmm12( 12 ), xmm13( 13 ),
|
||||
xmm14( 14 ), xmm15( 15 );
|
||||
|
||||
const xRegisterMMX
|
||||
mm0( 0 ), mm1( 1 ),
|
||||
mm2( 2 ), mm3( 3 ),
|
||||
mm4( 4 ), mm5( 5 ),
|
||||
mm6( 6 ), mm7( 7 );
|
||||
|
||||
const xAddressReg
|
||||
rax( 0 ), rbx( 3 ),
|
||||
rcx( 1 ), rdx( 2 ),
|
||||
|
|
@ -192,12 +186,6 @@ const char *const x86_regnames_sse[] =
|
|||
"xmm12", "xmm13", "xmm14", "xmm15"
|
||||
};
|
||||
|
||||
const char *const x86_regnames_mmx[] =
|
||||
{
|
||||
"mm0", "mm1", "mm2", "mm3",
|
||||
"mm4", "mm5", "mm6", "mm7"
|
||||
};
|
||||
|
||||
const char* xRegisterBase::GetName()
|
||||
{
|
||||
if( Id == xRegId_Invalid ) return "invalid";
|
||||
|
|
@ -214,8 +202,6 @@ const char* xRegisterBase::GetName()
|
|||
case 4: return x86_regnames_gpr32[ Id ];
|
||||
#ifdef __x86_64__
|
||||
case 8: return x86_regnames_gpr64[ Id ];
|
||||
#else
|
||||
case 8: return x86_regnames_mmx[ Id ];
|
||||
#endif
|
||||
case 16: return x86_regnames_sse[ Id ];
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue