diff --git a/common/include/x86emitter/implement/simd_arithmetic.h b/common/include/x86emitter/implement/simd_arithmetic.h index ec92e4ec44..fb9f44d8d2 100644 --- a/common/include/x86emitter/implement/simd_arithmetic.h +++ b/common/include/x86emitter/implement/simd_arithmetic.h @@ -30,11 +30,7 @@ struct _SimdShiftHelper void operator()( const xRegisterSSE& to, const xRegisterSSE& from ) const; void operator()( const xRegisterSSE& to, const xIndirectVoid& from ) const; - void operator()( const xRegisterMMX& to, const xRegisterMMX& from ) const; - void operator()( const xRegisterMMX& to, const xIndirectVoid& from ) const; - void operator()( const xRegisterSSE& to, u8 imm8 ) const; - void operator()( const xRegisterMMX& to, u8 imm8 ) const; }; // -------------------------------------------------------------------------------------- diff --git a/common/include/x86emitter/implement/simd_comparisons.h b/common/include/x86emitter/implement/simd_comparisons.h index 1cae06add0..d8ffd4eb7c 100644 --- a/common/include/x86emitter/implement/simd_comparisons.h +++ b/common/include/x86emitter/implement/simd_comparisons.h @@ -96,12 +96,10 @@ struct xImplSimd_PMinMax { // Compare packed unsigned byte integers in dest to src and store packed min/max // values in dest. - // Operation can be performed on either MMX or SSE operands. const xImplSimd_DestRegEither UB; // Compare packed signed word integers in dest to src and store packed min/max // values in dest. - // Operation can be performed on either MMX or SSE operands. const xImplSimd_DestRegEither SW; // [SSE-4.1] Compare packed signed byte integers in dest to src and store diff --git a/common/include/x86emitter/implement/simd_helpers.h b/common/include/x86emitter/implement/simd_helpers.h index acc5c2c082..606a500076 100644 --- a/common/include/x86emitter/implement/simd_helpers.h +++ b/common/include/x86emitter/implement/simd_helpers.h @@ -56,17 +56,8 @@ struct xImplSimd_DestSSE_CmpImm void operator()( const xRegisterSSE& to, const xIndirectVoid& from, SSE2_ComparisonType imm ) const; }; -struct xImplSimd_DestRegImmMMX -{ - u8 Prefix; - u16 Opcode; - - void operator()( const xRegisterMMX& to, const xRegisterMMX& from, u8 imm ) const; - void operator()( const xRegisterMMX& to, const xIndirectVoid& from, u8 imm ) const; -}; - // ------------------------------------------------------------------------ -// For implementing MMX/SSE operations that have reg,reg/rm forms only, +// For implementing SSE operations that have reg,reg/rm forms only, // but accept either MM or XMM destinations (most PADD/PSUB and other P arithmetic ops). // struct xImplSimd_DestRegEither @@ -76,9 +67,6 @@ struct xImplSimd_DestRegEither void operator()( const xRegisterSSE& to, const xRegisterSSE& from ) const; void operator()( const xRegisterSSE& to, const xIndirectVoid& from ) const; - - void operator()( const xRegisterMMX& to, const xRegisterMMX& from ) const; - void operator()( const xRegisterMMX& to, const xIndirectVoid& from ) const; }; } // end namespace x86Emitter diff --git a/common/include/x86emitter/implement/simd_shufflepack.h b/common/include/x86emitter/implement/simd_shufflepack.h index fd009c1f4a..47b884ab2c 100644 --- a/common/include/x86emitter/implement/simd_shufflepack.h +++ b/common/include/x86emitter/implement/simd_shufflepack.h @@ -36,10 +36,6 @@ struct xImplSimd_Shuffle // -------------------------------------------------------------------------------------- struct xImplSimd_PShuffle { - // Copies words from src and inserts them into dest at word locations selected with - // the order operand (8 bit immediate). - const xImplSimd_DestRegImmMMX W; - // Copies doublewords from src and inserts them into dest at dword locations selected // with the order operand (8 bit immediate). const xImplSimd_DestRegImmSSE D; @@ -61,7 +57,6 @@ struct xImplSimd_PShuffle // byte in dest. The value of each index is the least significant 4 bits (128-bit // operation) or 3 bits (64-bit operation) of the shuffle control byte. // - // Operands can be MMX or XMM registers. const xImplSimd_DestRegEither B; // below is my test bed for a new system, free of subclasses. Was supposed to improve intellisense @@ -70,8 +65,6 @@ struct xImplSimd_PShuffle #if 0 // Copies words from src and inserts them into dest at word locations selected with // the order operand (8 bit immediate). - void W( const xRegisterMMX& to, const xRegisterMMX& from, u8 imm ) const { xOpWrite0F( 0x70, to, from, imm ); } - void W( const xRegisterMMX& to, const xIndirectVoid& from, u8 imm ) const { xOpWrite0F( 0x70, to, from, imm ); } // Copies doublewords from src and inserts them into dest at dword locations selected // with the order operand (8 bit immediate). @@ -97,11 +90,8 @@ struct xImplSimd_PShuffle // byte in dest. The value of each index is the least significant 4 bits (128-bit // operation) or 3 bits (64-bit operation) of the shuffle control byte. // - // Operands can be MMX or XMM registers. void B( const xRegisterSSE& to, const xRegisterSSE& from ) const { OpWriteSSE( 0x66, 0x0038 ); } void B( const xRegisterSSE& to, const xIndirectVoid& from ) const { OpWriteSSE( 0x66, 0x0038 ); } - void B( const xRegisterMMX& to, const xRegisterMMX& from ) const { OpWriteSSE( 0x00, 0x0038 ); } - void B( const xRegisterMMX& to, const xIndirectVoid& from ) const { OpWriteSSE( 0x00, 0x0038 ); } #endif }; @@ -214,9 +204,6 @@ struct xImplSimd_PInsert void W( const xRegisterSSE& to, const xRegister32& from, u8 imm8 ) const; void W( const xRegisterSSE& to, const xIndirectVoid& from, u8 imm8 ) const; - void W( const xRegisterMMX& to, const xRegister32& from, u8 imm8 ) const; - void W( const xRegisterMMX& to, const xIndirectVoid& from, u8 imm8 ) const; - // [SSE-4.1] Allowed with SSE registers only (MMX regs are invalid) xImplSimd_InsertExtractHelper B; @@ -239,7 +226,6 @@ struct SimdImpl_PExtract // [SSE-4.1] Note: Indirect memory forms of this instruction are an SSE-4.1 extension! // void W( const xRegister32& to, const xRegisterSSE& from, u8 imm8 ) const; - void W( const xRegister32& to, const xRegisterMMX& from, u8 imm8 ) const; void W( const xIndirectVoid& dest, const xRegisterSSE& from, u8 imm8 ) const; // [SSE-4.1] Copies the byte element specified by imm8 from src to dest. The upper bits diff --git a/common/include/x86emitter/instructions.h b/common/include/x86emitter/instructions.h index 555c452fe2..9bd62693d9 100644 --- a/common/include/x86emitter/instructions.h +++ b/common/include/x86emitter/instructions.h @@ -339,22 +339,10 @@ namespace x86Emitter extern void xMOVDZX( const xRegisterSSE& to, const xRegister32or64& from ); extern void xMOVDZX( const xRegisterSSE& to, const xIndirectVoid& src ); - extern void xMOVDZX( const xRegisterMMX& to, const xRegister32or64& from ); - extern void xMOVDZX( const xRegisterMMX& to, const xIndirectVoid& src ); - extern void xMOVD( const xRegister32or64& to, const xRegisterSSE& from ); extern void xMOVD( const xIndirectVoid& dest, const xRegisterSSE& from ); - extern void xMOVD( const xRegister32or64& to, const xRegisterMMX& from ); - extern void xMOVD( const xIndirectVoid& dest, const xRegisterMMX& from ); - - extern void xMOVQ( const xRegisterMMX& to, const xRegisterMMX& from ); - extern void xMOVQ( const xRegisterMMX& to, const xRegisterSSE& from ); - extern void xMOVQ( const xRegisterSSE& to, const xRegisterMMX& from ); - extern void xMOVQ( const xIndirectVoid& dest, const xRegisterSSE& from ); - extern void xMOVQ( const xIndirectVoid& dest, const xRegisterMMX& from ); - extern void xMOVQ( const xRegisterMMX& to, const xIndirectVoid& src ); extern void xMOVQZX( const xRegisterSSE& to, const xIndirectVoid& src ); extern void xMOVQZX( const xRegisterSSE& to, const xRegisterSSE& from ); @@ -372,17 +360,13 @@ namespace x86Emitter extern void xMOVNTPD( const xIndirectVoid& to, const xRegisterSSE& from ); extern void xMOVNTPS( const xIndirectVoid& to, const xRegisterSSE& from ); - extern void xMOVNTQ( const xIndirectVoid& to, const xRegisterMMX& from ); extern void xMOVMSKPS( const xRegister32or64& to, const xRegisterSSE& from ); extern void xMOVMSKPD( const xRegister32or64& to, const xRegisterSSE& from ); extern void xMASKMOV( const xRegisterSSE& to, const xRegisterSSE& from ); - extern void xMASKMOV( const xRegisterMMX& to, const xRegisterMMX& from ); extern void xPMOVMSKB( const xRegister32or64& to, const xRegisterSSE& from ); - extern void xPMOVMSKB( const xRegister32or64& to, const xRegisterMMX& from ); extern void xPALIGNR( const xRegisterSSE& to, const xRegisterSSE& from, u8 imm8 ); - extern void xPALIGNR( const xRegisterMMX& to, const xRegisterMMX& from, u8 imm8 ); // ------------------------------------------------------------------------ @@ -455,29 +439,21 @@ namespace x86Emitter extern void xCVTPD2DQ( const xRegisterSSE& to, const xRegisterSSE& from ); extern void xCVTPD2DQ( const xRegisterSSE& to, const xIndirect128& from ); - extern void xCVTPD2PI( const xRegisterMMX& to, const xRegisterSSE& from ); - extern void xCVTPD2PI( const xRegisterMMX& to, const xIndirect128& from ); extern void xCVTPD2PS( const xRegisterSSE& to, const xRegisterSSE& from ); extern void xCVTPD2PS( const xRegisterSSE& to, const xIndirect128& from ); - extern void xCVTPI2PD( const xRegisterSSE& to, const xRegisterMMX& from ); extern void xCVTPI2PD( const xRegisterSSE& to, const xIndirect64& from ); - extern void xCVTPI2PS( const xRegisterSSE& to, const xRegisterMMX& from ); extern void xCVTPI2PS( const xRegisterSSE& to, const xIndirect64& from ); extern void xCVTPS2DQ( const xRegisterSSE& to, const xRegisterSSE& from ); extern void xCVTPS2DQ( const xRegisterSSE& to, const xIndirect128& from ); extern void xCVTPS2PD( const xRegisterSSE& to, const xRegisterSSE& from ); extern void xCVTPS2PD( const xRegisterSSE& to, const xIndirect64& from ); - extern void xCVTPS2PI( const xRegisterMMX& to, const xRegisterSSE& from ); - extern void xCVTPS2PI( const xRegisterMMX& to, const xIndirect64& from ); extern void xCVTSD2SI( const xRegister32or64& to, const xRegisterSSE& from ); extern void xCVTSD2SI( const xRegister32or64& to, const xIndirect64& from ); extern void xCVTSD2SS( const xRegisterSSE& to, const xRegisterSSE& from ); extern void xCVTSD2SS( const xRegisterSSE& to, const xIndirect64& from ); - extern void xCVTSI2SD( const xRegisterMMX& to, const xRegister32or64& from ); - extern void xCVTSI2SD( const xRegisterMMX& to, const xIndirect32& from ); extern void xCVTSI2SS( const xRegisterSSE& to, const xRegister32or64& from ); extern void xCVTSI2SS( const xRegisterSSE& to, const xIndirect32& from ); @@ -488,12 +464,8 @@ namespace x86Emitter extern void xCVTTPD2DQ( const xRegisterSSE& to, const xRegisterSSE& from ); extern void xCVTTPD2DQ( const xRegisterSSE& to, const xIndirect128& from ); - extern void xCVTTPD2PI( const xRegisterMMX& to, const xRegisterSSE& from ); - extern void xCVTTPD2PI( const xRegisterMMX& to, const xIndirect128& from ); extern void xCVTTPS2DQ( const xRegisterSSE& to, const xRegisterSSE& from ); extern void xCVTTPS2DQ( const xRegisterSSE& to, const xIndirect128& from ); - extern void xCVTTPS2PI( const xRegisterMMX& to, const xRegisterSSE& from ); - extern void xCVTTPS2PI( const xRegisterMMX& to, const xIndirect64& from ); extern void xCVTTSD2SI( const xRegister32or64& to, const xRegisterSSE& from ); extern void xCVTTSD2SI( const xRegister32or64& to, const xIndirect64& from ); diff --git a/common/include/x86emitter/legacy_types.h b/common/include/x86emitter/legacy_types.h index 1de549247a..6761d2af8f 100644 --- a/common/include/x86emitter/legacy_types.h +++ b/common/include/x86emitter/legacy_types.h @@ -21,5 +21,4 @@ // general types typedef int x86IntRegType; -typedef int x86MMXRegType; typedef int x86SSERegType; diff --git a/common/include/x86emitter/x86types.h b/common/include/x86emitter/x86types.h index 15245408de..cc6c8ffe68 100644 --- a/common/include/x86emitter/x86types.h +++ b/common/include/x86emitter/x86types.h @@ -18,12 +18,10 @@ #ifdef __x86_64__ static const uint iREGCNT_XMM = 16; static const uint iREGCNT_GPR = 16; -static const uint iREGCNT_MMX = 8; // FIXME: port the code and remove MMX #else // Register counts for x86/32 mode: static const uint iREGCNT_XMM = 8; static const uint iREGCNT_GPR = 8; -static const uint iREGCNT_MMX = 8; #endif enum XMMSSEType @@ -233,7 +231,7 @@ template< typename T > void xWrite( T val ); // -------------------------------------------------------------------------------------- // xRegisterBase - type-unsafe x86 register representation. // -------------------------------------------------------------------------------------- - // Unless doing some fundamental stuff, use the friendly xRegister32/16/8 and xRegisterSSE/MMX + // Unless doing some fundamental stuff, use the friendly xRegister32/16/8 and xRegisterSSE // instead, which are built using this class and provide strict register type safety when // passed into emitter instructions. // @@ -264,14 +262,13 @@ template< typename T > void xWrite( T val ); // Returns true if the register is a valid accumulator: Eax, Ax, Al, XMM0. bool IsAccumulator() const { return Id == 0; } - // IsSIMD: returns true if the register is a valid MMX or XMM register. + // IsSIMD: returns true if the register is a valid XMM register. + bool IsSIMD() const { return GetOperandSize() == 16; } + // IsWide: return true if the register is 64 bits (requires a wide op on the rex prefix) #ifdef __x86_64__ - // No MMX on 64 bits, let's directly uses GPR - bool IsSIMD() const { return GetOperandSize() == 16; } bool IsWide() const { return GetOperandSize() == 8; } #else - bool IsSIMD() const { return GetOperandSize() == 8 || GetOperandSize() == 16; } bool IsWide() const { return false; } // no 64 bits GPR #endif // return true if the register is a valid YMM register @@ -359,29 +356,10 @@ template< typename T > void xWrite( T val ); }; // -------------------------------------------------------------------------------------- - // xRegisterMMX/SSE - Represents either a 64 bit or 128 bit SIMD register + // xRegisterSSE - Represents either a 64 bit or 128 bit SIMD register // -------------------------------------------------------------------------------------- - // This register type is provided to allow legal syntax for instructions that accept either - // an XMM or MMX register as a parameter, but do not allow for a GPR. - - class xRegisterMMX : public xRegisterBase - { - typedef xRegisterBase _parent; - - public: - xRegisterMMX(): _parent() { -#ifdef __x86_64__ - pxAssert(0); // Sorry but code must be ported -#endif - } - //xRegisterMMX( const xRegisterBase& src ) : _parent( src ) {} - explicit xRegisterMMX( int regId ) : _parent( regId ) {} - - virtual uint GetOperandSize() const { return 8; } - - bool operator==( const xRegisterMMX& src ) const { return this->Id == src.Id; } - bool operator!=( const xRegisterMMX& src ) const { return this->Id != src.Id; } - }; + // This register type is provided to allow legal syntax for instructions that accept + // an XMM register as a parameter, but do not allow for a GPR. class xRegisterSSE : public xRegisterBase { @@ -473,12 +451,6 @@ template< typename T > void xWrite( T val ); return xRegister16( xRegId_Empty ); } - // FIXME remove it in x86 64 - operator xRegisterMMX() const - { - return xRegisterMMX( xRegId_Empty ); - } - operator xRegisterSSE() const { return xRegisterSSE( xRegId_Empty ); @@ -551,10 +523,6 @@ template< typename T > void xWrite( T val ); xmm8, xmm9, xmm10, xmm11, xmm12, xmm13, xmm14, xmm15; - extern const xRegisterMMX - mm0, mm1, mm2, mm3, - mm4, mm5, mm6, mm7; - extern const xAddressReg rax, rbx, rcx, rdx, rsi, rdi, rbp, rsp, @@ -943,7 +911,6 @@ template< typename T > void xWrite( T val ); typedef xDirectOrIndirect xDirectOrIndirect8; typedef xDirectOrIndirect xDirectOrIndirect16; typedef xDirectOrIndirect xDirectOrIndirect32; - typedef xDirectOrIndirect xDirectOrIndirect64; typedef xDirectOrIndirect xDirectOrIndirect128; #endif diff --git a/common/src/x86emitter/simd.cpp b/common/src/x86emitter/simd.cpp index 00af27f0f3..a15d581353 100644 --- a/common/src/x86emitter/simd.cpp +++ b/common/src/x86emitter/simd.cpp @@ -145,29 +145,21 @@ __fi void xCVTDQ2PS( const xRegisterSSE& to, const xIndirect128& from ) { OpWri __fi void xCVTPD2DQ( const xRegisterSSE& to, const xRegisterSSE& from ) { OpWriteSSE( 0xf2, 0xe6 ); } __fi void xCVTPD2DQ( const xRegisterSSE& to, const xIndirect128& from ) { OpWriteSSE( 0xf2, 0xe6 ); } -__fi void xCVTPD2PI( const xRegisterMMX& to, const xRegisterSSE& from ) { OpWriteSSE( 0x66, 0x2d ); } -__fi void xCVTPD2PI( const xRegisterMMX& to, const xIndirect128& from ) { OpWriteSSE( 0x66, 0x2d ); } __fi void xCVTPD2PS( const xRegisterSSE& to, const xRegisterSSE& from ) { OpWriteSSE( 0x66, 0x5a ); } __fi void xCVTPD2PS( const xRegisterSSE& to, const xIndirect128& from ) { OpWriteSSE( 0x66, 0x5a ); } -__fi void xCVTPI2PD( const xRegisterSSE& to, const xRegisterMMX& from ) { OpWriteSSE( 0x66, 0x2a ); } __fi void xCVTPI2PD( const xRegisterSSE& to, const xIndirect64& from ) { OpWriteSSE( 0x66, 0x2a ); } -__fi void xCVTPI2PS( const xRegisterSSE& to, const xRegisterMMX& from ) { OpWriteSSE( 0x00, 0x2a ); } __fi void xCVTPI2PS( const xRegisterSSE& to, const xIndirect64& from ) { OpWriteSSE( 0x00, 0x2a ); } __fi void xCVTPS2DQ( const xRegisterSSE& to, const xRegisterSSE& from ) { OpWriteSSE( 0x66, 0x5b ); } __fi void xCVTPS2DQ( const xRegisterSSE& to, const xIndirect128& from ) { OpWriteSSE( 0x66, 0x5b ); } __fi void xCVTPS2PD( const xRegisterSSE& to, const xRegisterSSE& from ) { OpWriteSSE( 0x00, 0x5a ); } __fi void xCVTPS2PD( const xRegisterSSE& to, const xIndirect64& from ) { OpWriteSSE( 0x00, 0x5a ); } -__fi void xCVTPS2PI( const xRegisterMMX& to, const xRegisterSSE& from ) { OpWriteSSE( 0x00, 0x2d ); } -__fi void xCVTPS2PI( const xRegisterMMX& to, const xIndirect64& from ) { OpWriteSSE( 0x00, 0x2d ); } __fi void xCVTSD2SI( const xRegister32or64& to, const xRegisterSSE& from ) { OpWriteSSE( 0xf2, 0x2d ); } __fi void xCVTSD2SI( const xRegister32or64& to, const xIndirect64& from ) { OpWriteSSE( 0xf2, 0x2d ); } __fi void xCVTSD2SS( const xRegisterSSE& to, const xRegisterSSE& from ) { OpWriteSSE( 0xf2, 0x5a ); } __fi void xCVTSD2SS( const xRegisterSSE& to, const xIndirect64& from ) { OpWriteSSE( 0xf2, 0x5a ); } -__fi void xCVTSI2SD( const xRegisterMMX& to, const xRegister32or64& from ) { OpWriteSSE( 0xf2, 0x2a ); } -__fi void xCVTSI2SD( const xRegisterMMX& to, const xIndirect32& from ) { OpWriteSSE( 0xf2, 0x2a ); } __fi void xCVTSI2SS( const xRegisterSSE& to, const xRegister32or64& from ) { OpWriteSSE( 0xf3, 0x2a ); } __fi void xCVTSI2SS( const xRegisterSSE& to, const xIndirect32& from ) { OpWriteSSE( 0xf3, 0x2a ); } @@ -178,12 +170,8 @@ __fi void xCVTSS2SI( const xRegister32or64& to, const xIndirect32& from ) { Op __fi void xCVTTPD2DQ( const xRegisterSSE& to, const xRegisterSSE& from ) { OpWriteSSE( 0x66, 0xe6 ); } __fi void xCVTTPD2DQ( const xRegisterSSE& to, const xIndirect128& from ) { OpWriteSSE( 0x66, 0xe6 ); } -__fi void xCVTTPD2PI( const xRegisterMMX& to, const xRegisterSSE& from ) { OpWriteSSE( 0x66, 0x2c ); } -__fi void xCVTTPD2PI( const xRegisterMMX& to, const xIndirect128& from ) { OpWriteSSE( 0x66, 0x2c ); } __fi void xCVTTPS2DQ( const xRegisterSSE& to, const xRegisterSSE& from ) { OpWriteSSE( 0xf3, 0x5b ); } __fi void xCVTTPS2DQ( const xRegisterSSE& to, const xIndirect128& from ) { OpWriteSSE( 0xf3, 0x5b ); } -__fi void xCVTTPS2PI( const xRegisterMMX& to, const xRegisterSSE& from ) { OpWriteSSE( 0x00, 0x2c ); } -__fi void xCVTTPS2PI( const xRegisterMMX& to, const xIndirect64& from ) { OpWriteSSE( 0x00, 0x2c ); } __fi void xCVTTSD2SI( const xRegister32or64& to, const xRegisterSSE& from ) { OpWriteSSE( 0xf2, 0x2c ); } __fi void xCVTTSD2SI( const xRegister32or64& to, const xIndirect64& from ) { OpWriteSSE( 0xf2, 0x2c ); } @@ -199,14 +187,10 @@ void xImplSimd_DestRegSSE::operator()( const xRegisterSSE& to, const xIndirectVo void xImplSimd_DestRegImmSSE::operator()( const xRegisterSSE& to, const xRegisterSSE& from, u8 imm ) const { xOpWrite0F( Prefix, Opcode, to, from, imm ); } void xImplSimd_DestRegImmSSE::operator()( const xRegisterSSE& to, const xIndirectVoid& from, u8 imm ) const { xOpWrite0F( Prefix, Opcode, to, from, imm ); } -void xImplSimd_DestRegImmMMX::operator()( const xRegisterMMX& to, const xRegisterMMX& from, u8 imm ) const { xOpWrite0F( Opcode, to, from, imm ); } -void xImplSimd_DestRegImmMMX::operator()( const xRegisterMMX& to, const xIndirectVoid& from, u8 imm ) const { xOpWrite0F( Opcode, to, from, imm ); } void xImplSimd_DestRegEither::operator()( const xRegisterSSE& to, const xRegisterSSE& from ) const { OpWriteSSE( Prefix, Opcode ); } void xImplSimd_DestRegEither::operator()( const xRegisterSSE& to, const xIndirectVoid& from ) const { OpWriteSSE( Prefix, Opcode ); } -void xImplSimd_DestRegEither::operator()( const xRegisterMMX& to, const xRegisterMMX& from ) const { OpWriteSSE( 0x00, Opcode ); } -void xImplSimd_DestRegEither::operator()( const xRegisterMMX& to, const xIndirectVoid& from ) const { OpWriteSSE( 0x00, Opcode ); } void xImplSimd_DestSSE_CmpImm::operator()( const xRegisterSSE& to, const xRegisterSSE& from, SSE2_ComparisonType imm ) const { xOpWrite0F( Prefix, Opcode, to, from, imm ); } void xImplSimd_DestSSE_CmpImm::operator()( const xRegisterSSE& to, const xIndirectVoid& from, SSE2_ComparisonType imm ) const { xOpWrite0F( Prefix, Opcode, to, from, imm ); } @@ -218,8 +202,6 @@ void xImplSimd_DestSSE_CmpImm::operator()( const xRegisterSSE& to, const xIndire void _SimdShiftHelper::operator()( const xRegisterSSE& to, const xRegisterSSE& from ) const { OpWriteSSE( Prefix, Opcode ); } void _SimdShiftHelper::operator()( const xRegisterSSE& to, const xIndirectVoid& from ) const { OpWriteSSE( Prefix, Opcode ); } -void _SimdShiftHelper::operator()( const xRegisterMMX& to, const xRegisterMMX& from ) const { OpWriteSSE( 0x00, Opcode ); } -void _SimdShiftHelper::operator()( const xRegisterMMX& to, const xIndirectVoid& from ) const { OpWriteSSE( 0x00, Opcode ); } void _SimdShiftHelper::operator()( const xRegisterSSE& to, u8 imm8 ) const { @@ -227,12 +209,6 @@ void _SimdShiftHelper::operator()( const xRegisterSSE& to, u8 imm8 ) const xWrite8( imm8 ); } -void _SimdShiftHelper::operator()( const xRegisterMMX& to, u8 imm8 ) const -{ - xOpWrite0F( 0x00, OpcodeImm, (int)Modcode, to ); - xWrite8( imm8 ); -} - void xImplSimd_Shift::DQ( const xRegisterSSE& to, u8 imm8 ) const { xOpWrite0F( 0x66, 0x73, (int)Q.Modcode+1, to, imm8 ); @@ -495,18 +471,14 @@ void xImplSimd_InsertExtractHelper::operator()( const xRegisterSSE& to, const xI void xImplSimd_PInsert::W( const xRegisterSSE& to, const xRegister32& from, u8 imm8 ) const { xOpWrite0F( 0x66, 0xc4, to, from, imm8 ); } void xImplSimd_PInsert::W( const xRegisterSSE& to, const xIndirectVoid& from, u8 imm8 ) const { xOpWrite0F( 0x66, 0xc4, to, from, imm8 ); } -void xImplSimd_PInsert::W( const xRegisterMMX& to, const xRegister32& from, u8 imm8 ) const { xOpWrite0F( 0xc4, to, from, imm8 ); } -void xImplSimd_PInsert::W( const xRegisterMMX& to, const xIndirectVoid& from, u8 imm8 ) const { xOpWrite0F( 0xc4, to, from, imm8 ); } void SimdImpl_PExtract::W( const xRegister32& to, const xRegisterSSE& from, u8 imm8 ) const { xOpWrite0F( 0x66, 0xc5, to, from, imm8 ); } -void SimdImpl_PExtract::W( const xRegister32& to, const xRegisterMMX& from, u8 imm8 ) const { xOpWrite0F( 0xc5, to, from, imm8 ); } void SimdImpl_PExtract::W( const xIndirectVoid& dest, const xRegisterSSE& from, u8 imm8 ) const { xOpWrite0F( 0x66, 0x153a, from, dest, imm8 ); } const xImplSimd_Shuffle xSHUF = { }; const xImplSimd_PShuffle xPSHUF = { - { 0x00, 0x70 }, // W { 0x66, 0x70 }, // D { 0xf2, 0x70 }, // LW { 0xf3, 0x70 }, // HW @@ -689,16 +661,9 @@ const xImplSimd_DestRegSSE xMOVSHDUP = { 0xf3,0x16 }; __fi void xMOVDZX( const xRegisterSSE& to, const xRegister32or64& from ) { xOpWrite0F( 0x66, 0x6e, to, from ); } __fi void xMOVDZX( const xRegisterSSE& to, const xIndirectVoid& src ) { xOpWrite0F( 0x66, 0x6e, to, src ); } -__fi void xMOVDZX( const xRegisterMMX& to, const xRegister32or64& from ) { xOpWrite0F( 0x6e, to, from ); } -__fi void xMOVDZX( const xRegisterMMX& to, const xIndirectVoid& src ) { xOpWrite0F( 0x6e, to, src ); } - __fi void xMOVD( const xRegister32or64& to, const xRegisterSSE& from ) { xOpWrite0F( 0x66, 0x7e, from, to ); } __fi void xMOVD( const xIndirectVoid& dest, const xRegisterSSE& from ) { xOpWrite0F( 0x66, 0x7e, from, dest ); } -__fi void xMOVD( const xRegister32or64& to, const xRegisterMMX& from ) { xOpWrite0F( 0x7e, from, to ); } -__fi void xMOVD( const xIndirectVoid& dest, const xRegisterMMX& from ) { xOpWrite0F( 0x7e, from, dest ); } - - // Moves from XMM to XMM, with the *upper 64 bits* of the destination register // being cleared to zero. __fi void xMOVQZX( const xRegisterSSE& to, const xRegisterSSE& from ) { xOpWrite0F( 0xf3, 0x7e, to, from ); } @@ -714,23 +679,6 @@ __fi void xMOVQZX( const xRegisterSSE& to, const void* src ) { xOpWrite0F( 0xf // Moves lower quad of XMM to ptr64 (no bits are cleared) __fi void xMOVQ( const xIndirectVoid& dest, const xRegisterSSE& from ) { xOpWrite0F( 0x66, 0xd6, from, dest ); } -__fi void xMOVQ( const xRegisterMMX& to, const xRegisterMMX& from ) { if( to != from ) xOpWrite0F( 0x6f, to, from ); } -__fi void xMOVQ( const xRegisterMMX& to, const xIndirectVoid& src ) { xOpWrite0F( 0x6f, to, src ); } -__fi void xMOVQ( const xIndirectVoid& dest, const xRegisterMMX& from ) { xOpWrite0F( 0x7f, from, dest ); } - -// This form of xMOVQ is Intel's adeptly named 'MOVQ2DQ' -__fi void xMOVQ( const xRegisterSSE& to, const xRegisterMMX& from ) { xOpWrite0F( 0xf3, 0xd6, to, from ); } - -// This form of xMOVQ is Intel's adeptly named 'MOVDQ2Q' -__fi void xMOVQ( const xRegisterMMX& to, const xRegisterSSE& from ) -{ - // Manual implementation of this form of MOVQ, since its parameters are unique in a way - // that breaks the template inference of writeXMMop(); - - SimdPrefix( 0xf2, 0xd6 ); - EmitSibMagic( to, from ); -} - ////////////////////////////////////////////////////////////////////////////////////////// // @@ -756,8 +704,6 @@ __fi void xMOVNTDQA( const xIndirectVoid& to, const xRegisterSSE& from ) { xOpWr __fi void xMOVNTPD( const xIndirectVoid& to, const xRegisterSSE& from ) { xOpWrite0F( 0x66, 0x2b, from, to ); } __fi void xMOVNTPS( const xIndirectVoid& to, const xRegisterSSE& from ) { xOpWrite0F( 0x2b, from, to ); } -__fi void xMOVNTQ( const xIndirectVoid& to, const xRegisterMMX& from ) { xOpWrite0F( 0xe7, from, to ); } - // ------------------------------------------------------------------------ __fi void xMOVMSKPS( const xRegister32or64& to, const xRegisterSSE& from) { xOpWrite0F( 0x50, to, from ); } @@ -769,7 +715,6 @@ __fi void xMOVMSKPD( const xRegister32or64& to, const xRegisterSSE& from) { xOpW // of the mask operand determines whether the corresponding byte in the source operand is // written to the corresponding byte location in memory. __fi void xMASKMOV( const xRegisterSSE& to, const xRegisterSSE& from ) { xOpWrite0F( 0x66, 0xf7, to, from ); } -__fi void xMASKMOV( const xRegisterMMX& to, const xRegisterMMX& from ) { xOpWrite0F( 0xf7, to, from ); } // xPMOVMSKB: // Creates a mask made up of the most significant bit of each byte of the source @@ -780,14 +725,12 @@ __fi void xMASKMOV( const xRegisterMMX& to, const xRegisterMMX& from ) { xOpWri // 128-bit (SSE) source, the byte mask is 16-bits. // __fi void xPMOVMSKB( const xRegister32or64& to, const xRegisterSSE& from ) { xOpWrite0F( 0x66, 0xd7, to, from ); } -__fi void xPMOVMSKB( const xRegister32or64& to, const xRegisterMMX& from ) { xOpWrite0F( 0xd7, to, from ); } // [sSSE-3] Concatenates dest and source operands into an intermediate composite, // shifts the composite at byte granularity to the right by a constant immediate, // and extracts the right-aligned result into the destination. // __fi void xPALIGNR( const xRegisterSSE& to, const xRegisterSSE& from, u8 imm8 ) { xOpWrite0F( 0x66, 0x0f3a, to, from, imm8 ); } -__fi void xPALIGNR( const xRegisterMMX& to, const xRegisterMMX& from, u8 imm8 ) { xOpWrite0F( 0x0f3a, to, from, imm8 ); } // -------------------------------------------------------------------------------------- @@ -824,11 +767,6 @@ __emitinline void xEXTRACTPS( const xIndirect32& dest, const xRegisterSSE& from, // Ungrouped Instructions! // ===================================================================================================== -// Converts from MMX register mode to FPU register mode. The cpu enters MMX register mode -// when ever MMX instructions are run, and if FPU instructions are run without using EMMS, -// the FPU results will be invalid. -__fi void xEMMS() { xWrite16( 0x770F ); } - // Store Streaming SIMD Extension Control/Status to Mem32. __emitinline void xSTMXCSR( const xIndirect32& dest ) diff --git a/common/src/x86emitter/x86emitter.cpp b/common/src/x86emitter/x86emitter.cpp index 4317cd585f..a281febc86 100644 --- a/common/src/x86emitter/x86emitter.cpp +++ b/common/src/x86emitter/x86emitter.cpp @@ -116,12 +116,6 @@ const xRegisterSSE xmm12( 12 ), xmm13( 13 ), xmm14( 14 ), xmm15( 15 ); -const xRegisterMMX - mm0( 0 ), mm1( 1 ), - mm2( 2 ), mm3( 3 ), - mm4( 4 ), mm5( 5 ), - mm6( 6 ), mm7( 7 ); - const xAddressReg rax( 0 ), rbx( 3 ), rcx( 1 ), rdx( 2 ), @@ -192,12 +186,6 @@ const char *const x86_regnames_sse[] = "xmm12", "xmm13", "xmm14", "xmm15" }; -const char *const x86_regnames_mmx[] = -{ - "mm0", "mm1", "mm2", "mm3", - "mm4", "mm5", "mm6", "mm7" -}; - const char* xRegisterBase::GetName() { if( Id == xRegId_Invalid ) return "invalid"; @@ -214,8 +202,6 @@ const char* xRegisterBase::GetName() case 4: return x86_regnames_gpr32[ Id ]; #ifdef __x86_64__ case 8: return x86_regnames_gpr64[ Id ]; -#else - case 8: return x86_regnames_mmx[ Id ]; #endif case 16: return x86_regnames_sse[ Id ]; }