diff --git a/pcsx2/x86/iFPU.cpp b/pcsx2/x86/iFPU.cpp
index 0d59792dc4..3b477df90a 100644
--- a/pcsx2/x86/iFPU.cpp
+++ b/pcsx2/x86/iFPU.cpp
@@ -108,6 +108,15 @@ static const __aligned16 u32 s_pos[4] = { 0x7fffffff, 0xffffffff, 0xffffffff, 0x
 // *FPU Opcodes!*
 //------------------------------------------------------------------
 
+// Those opcode are marked as special ! But I don't understand why we can't run them in the interpreter
+#ifndef FPU_RECOMPILE
+
+REC_FPUFUNC(CFC1);
+REC_FPUFUNC(CTC1);
+REC_FPUFUNC(MFC1);
+REC_FPUFUNC(MTC1);
+
+#else
 
 //------------------------------------------------------------------
 // CFC1 / CTC1
@@ -260,6 +269,7 @@ void recMTC1()
 		}
 	}
 }
+#endif
 //------------------------------------------------------------------
 
 
diff --git a/pcsx2/x86/ix86-32/iR5900LoadStore.cpp b/pcsx2/x86/ix86-32/iR5900LoadStore.cpp
index 1511de0bf3..abbdee7f37 100644
--- a/pcsx2/x86/ix86-32/iR5900LoadStore.cpp
+++ b/pcsx2/x86/ix86-32/iR5900LoadStore.cpp
@@ -500,6 +500,9 @@ void recSDR()
 
 void recLWC1()
 {
+#ifndef FPU_RECOMPILE
+	recCall(::R5900::Interpreter::OpcodeImpl::LWC1);
+#else
 	_deleteFPtoXMMreg(_Rt_, 2);
 
 	if (GPR_IS_CONST1(_Rs_))
@@ -521,12 +524,16 @@ void recLWC1()
 	xMOV(ptr32[&fpuRegs.fpr[_Rt_].UL], eax);
 
 	EE::Profiler.EmitOp(eeOpcode::LWC1);
+#endif
 }
 
-////////////////////////////////////////////////////
+//////////////////////////////////////////////////////
 
 void recSWC1()
 {
+#ifndef FPU_RECOMPILE
+	recCall(::R5900::Interpreter::OpcodeImpl::SWC1);
+#else
 	_deleteFPtoXMMreg(_Rt_, 1);
 
 	xMOV(edx, ptr32[&fpuRegs.fpr[_Rt_].UL] );
@@ -548,6 +555,7 @@ void recSWC1()
 	}
 
 	EE::Profiler.EmitOp(eeOpcode::SWC1);
+#endif
 }
 
 ////////////////////////////////////////////////////