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microVU: added support for logging complete micro programs saved to the files microVU0.txt/microVU1.txt (in the logs folder) 

note: currently the code only lists the opcodes without the operands.


git-svn-id: http://pcsx2.googlecode.com/svn/trunk@1033 96395faa-99c1-11dd-bbfe-3dabce05a288
This commit is contained in:
cottonvibes 2009-04-20 19:37:41 +00:00
parent 73e50f49ea
commit 50c4a95c06
11 changed files with 902 additions and 389 deletions
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4
pcsx2/windows/VCprojects/pcsx2_2008.vcproj
View File

@ -2509,6 +2509,10 @@
RelativePath="..\..\x86\microVU_Execute.inl"
>
</File>
<File
RelativePath="..\..\x86\microVU_Log.inl"
>
</File>
<File
RelativePath="..\..\x86\microVU_Lower.inl"
>

34
pcsx2/x86/microVU.cpp
View File

@ -28,6 +28,7 @@
PCSX2_ALIGNED16(microVU microVU0);
PCSX2_ALIGNED16(microVU microVU1);
FILE *mVUlogFile[2] = {NULL, NULL};
declareAllVariables // Declares All Global Variables :D
//------------------------------------------------------------------
@ -44,7 +45,8 @@ microVUt(void) mVUinit(VURegs* vuRegsPtr) {
mVU->progSize = (vuIndex ? 0x4000 : 0x1000) / 4;
mVU->cache = NULL;
memset(&mVU->prog, 0, sizeof(mVU->prog));
mVUlog((vuIndex) ? "microVU1: init" : "microVU0: init");
mVUprint((vuIndex) ? "microVU1: init" : "microVU0: init");
mVUsetupLog();
mVUreset<vuIndex>();
}
@ -55,7 +57,7 @@ microVUt(void) mVUreset() {
microVU* mVU = mVUx;
mVUclose<vuIndex>(); // Close
mVUlog((vuIndex) ? "microVU1: reset" : "microVU0: reset");
mVUprint((vuIndex) ? "microVU1: reset" : "microVU0: reset");
// Dynarec Cache
mVU->cache = SysMmapEx((vuIndex ? 0x1e840000 : 0x0e840000), mVU->cacheSize, 0, (vuIndex ? "Micro VU1" : "Micro VU0"));
@ -95,7 +97,7 @@ microVUt(void) mVUreset() {
microVUt(void) mVUclose() {
microVU* mVU = mVUx;
mVUlog((vuIndex) ? "microVU1: close" : "microVU0: close");
mVUprint((vuIndex) ? "microVU1: close" : "microVU0: close");
if ( mVU->cache ) { HostSys::Munmap( mVU->cache, mVU->cacheSize ); mVU->cache = NULL; }
@ -124,7 +126,8 @@ microVUt(void) mVUclear(u32 addr, u32 size) {
//------------------------------------------------------------------
// Clears program data (Sets used to 1 because calling this function implies the program will be used at least once)
__forceinline void mVUclearProg(microVU* mVU, int progIndex) {
microVUt(void) mVUclearProg(int progIndex) {
microVU* mVU = mVUx;
mVU->prog.prog[progIndex].used = 1;
mVU->prog.prog[progIndex].x86ptr = mVU->prog.prog[progIndex].x86start;
for (u32 i = 0; i < (mVU->progSize / 2); i++) {
@ -133,15 +136,19 @@ __forceinline void mVUclearProg(microVU* mVU, int progIndex) {
}
// Caches Micro Program
__forceinline void mVUcacheProg(microVU* mVU, int progIndex) {
microVUt(void) mVUcacheProg(int progIndex) {
microVU* mVU = mVUx;
memcpy_fast(mVU->prog.prog[progIndex].data, mVU->regs->Micro, mVU->microSize);
mVUdumpProg(progIndex);
}
// Finds the least used program, (if program list full clears and returns an old program; if not-full, returns free program)
__forceinline int mVUfindLeastUsedProg(microVU* mVU) {
microVUt(int) mVUfindLeastUsedProg() {
microVU* mVU = mVUx;
if (mVU->prog.total < mVU->prog.max) {
mVU->prog.total++;
mVUcacheProg(mVU, mVU->prog.total); // Cache Micro Program
mVUcacheProg<vuIndex>(mVU->prog.total); // Cache Micro Program
Console::Notice("microVU: Program Total = %d", params mVU->prog.total);
return mVU->prog.total;
}
else {
@ -153,27 +160,28 @@ __forceinline int mVUfindLeastUsedProg(microVU* mVU) {
j = i;
}
}
mVUclearProg(mVU, j); // Clear old data if overwriting old program
mVUcacheProg(mVU, j); // Cache Micro Program
mVUlog("microVU: Program Cache got Full!");
mVUclearProg<vuIndex>(j); // Clear old data if overwriting old program
mVUcacheProg<vuIndex>(j); // Cache Micro Program
Console::Notice("microVU: Program Cache got Full!");
return j;
}
}
// Searches for Cached Micro Program and sets prog.cur to it (returns 1 if program found, else returns 0)
__forceinline int mVUsearchProg(microVU* mVU) {
microVUt(int) mVUsearchProg() {
microVU* mVU = mVUx;
if (mVU->prog.cleared) { // If cleared, we need to search for new program
for (int i = 0; i <= mVU->prog.total; i++) {
//if (i == mVU->prog.cur) continue; // We can skip the current program. (ToDo: Verify that games don't clear, and send the same microprogram :/)
if (!memcmp_mmx(mVU->prog.prog[i].data, mVU->regs->Micro, mVU->microSize)) {
//if (i == mVU->prog.cur) { mVUlog("microVU: Same micro program sent!"); }
//if (i == mVU->prog.cur) { mVUprint("microVU: Same micro program sent!"); }
mVU->prog.cur = i;
mVU->prog.cleared = 0;
mVU->prog.prog[i].used++;
return 1;
}
}
mVU->prog.cur = mVUfindLeastUsedProg(mVU); // If cleared and program not found, make a new program instance
mVU->prog.cur = mVUfindLeastUsedProg<vuIndex>(); // If cleared and program not found, make a new program instance
mVU->prog.cleared = 0;
return 0;
}

21
pcsx2/x86/microVU.h
View File

@ -17,7 +17,8 @@
*/
#pragma once
//#define mVUdebug // Prints Extra Info to Console
#define mVUdebug // Prints Extra Info to Console
//#define mVUlogProg // Dumps MicroPrograms into microVU0.txt/microVU1.txt
#include "Common.h"
#include "VU.h"
#include "GS.h"
@ -48,16 +49,16 @@ public:
}
microBlock* search(microRegInfo* pState) {
if (listSize < 0) return NULL;
if (blockList[0].pState.needExactMatch) { // Needs Detailed Search (Exact Match of Pipeline State)
//if (blockList[0].pState.needExactMatch) { // Needs Detailed Search (Exact Match of Pipeline State)
for (int i = 0; i <= listSize; i++) {
if (!memcmp(pState, &blockList[i].pState, sizeof(microRegInfo))) return &blockList[i];
}
}
/*}
else { // Can do Simple Search (Only Matches the Important Pipeline Stuff)
for (int i = 0; i <= listSize; i++) {
if ((blockList[i].pState.q == pState->q) && (blockList[i].pState.p == pState->p)) { return &blockList[i]; }
}
}
}*/
return NULL;
}
};
@ -118,6 +119,9 @@ extern PCSX2_ALIGNED16(microVU microVU1);
extern void (*mVU_UPPER_OPCODE[64])( VURegs* VU, s32 info );
extern void (*mVU_LOWER_OPCODE[128])( VURegs* VU, s32 info );
// Used for logging microPrograms
extern FILE *mVUlogFile[2];
// Main Functions
microVUt(void) mVUinit(VURegs*);
microVUt(void) mVUreset();
@ -125,10 +129,10 @@ microVUt(void) mVUclose();
microVUt(void) mVUclear(u32, u32);
// Private Functions
__forceinline void mVUclearProg(microVU* mVU, int progIndex);
__forceinline int mVUfindLeastUsedProg(microVU* mVU);
__forceinline int mVUsearchProg(microVU* mVU);
__forceinline void mVUcacheProg(microVU* mVU, int progIndex);
microVUt(void) mVUclearProg(microVU* mVU, int progIndex);
microVUt(int) mVUfindLeastUsedProg(microVU* mVU);
microVUt(int) mVUsearchProg(microVU* mVU);
microVUt(void) mVUcacheProg(microVU* mVU, int progIndex);
void* __fastcall mVUexecuteVU0(u32 startPC, u32 cycles);
void* __fastcall mVUexecuteVU1(u32 startPC, u32 cycles);
@ -140,6 +144,7 @@ typedef void (*mVUrecCall)(u32, u32) __attribute__((__fastcall)); // Not sure if
// Include all the *.inl files (Needed because C++ sucks with templates and *.cpp files)
#include "microVU_Misc.inl"
#include "microVU_Log.inl"
#include "microVU_Analyze.inl"
#include "microVU_Alloc.inl"
#include "microVU_Upper.inl"

32
pcsx2/x86/microVU_Analyze.inl
View File

@ -51,7 +51,7 @@
microVUt(void) mVUanalyzeFMAC1(int Fd, int Fs, int Ft) {
microVU* mVU = mVUx;
//mVUlog("microVU: FMAC1 Opcode");
//mVUprint("microVU: FMAC1 Opcode");
mVUinfo |= _doStatus;
analyzeReg1(Fs);
analyzeReg1(Ft);
@ -64,7 +64,7 @@ microVUt(void) mVUanalyzeFMAC1(int Fd, int Fs, int Ft) {
microVUt(void) mVUanalyzeFMAC2(int Fs, int Ft) {
microVU* mVU = mVUx;
//mVUlog("microVU: FMAC2 Opcode");
//mVUprint("microVU: FMAC2 Opcode");
analyzeReg1(Fs);
analyzeReg2(Ft);
}
@ -84,7 +84,7 @@ microVUt(void) mVUanalyzeFMAC2(int Fs, int Ft) {
microVUt(void) mVUanalyzeFMAC3(int Fd, int Fs, int Ft) {
microVU* mVU = mVUx;
//mVUlog("microVU: FMAC3 Opcode");
//mVUprint("microVU: FMAC3 Opcode");
mVUinfo |= _doStatus;
analyzeReg1(Fs);
analyzeReg3(Ft);
@ -114,7 +114,7 @@ microVUt(void) mVUanalyzeFMAC4(int Fs, int Ft) {
microVUt(void) mVUanalyzeIALU1(int Id, int Is, int It) {
microVU* mVU = mVUx;
//mVUlog("microVU: IALU1 Opcode");
//mVUprint("microVU: IALU1 Opcode");
if (!Id) { mVUinfo |= _isNOP; }
analyzeVIreg1(Is);
analyzeVIreg1(It);
@ -123,7 +123,7 @@ microVUt(void) mVUanalyzeIALU1(int Id, int Is, int It) {
microVUt(void) mVUanalyzeIALU2(int Is, int It) {
microVU* mVU = mVUx;
//mVUlog("microVU: IALU2 Opcode");
//mVUprint("microVU: IALU2 Opcode");
if (!It) { mVUinfo |= _isNOP; }
analyzeVIreg1(Is);
analyzeVIreg2(It, 1);
@ -145,7 +145,7 @@ microVUt(void) mVUanalyzeIALU2(int Is, int It) {
microVUt(void) mVUanalyzeMR32(int Fs, int Ft) {
microVU* mVU = mVUx;
mVUlog("microVU: MR32 Opcode");
mVUprint("microVU: MR32 Opcode");
if (!Ft) { mVUinfo |= _isNOP; }
analyzeReg6(Fs);
analyzeReg2(Ft);
@ -171,7 +171,7 @@ microVUt(void) mVUanalyzeMR32(int Fs, int Ft) {
microVUt(void) mVUanalyzeFDIV(int Fs, int Fsf, int Ft, int Ftf, u8 xCycles) {
microVU* mVU = mVUx;
mVUlog("microVU: DIV Opcode");
mVUprint("microVU: DIV Opcode");
analyzeReg5(Fs, Fsf);
analyzeReg5(Ft, Ftf);
analyzeQreg(xCycles);
@ -183,14 +183,14 @@ microVUt(void) mVUanalyzeFDIV(int Fs, int Fsf, int Ft, int Ftf, u8 xCycles) {
microVUt(void) mVUanalyzeEFU1(int Fs, int Fsf, u8 xCycles) {
microVU* mVU = mVUx;
mVUlog("microVU: EFU Opcode");
mVUprint("microVU: EFU Opcode");
analyzeReg5(Fs, Fsf);
analyzePreg(xCycles);
}
microVUt(void) mVUanalyzeEFU2(int Fs, u8 xCycles) {
microVU* mVU = mVUx;
mVUlog("microVU: EFU Opcode");
mVUprint("microVU: EFU Opcode");
analyzeReg1(Fs);
analyzePreg(xCycles);
}
@ -201,7 +201,7 @@ microVUt(void) mVUanalyzeEFU2(int Fs, u8 xCycles) {
microVUt(void) mVUanalyzeMFP(int Ft) {
microVU* mVU = mVUx;
mVUlog("microVU: MFP Opcode");
mVUprint("microVU: MFP Opcode");
if (!Ft) { mVUinfo |= _isNOP; }
analyzeReg2(Ft);
}
@ -212,7 +212,7 @@ microVUt(void) mVUanalyzeMFP(int Ft) {
microVUt(void) mVUanalyzeLQ(int Ft, int Is, bool writeIs) {
microVU* mVU = mVUx;
//mVUlog("microVU: LQ Opcode");
//mVUprint("microVU: LQ Opcode");
analyzeVIreg1(Is);
analyzeReg2(Ft);
if (!Ft) { mVUinfo |= (writeIs && Is) ? _noWriteVF : _isNOP; }
@ -238,14 +238,14 @@ microVUt(void) mVUanalyzeSQ(int Fs, int It, bool writeIt) {
microVUt(void) mVUanalyzeR1(int Fs, int Fsf) {
microVU* mVU = mVUx;
mVUlog("microVU: R-reg Opcode");
mVUprint("microVU: R-reg Opcode");
analyzeReg5(Fs, Fsf);
analyzeRreg();
}
microVUt(void) mVUanalyzeR2(int Ft, bool canBeNOP) {
microVU* mVU = mVUx;
mVUlog("microVU: R-reg Opcode");
mVUprint("microVU: R-reg Opcode");
if (!Ft) { mVUinfo |= ((canBeNOP) ? _isNOP : _noWriteVF); }
analyzeReg2(Ft);
analyzeRreg();
@ -257,7 +257,7 @@ microVUt(void) mVUanalyzeR2(int Ft, bool canBeNOP) {
microVUt(void) mVUanalyzeSflag(int It) {
microVU* mVU = mVUx;
mVUlog("microVU: Sflag Opcode");
mVUprint("microVU: Sflag Opcode");
if (!It) { mVUinfo |= _isNOP; }
else { // Sets _isSflag at instruction that FSxxx opcode reads it's status flag from
mVUinfo |= _swapOps;
@ -273,7 +273,7 @@ microVUt(void) mVUanalyzeSflag(int It) {
microVUt(void) mVUanalyzeFSSET() {
microVU* mVU = mVUx;
mVUinfo |= _isFSSET;
mVUlog("microVU: FSSET Opcode");
mVUprint("microVU: FSSET Opcode");
// mVUinfo &= ~_doStatus;
// Note: I'm not entirely sure if the non-sticky flags
// should be taken from the current upper instruction
@ -287,7 +287,7 @@ microVUt(void) mVUanalyzeFSSET() {
microVUt(void) mVUanalyzeMflag(int Is, int It) {
microVU* mVU = mVUx;
mVUlog("microVU: Mflag Opcode");
mVUprint("microVU: Mflag Opcode");
if (!It) { mVUinfo |= _isNOP; }
else { // Need set _doMac for 4 previous Ops (need to do all 4 because stalls could change the result needed)
mVUinfo |= _swapOps;

16
pcsx2/x86/microVU_Compile.inl
View File

@ -25,7 +25,7 @@
#define branchCase(JMPcc, nJMPcc) \
mVUsetupBranch<vuIndex>(bStatus, bMac); \
mVUlog("mVUcompile branchCase"); \
mVUprint("mVUcompile branchCase"); \
CMP16ItoM((uptr)&mVU->branch, 0); \
incPC2(1); \
pBlock = mVUblocks[iPC/2]->search((microRegInfo*)&mVUregs); \
@ -142,7 +142,7 @@ microVUt(void) mVUsetFlags(int* bStatus, int* bMac) {
// Recompiles Code for Proper Flags and Q/P regs on Block Linkings
microVUt(void) mVUsetupBranch(int* bStatus, int* bMac) {
microVU* mVU = mVUx;
mVUlog("mVUsetupBranch");
mVUprint("mVUsetupBranch");
PUSH32R(gprR); // Backup gprR
MOV32RtoM((uptr)&mVU->espBackup, gprESP);
@ -268,7 +268,7 @@ microVUt(void*) __fastcall mVUcompile(u32 startPC, uptr pState) {
microVU* mVU = mVUx;
u8* thisPtr = x86Ptr;
if (startPC > ((vuIndex) ? 0x3fff : 0xfff)) { mVUlog("microVU: invalid startPC"); }
if (startPC > ((vuIndex) ? 0x3fff : 0xfff)) { mVUprint("microVU: invalid startPC"); }
startPC &= (vuIndex ? 0x3ff8 : 0xff8);
// Searches for Existing Compiled Block (if found, then returns; else, compile)
@ -336,7 +336,7 @@ microVUt(void*) __fastcall mVUcompile(u32 startPC, uptr pState) {
case 8: branchCase(JNZ32, JZ32); // IBNEQ
case 1: case 2: // B/BAL
mVUlog("mVUcompile B/BAL");
mVUprint("mVUcompile B/BAL");
incPC(-3); // Go back to branch opcode (to get branch imm addr)
mVUsetupBranch<vuIndex>(bStatus, bMac);
@ -348,7 +348,7 @@ microVUt(void*) __fastcall mVUcompile(u32 startPC, uptr pState) {
return thisPtr;
case 9: case 10: // JR/JALR
mVUlog("mVUcompile JR/JALR");
mVUprint("mVUcompile JR/JALR");
memcpy_fast(&pBlock->pStateEnd, &mVUregs, sizeof(microRegInfo));
mVUsetupBranch<vuIndex>(bStatus, bMac);
@ -364,7 +364,7 @@ microVUt(void*) __fastcall mVUcompile(u32 startPC, uptr pState) {
return thisPtr;
}
// Conditional Branches
mVUlog("mVUcompile conditional branch");
mVUprint("mVUcompile conditional branch");
if (pBlock) { // Branch non-taken has already been compiled
incPC(-3); // Go back to branch opcode (to get branch imm addr)
// Check if branch-block has already been compiled
@ -386,8 +386,8 @@ microVUt(void*) __fastcall mVUcompile(u32 startPC, uptr pState) {
return thisPtr;
}
}
mVUlog("mVUcompile ebit");
if (x == (vuIndex?(0x3fff/8):(0xfff/8))) { mVUlog("microVU: Possible infinite compiling loop!"); }
mVUprint("mVUcompile ebit");
if (x == (vuIndex?(0x3fff/8):(0xfff/8))) { mVUprint("microVU: Possible infinite compiling loop!"); }
// Do E-bit end stuff here
mVUendProgram<vuIndex>();

9
pcsx2/x86/microVU_Execute.inl
View File

@ -15,6 +15,7 @@
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
*/
#pragma once
#ifdef PCSX2_MICROVU
@ -22,7 +23,7 @@
// Dispatcher Functions
//------------------------------------------------------------------
void testFunction() { mVUlog("microVU: Entered Execution Mode"); }
void testFunction() { mVUprint("microVU: Entered Execution Mode"); }
// Generates the code for entering recompiled blocks
microVUt(void) mVUdispatcherA() {
@ -128,9 +129,9 @@ microVUt(void) mVUdispatcherB() {
microVUt(void*) __fastcall mVUexecute(u32 startPC, u32 cycles) {
microVU* mVU = mVUx;
//mVUlog("microVU%x: startPC = 0x%x, cycles = 0x%x", params vuIndex, startPC, cycles);
//mVUprint("microVU%x: startPC = 0x%x, cycles = 0x%x", params vuIndex, startPC, cycles);
mVUsearchProg(mVU); // Find and set correct program
mVUsearchProg<vuIndex>(); // Find and set correct program
mVU->cycles = cycles;
mVU->totalCycles = cycles;
@ -145,7 +146,7 @@ microVUt(void*) __fastcall mVUexecute(u32 startPC, u32 cycles) {
microVUt(void) mVUcleanUp() {
microVU* mVU = mVUx;
mVUlog("microVU: Program exited successfully!");
//mVUprint("microVU: Program exited successfully!");
mVUcurProg.x86ptr = x86Ptr;
mVUcacheCheck(x86Ptr, mVUcurProg.x86start, (uptr)(mVUcurProg.x86end - mVUcurProg.x86start));
}

91
pcsx2/x86/microVU_Log.inl Normal file
View File

@ -0,0 +1,91 @@
/* Pcsx2 - Pc Ps2 Emulator
* Copyright (C) 2009 Pcsx2-Playground Team
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
*/
#pragma once
#ifdef PCSX2_MICROVU
microVUt(void) __mVUsetupLog() {
if (!vuIndex) { if (!mVUlogFile[0]) mVUlogFile[0] = fopen(LOGS_DIR "\\microVU0.txt", "w"); }
else { if (!mVUlogFile[1]) mVUlogFile[1] = fopen(LOGS_DIR "\\microVU1.txt", "w"); }
}
// writes text directly to the microVU.txt, no newlines appended.
microVUx(void) __mVULog(const char* fmt, ...) {
char tmp[2024];
va_list list;
va_start(list, fmt);
// concatenate the log message after the prefix:
int length = vsprintf(tmp, fmt, list);
va_end(list);
if (mVUlogFile[vuIndex]) {
fputs(tmp, mVUlogFile[vuIndex]);
//fputs("\n", mVUlogFile[vuIndex]);
fflush(mVUlogFile[vuIndex]);
}
}
#define commaIf() { if (bitX[6]) { mVUlog(","); bitX[6] = 0; } }
microVUt(void) __mVUdumpProgram(int progIndex) {
microVU* mVU = mVUx;
bool bitX[7];
mVUlog("*********************\n", progIndex);
mVUlog("* Micro-Program #%02d *\n", progIndex);
mVUlog("*********************\n\n", progIndex);
for (u32 i = 0; i < mVU->progSize; i+=2) {
mVU->code = mVU->prog.prog[progIndex].data[i+1];
mVUlog("[%04x] (%08x) ", i*4, mVU->code);
bitX[0] = 0;
bitX[1] = 0;
bitX[2] = 0;
bitX[3] = 0;
bitX[4] = 0;
bitX[5] = 0;
bitX[6] = 0;
if (mVU->code & _Ibit_) {bitX[0] = 1; bitX[5] = 1;}
if (mVU->code & _Ebit_) {bitX[1] = 1; bitX[5] = 1;}
if (mVU->code & _Mbit_) {bitX[2] = 1; bitX[5] = 1;}
if (mVU->code & _Dbit_) {bitX[3] = 1; bitX[5] = 1;}
if (mVU->code & _Tbit_) {bitX[4] = 1; bitX[5] = 1;}
mVUopU<vuIndex, 2>();
if (bitX[5]) {
mVUlog(" (");
if (bitX[0]) { mVUlog("I"); bitX[6] = 1; }
if (bitX[1]) { commaIf(); mVUlog("E"); bitX[6] = 1; }
if (bitX[2]) { commaIf(); mVUlog("M"); bitX[6] = 1; }
if (bitX[3]) { commaIf(); mVUlog("D"); bitX[6] = 1; }
if (bitX[4]) { commaIf(); mVUlog("T"); }
mVUlog(")");
}
mVU->code = mVU->prog.prog[progIndex].data[i];
mVUlog("\n[%04x] (%08x) ", i*4, mVU->code);
mVUopL<vuIndex, 2>();
mVUlog("\n\n");
}
}
#endif //PCSX2_MICROVU

367
pcsx2/x86/microVU_Lower.inl
View File

File diff suppressed because it is too large Load Diff

18
pcsx2/x86/microVU_Misc.h
View File

@ -138,6 +138,10 @@ declareAllVariables
#define microVUf(aType) template<int vuIndex, int recPass> aType
#define microVUq(aType) template<int vuIndex, int recPass> __forceinline aType
#define pass1 if (recPass == 0)
#define pass2 if (recPass == 1)
#define pass3 if (recPass == 2)
#define mVUcurProg mVU->prog.prog[mVU->prog.cur]
#define mVUblocks mVU->prog.prog[mVU->prog.cur].block
#define mVUallocInfo mVU->prog.prog[mVU->prog.cur].allocInfo
@ -226,7 +230,7 @@ declareAllVariables
#define mmVI(_VIreg_) (_VIreg_ - 1)
#ifdef mVUdebug
#define mVUlog Console::Status
#define mVUprint Console::Status
#define mVUdebug1() { \
if (curI & _Ibit_) { SysPrintf("microVU: I-bit set!\n"); } \
if (curI & _Ebit_) { SysPrintf("microVU: E-bit set!\n"); } \
@ -235,10 +239,20 @@ declareAllVariables
if (curI & _Tbit_) { SysPrintf("microVU: T-bit set!\n"); } \
}
#else
#define mVUlog 0&&
#define mVUprint 0&&
#define mVUdebug1() {}
#endif
#ifdef mVUlogProg
#define mVUlog __mVULog<vuIndex>
#define mVUsetupLog __mVUsetupLog<vuIndex>
#define mVUdumpProg __mVUdumpProgram<vuIndex>
#else
#define mVUlog 0&&
#define mVUsetupLog()
#define mVUdumpProg 0&&
#endif
#define mVUcacheCheck(ptr, start, limit) { \
uptr diff = ptr - start; \
if (diff >= limit) { Console::Error("microVU Error: Program went over it's cache limit. Size = %x", params diff); } \

338
pcsx2/x86/microVU_Tables.inl
View File

@ -178,6 +178,76 @@ void (* mVULOWER_OPCODE11 [128])() = {
mVUunknown<1,1> , mVUunknown<1,1> , mVUunknown<1,1> , mVUunknown<1,1>,
mVUunknown<1,1> , mVUunknown<1,1> , mVUunknown<1,1> , mVUunknown<1,1>,
};
void (* mVULOWER_OPCODE02 [128])() = {
mVU_LQ<0,2> , mVU_SQ<0,2> , mVUunknown<0,2> , mVUunknown<0,2>,
mVU_ILW<0,2> , mVU_ISW<0,2> , mVUunknown<0,2> , mVUunknown<0,2>,
mVU_IADDIU<0,2> , mVU_ISUBIU<0,2> , mVUunknown<0,2> , mVUunknown<0,2>,
mVUunknown<0,2> , mVUunknown<0,2> , mVUunknown<0,2> , mVUunknown<0,2>,
mVU_FCEQ<0,2> , mVU_FCSET<0,2> , mVU_FCAND<0,2> , mVU_FCOR<0,2>, /* 0x10 */
mVU_FSEQ<0,2> , mVU_FSSET<0,2> , mVU_FSAND<0,2> , mVU_FSOR<0,2>,
mVU_FMEQ<0,2> , mVUunknown<0,2> , mVU_FMAND<0,2> , mVU_FMOR<0,2>,
mVU_FCGET<0,2> , mVUunknown<0,2> , mVUunknown<0,2> , mVUunknown<0,2>,
mVU_B<0,2> , mVU_BAL<0,2> , mVUunknown<0,2> , mVUunknown<0,2>, /* 0x20 */
mVU_JR<0,2> , mVU_JALR<0,2> , mVUunknown<0,2> , mVUunknown<0,2>,
mVU_IBEQ<0,2> , mVU_IBNE<0,2> , mVUunknown<0,2> , mVUunknown<0,2>,
mVU_IBLTZ<0,2> , mVU_IBGTZ<0,2> , mVU_IBLEZ<0,2> , mVU_IBGEZ<0,2>,
mVUunknown<0,2> , mVUunknown<0,2> , mVUunknown<0,2> , mVUunknown<0,2>, /* 0x30 */
mVUunknown<0,2> , mVUunknown<0,2> , mVUunknown<0,2> , mVUunknown<0,2>,
mVUunknown<0,2> , mVUunknown<0,2> , mVUunknown<0,2> , mVUunknown<0,2>,
mVUunknown<0,2> , mVUunknown<0,2> , mVUunknown<0,2> , mVUunknown<0,2>,
mVULowerOP<0,2> , mVUunknown<0,2> , mVUunknown<0,2> , mVUunknown<0,2>, /* 0x40*/
mVUunknown<0,2> , mVUunknown<0,2> , mVUunknown<0,2> , mVUunknown<0,2>,
mVUunknown<0,2> , mVUunknown<0,2> , mVUunknown<0,2> , mVUunknown<0,2>,
mVUunknown<0,2> , mVUunknown<0,2> , mVUunknown<0,2> , mVUunknown<0,2>,
mVUunknown<0,2> , mVUunknown<0,2> , mVUunknown<0,2> , mVUunknown<0,2>, /* 0x50 */
mVUunknown<0,2> , mVUunknown<0,2> , mVUunknown<0,2> , mVUunknown<0,2>,
mVUunknown<0,2> , mVUunknown<0,2> , mVUunknown<0,2> , mVUunknown<0,2>,
mVUunknown<0,2> , mVUunknown<0,2> , mVUunknown<0,2> , mVUunknown<0,2>,
mVUunknown<0,2> , mVUunknown<0,2> , mVUunknown<0,2> , mVUunknown<0,2>, /* 0x60 */
mVUunknown<0,2> , mVUunknown<0,2> , mVUunknown<0,2> , mVUunknown<0,2>,
mVUunknown<0,2> , mVUunknown<0,2> , mVUunknown<0,2> , mVUunknown<0,2>,
mVUunknown<0,2> , mVUunknown<0,2> , mVUunknown<0,2> , mVUunknown<0,2>,
mVUunknown<0,2> , mVUunknown<0,2> , mVUunknown<0,2> , mVUunknown<0,2>, /* 0x70 */
mVUunknown<0,2> , mVUunknown<0,2> , mVUunknown<0,2> , mVUunknown<0,2>,
mVUunknown<0,2> , mVUunknown<0,2> , mVUunknown<0,2> , mVUunknown<0,2>,
mVUunknown<0,2> , mVUunknown<0,2> , mVUunknown<0,2> , mVUunknown<0,2>,
};
void (* mVULOWER_OPCODE12 [128])() = {
mVU_LQ<1,2> , mVU_SQ<1,2> , mVUunknown<1,2> , mVUunknown<1,2>,
mVU_ILW<1,2> , mVU_ISW<1,2> , mVUunknown<1,2> , mVUunknown<1,2>,
mVU_IADDIU<1,2> , mVU_ISUBIU<1,2> , mVUunknown<1,2> , mVUunknown<1,2>,
mVUunknown<1,2> , mVUunknown<1,2> , mVUunknown<1,2> , mVUunknown<1,2>,
mVU_FCEQ<1,2> , mVU_FCSET<1,2> , mVU_FCAND<1,2> , mVU_FCOR<1,2>, /* 0x10 */
mVU_FSEQ<1,2> , mVU_FSSET<1,2> , mVU_FSAND<1,2> , mVU_FSOR<1,2>,
mVU_FMEQ<1,2> , mVUunknown<1,2> , mVU_FMAND<1,2> , mVU_FMOR<1,2>,
mVU_FCGET<1,2> , mVUunknown<1,2> , mVUunknown<1,2> , mVUunknown<1,2>,
mVU_B<1,2> , mVU_BAL<1,2> , mVUunknown<1,2> , mVUunknown<1,2>, /* 0x20 */
mVU_JR<1,2> , mVU_JALR<1,2> , mVUunknown<1,2> , mVUunknown<1,2>,
mVU_IBEQ<1,2> , mVU_IBNE<1,2> , mVUunknown<1,2> , mVUunknown<1,2>,
mVU_IBLTZ<1,2> , mVU_IBGTZ<1,2> , mVU_IBLEZ<1,2> , mVU_IBGEZ<1,2>,
mVUunknown<1,2> , mVUunknown<1,2> , mVUunknown<1,2> , mVUunknown<1,2>, /* 0x30 */
mVUunknown<1,2> , mVUunknown<1,2> , mVUunknown<1,2> , mVUunknown<1,2>,
mVUunknown<1,2> , mVUunknown<1,2> , mVUunknown<1,2> , mVUunknown<1,2>,
mVUunknown<1,2> , mVUunknown<1,2> , mVUunknown<1,2> , mVUunknown<1,2>,
mVULowerOP<1,2> , mVUunknown<1,2> , mVUunknown<1,2> , mVUunknown<1,2>, /* 0x40*/
mVUunknown<1,2> , mVUunknown<1,2> , mVUunknown<1,2> , mVUunknown<1,2>,
mVUunknown<1,2> , mVUunknown<1,2> , mVUunknown<1,2> , mVUunknown<1,2>,
mVUunknown<1,2> , mVUunknown<1,2> , mVUunknown<1,2> , mVUunknown<1,2>,
mVUunknown<1,2> , mVUunknown<1,2> , mVUunknown<1,2> , mVUunknown<1,2>, /* 0x50 */
mVUunknown<1,2> , mVUunknown<1,2> , mVUunknown<1,2> , mVUunknown<1,2>,
mVUunknown<1,2> , mVUunknown<1,2> , mVUunknown<1,2> , mVUunknown<1,2>,
mVUunknown<1,2> , mVUunknown<1,2> , mVUunknown<1,2> , mVUunknown<1,2>,
mVUunknown<1,2> , mVUunknown<1,2> , mVUunknown<1,2> , mVUunknown<1,2>, /* 0x60 */
mVUunknown<1,2> , mVUunknown<1,2> , mVUunknown<1,2> , mVUunknown<1,2>,
mVUunknown<1,2> , mVUunknown<1,2> , mVUunknown<1,2> , mVUunknown<1,2>,
mVUunknown<1,2> , mVUunknown<1,2> , mVUunknown<1,2> , mVUunknown<1,2>,
mVUunknown<1,2> , mVUunknown<1,2> , mVUunknown<1,2> , mVUunknown<1,2>, /* 0x70 */
mVUunknown<1,2> , mVUunknown<1,2> , mVUunknown<1,2> , mVUunknown<1,2>,
mVUunknown<1,2> , mVUunknown<1,2> , mVUunknown<1,2> , mVUunknown<1,2>,
mVUunknown<1,2> , mVUunknown<1,2> , mVUunknown<1,2> , mVUunknown<1,2>,
};
//------------------------------------------------------------------
//------------------------------------------------------------------
@ -226,6 +296,28 @@ void (* mVULowerOP_T3_00_OPCODE11 [32])() = {
mVUunknown<1,1> , mVU_MFP<1,1> , mVU_XTOP<1,1> , mVU_XGKICK<1,1>,
mVU_ESADD<1,1> , mVU_EATANxy<1,1> , mVU_ESQRT<1,1> , mVU_ESIN<1,1>,
};
void (* mVULowerOP_T3_00_OPCODE02 [32])() = {
mVUunknown<0,2> , mVUunknown<0,2> , mVUunknown<0,2> , mVUunknown<0,2>,
mVUunknown<0,2> , mVUunknown<0,2> , mVUunknown<0,2> , mVUunknown<0,2>,
mVUunknown<0,2> , mVUunknown<0,2> , mVUunknown<0,2> , mVUunknown<0,2>,
mVU_MOVE<0,2> , mVU_LQI<0,2> , mVU_DIV<0,2> , mVU_MTIR<0,2>,
mVU_RNEXT<0,2> , mVUunknown<0,2> , mVUunknown<0,2> , mVUunknown<0,2>, /* 0x10 */
mVUunknown<0,2> , mVUunknown<0,2> , mVUunknown<0,2> , mVUunknown<0,2>,
mVUunknown<0,2> , mVU_MFP<0,2> , mVU_XTOP<0,2> , mVU_XGKICK<0,2>,
mVU_ESADD<0,2> , mVU_EATANxy<0,2> , mVU_ESQRT<0,2> , mVU_ESIN<0,2>,
};
void (* mVULowerOP_T3_00_OPCODE12 [32])() = {
mVUunknown<1,2> , mVUunknown<1,2> , mVUunknown<1,2> , mVUunknown<1,2>,
mVUunknown<1,2> , mVUunknown<1,2> , mVUunknown<1,2> , mVUunknown<1,2>,
mVUunknown<1,2> , mVUunknown<1,2> , mVUunknown<1,2> , mVUunknown<1,2>,
mVU_MOVE<1,2> , mVU_LQI<1,2> , mVU_DIV<1,2> , mVU_MTIR<1,2>,
mVU_RNEXT<1,2> , mVUunknown<1,2> , mVUunknown<1,2> , mVUunknown<1,2>, /* 0x10 */
mVUunknown<1,2> , mVUunknown<1,2> , mVUunknown<1,2> , mVUunknown<1,2>,
mVUunknown<1,2> , mVU_MFP<1,2> , mVU_XTOP<1,2> , mVU_XGKICK<1,2>,
mVU_ESADD<1,2> , mVU_EATANxy<1,2> , mVU_ESQRT<1,2> , mVU_ESIN<1,2>,
};
//------------------------------------------------------------------
//------------------------------------------------------------------
@ -274,6 +366,29 @@ void (* mVULowerOP_T3_01_OPCODE11 [32])() = {
mVUunknown<1,1> , mVUunknown<1,1> , mVU_XITOP<1,1> , mVUunknown<1,1>,
mVU_ERSADD<1,1> , mVU_EATANxz<1,1> , mVU_ERSQRT<1,1> , mVU_EATAN<1,1>,
};
void (* mVULowerOP_T3_01_OPCODE02 [32])() = {
mVUunknown<0,2> , mVUunknown<0,2> , mVUunknown<0,2> , mVUunknown<0,2>,
mVUunknown<0,2> , mVUunknown<0,2> , mVUunknown<0,2> , mVUunknown<0,2>,
mVUunknown<0,2> , mVUunknown<0,2> , mVUunknown<0,2> , mVUunknown<0,2>,
mVU_MR32<0,2> , mVU_SQI<0,2> , mVU_SQRT<0,2> , mVU_MFIR<0,2>,
mVU_RGET<0,2> , mVUunknown<0,2> , mVUunknown<0,2> , mVUunknown<0,2>, /* 0x10 */
mVUunknown<0,2> , mVUunknown<0,2> , mVUunknown<0,2> , mVUunknown<0,2>,
mVUunknown<0,2> , mVUunknown<0,2> , mVU_XITOP<0,2> , mVUunknown<0,2>,
mVU_ERSADD<0,2> , mVU_EATANxz<0,2> , mVU_ERSQRT<0,2> , mVU_EATAN<0,2>,
};
void (* mVULowerOP_T3_01_OPCODE12 [32])() = {
mVUunknown<1,2> , mVUunknown<1,2> , mVUunknown<1,2> , mVUunknown<1,2>,
mVUunknown<1,2> , mVUunknown<1,2> , mVUunknown<1,2> , mVUunknown<1,2>,
mVUunknown<1,2> , mVUunknown<1,2> , mVUunknown<1,2> , mVUunknown<1,2>,
mVU_MR32<1,2> , mVU_SQI<1,2> , mVU_SQRT<1,2> , mVU_MFIR<1,2>,
mVU_RGET<1,2> , mVUunknown<1,2> , mVUunknown<1,2> , mVUunknown<1,2>, /* 0x10 */
mVUunknown<1,2> , mVUunknown<1,2> , mVUunknown<1,2> , mVUunknown<1,2>,
mVUunknown<1,2> , mVUunknown<1,2> , mVU_XITOP<1,2> , mVUunknown<1,2>,
mVU_ERSADD<1,2> , mVU_EATANxz<1,2> , mVU_ERSQRT<1,2> , mVU_EATAN<1,2>,
};
//------------------------------------------------------------------
//------------------------------------------------------------------
@ -322,6 +437,28 @@ void (* mVULowerOP_T3_10_OPCODE11 [32])() = {
mVUunknown<1,1> , mVUunknown<1,1> , mVUunknown<1,1> , mVUunknown<1,1>,
mVU_ELENG<1,1> , mVU_ESUM<1,1> , mVU_ERCPR<1,1> , mVU_EEXP<1,1>,
};
void (* mVULowerOP_T3_10_OPCODE02 [32])() = {
mVUunknown<0,2> , mVUunknown<0,2> , mVUunknown<0,2> , mVUunknown<0,2>,
mVUunknown<0,2> , mVUunknown<0,2> , mVUunknown<0,2> , mVUunknown<0,2>,
mVUunknown<0,2> , mVUunknown<0,2> , mVUunknown<0,2> , mVUunknown<0,2>,
mVUunknown<0,2> , mVU_LQD<0,2> , mVU_RSQRT<0,2> , mVU_ILWR<0,2>,
mVU_RINIT<0,2> , mVUunknown<0,2> , mVUunknown<0,2> , mVUunknown<0,2>, /* 0x10 */
mVUunknown<0,2> , mVUunknown<0,2> , mVUunknown<0,2> , mVUunknown<0,2>,
mVUunknown<0,2> , mVUunknown<0,2> , mVUunknown<0,2> , mVUunknown<0,2>,
mVU_ELENG<0,2> , mVU_ESUM<0,2> , mVU_ERCPR<0,2> , mVU_EEXP<0,2>,
};
void (* mVULowerOP_T3_10_OPCODE12 [32])() = {
mVUunknown<1,2> , mVUunknown<1,2> , mVUunknown<1,2> , mVUunknown<1,2>,
mVUunknown<1,2> , mVUunknown<1,2> , mVUunknown<1,2> , mVUunknown<1,2>,
mVUunknown<1,2> , mVUunknown<1,2> , mVUunknown<1,2> , mVUunknown<1,2>,
mVUunknown<1,2> , mVU_LQD<1,2> , mVU_RSQRT<1,2> , mVU_ILWR<1,2>,
mVU_RINIT<1,2> , mVUunknown<1,2> , mVUunknown<1,2> , mVUunknown<1,2>, /* 0x10 */
mVUunknown<1,2> , mVUunknown<1,2> , mVUunknown<1,2> , mVUunknown<1,2>,
mVUunknown<1,2> , mVUunknown<1,2> , mVUunknown<1,2> , mVUunknown<1,2>,
mVU_ELENG<1,2> , mVU_ESUM<1,2> , mVU_ERCPR<1,2> , mVU_EEXP<1,2>,
};
//------------------------------------------------------------------
//------------------------------------------------------------------
@ -370,6 +507,28 @@ void (* mVULowerOP_T3_11_OPCODE11 [32])() = {
mVUunknown<1,1> , mVUunknown<1,1> , mVUunknown<1,1> , mVUunknown<1,1>,
mVU_ERLENG<1,1> , mVUunknown<1,1> , mVU_WAITP<1,1> , mVUunknown<1,1>,
};
void (* mVULowerOP_T3_11_OPCODE02 [32])() = {
mVUunknown<0,2> , mVUunknown<0,2> , mVUunknown<0,2> , mVUunknown<0,2>,
mVUunknown<0,2> , mVUunknown<0,2> , mVUunknown<0,2> , mVUunknown<0,2>,
mVUunknown<0,2> , mVUunknown<0,2> , mVUunknown<0,2> , mVUunknown<0,2>,
mVUunknown<0,2> , mVU_SQD<0,2> , mVU_WAITQ<0,2> , mVU_ISWR<0,2>,
mVU_RXOR<0,2> , mVUunknown<0,2> , mVUunknown<0,2> , mVUunknown<0,2>, /* 0x10 */
mVUunknown<0,2> , mVUunknown<0,2> , mVUunknown<0,2> , mVUunknown<0,2>,
mVUunknown<0,2> , mVUunknown<0,2> , mVUunknown<0,2> , mVUunknown<0,2>,
mVU_ERLENG<0,2> , mVUunknown<0,2> , mVU_WAITP<0,2> , mVUunknown<0,2>,
};
void (* mVULowerOP_T3_11_OPCODE12 [32])() = {
mVUunknown<1,2> , mVUunknown<1,2> , mVUunknown<1,2> , mVUunknown<1,2>,
mVUunknown<1,2> , mVUunknown<1,2> , mVUunknown<1,2> , mVUunknown<1,2>,
mVUunknown<1,2> , mVUunknown<1,2> , mVUunknown<1,2> , mVUunknown<1,2>,
mVUunknown<1,2> , mVU_SQD<1,2> , mVU_WAITQ<1,2> , mVU_ISWR<1,2>,
mVU_RXOR<1,2> , mVUunknown<1,2> , mVUunknown<1,2> , mVUunknown<1,2>, /* 0x10 */
mVUunknown<1,2> , mVUunknown<1,2> , mVUunknown<1,2> , mVUunknown<1,2>,
mVUunknown<1,2> , mVUunknown<1,2> , mVUunknown<1,2> , mVUunknown<1,2>,
mVU_ERLENG<1,2> , mVUunknown<1,2> , mVU_WAITP<1,2> , mVUunknown<1,2>,
};
//------------------------------------------------------------------
//------------------------------------------------------------------
@ -450,6 +609,44 @@ void (* mVULowerOP_OPCODE11 [64])() = {
mVUunknown<1,1> , mVUunknown<1,1> , mVUunknown<1,1> , mVUunknown<1,1>,
mVULowerOP_T3_00<1,1>, mVULowerOP_T3_01<1,1>, mVULowerOP_T3_10<1,1>, mVULowerOP_T3_11<1,1>,
};
void (* mVULowerOP_OPCODE02 [64])() = {
mVUunknown<0,2> , mVUunknown<0,2> , mVUunknown<0,2> , mVUunknown<0,2>,
mVUunknown<0,2> , mVUunknown<0,2> , mVUunknown<0,2> , mVUunknown<0,2>,
mVUunknown<0,2> , mVUunknown<0,2> , mVUunknown<0,2> , mVUunknown<0,2>,
mVUunknown<0,2> , mVUunknown<0,2> , mVUunknown<0,2> , mVUunknown<0,2>,
mVUunknown<0,2> , mVUunknown<0,2> , mVUunknown<0,2> , mVUunknown<0,2>, /* 0x10 */
mVUunknown<0,2> , mVUunknown<0,2> , mVUunknown<0,2> , mVUunknown<0,2>,
mVUunknown<0,2> , mVUunknown<0,2> , mVUunknown<0,2> , mVUunknown<0,2>,
mVUunknown<0,2> , mVUunknown<0,2> , mVUunknown<0,2> , mVUunknown<0,2>,
mVUunknown<0,2> , mVUunknown<0,2> , mVUunknown<0,2> , mVUunknown<0,2>, /* 0x20 */
mVUunknown<0,2> , mVUunknown<0,2> , mVUunknown<0,2> , mVUunknown<0,2>,
mVUunknown<0,2> , mVUunknown<0,2> , mVUunknown<0,2> , mVUunknown<0,2>,
mVUunknown<0,2> , mVUunknown<0,2> , mVUunknown<0,2> , mVUunknown<0,2>,
mVU_IADD<0,2> , mVU_ISUB<0,2> , mVU_IADDI<0,2> , mVUunknown<0,2>, /* 0x30 */
mVU_IAND<0,2> , mVU_IOR<0,2> , mVUunknown<0,2> , mVUunknown<0,2>,
mVUunknown<0,2> , mVUunknown<0,2> , mVUunknown<0,2> , mVUunknown<0,2>,
mVULowerOP_T3_00<0,2>, mVULowerOP_T3_01<0,2>, mVULowerOP_T3_10<0,2>, mVULowerOP_T3_11<0,2>,
};
void (* mVULowerOP_OPCODE12 [64])() = {
mVUunknown<1,2> , mVUunknown<1,2> , mVUunknown<1,2> , mVUunknown<1,2>,
mVUunknown<1,2> , mVUunknown<1,2> , mVUunknown<1,2> , mVUunknown<1,2>,
mVUunknown<1,2> , mVUunknown<1,2> , mVUunknown<1,2> , mVUunknown<1,2>,
mVUunknown<1,2> , mVUunknown<1,2> , mVUunknown<1,2> , mVUunknown<1,2>,
mVUunknown<1,2> , mVUunknown<1,2> , mVUunknown<1,2> , mVUunknown<1,2>, /* 0x10 */
mVUunknown<1,2> , mVUunknown<1,2> , mVUunknown<1,2> , mVUunknown<1,2>,
mVUunknown<1,2> , mVUunknown<1,2> , mVUunknown<1,2> , mVUunknown<1,2>,
mVUunknown<1,2> , mVUunknown<1,2> , mVUunknown<1,2> , mVUunknown<1,2>,
mVUunknown<1,2> , mVUunknown<1,2> , mVUunknown<1,2> , mVUunknown<1,2>, /* 0x20 */
mVUunknown<1,2> , mVUunknown<1,2> , mVUunknown<1,2> , mVUunknown<1,2>,
mVUunknown<1,2> , mVUunknown<1,2> , mVUunknown<1,2> , mVUunknown<1,2>,
mVUunknown<1,2> , mVUunknown<1,2> , mVUunknown<1,2> , mVUunknown<1,2>,
mVU_IADD<1,2> , mVU_ISUB<1,2> , mVU_IADDI<1,2> , mVUunknown<1,2>, /* 0x30 */
mVU_IAND<1,2> , mVU_IOR<1,2> , mVUunknown<1,2> , mVUunknown<1,2>,
mVUunknown<1,2> , mVUunknown<1,2> , mVUunknown<1,2> , mVUunknown<1,2>,
mVULowerOP_T3_00<1,2>, mVULowerOP_T3_01<1,2>, mVULowerOP_T3_10<1,2>, mVULowerOP_T3_11<1,2>,
};
//------------------------------------------------------------------
//------------------------------------------------------------------
@ -530,6 +727,44 @@ void (* mVU_UPPER_OPCODE11 [64])() = {
mVUunknown<1,1> , mVUunknown<1,1> , mVUunknown<1,1> , mVUunknown<1,1>,
mVU_UPPER_FD_00<1,1>, mVU_UPPER_FD_01<1,1>, mVU_UPPER_FD_10<1,1>, mVU_UPPER_FD_11<1,1>,
};
void (* mVU_UPPER_OPCODE02 [64])() = {
mVU_ADDx<0,2> , mVU_ADDy<0,2> , mVU_ADDz<0,2> , mVU_ADDw<0,2>,
mVU_SUBx<0,2> , mVU_SUBy<0,2> , mVU_SUBz<0,2> , mVU_SUBw<0,2>,
mVU_MADDx<0,2> , mVU_MADDy<0,2> , mVU_MADDz<0,2> , mVU_MADDw<0,2>,
mVU_MSUBx<0,2> , mVU_MSUBy<0,2> , mVU_MSUBz<0,2> , mVU_MSUBw<0,2>,
mVU_MAXx<0,2> , mVU_MAXy<0,2> , mVU_MAXz<0,2> , mVU_MAXw<0,2>, /* 0x10 */
mVU_MINIx<0,2> , mVU_MINIy<0,2> , mVU_MINIz<0,2> , mVU_MINIw<0,2>,
mVU_MULx<0,2> , mVU_MULy<0,2> , mVU_MULz<0,2> , mVU_MULw<0,2>,
mVU_MULq<0,2> , mVU_MAXi<0,2> , mVU_MULi<0,2> , mVU_MINIi<0,2>,
mVU_ADDq<0,2> , mVU_MADDq<0,2> , mVU_ADDi<0,2> , mVU_MADDi<0,2>, /* 0x20 */
mVU_SUBq<0,2> , mVU_MSUBq<0,2> , mVU_SUBi<0,2> , mVU_MSUBi<0,2>,
mVU_ADD<0,2> , mVU_MADD<0,2> , mVU_MUL<0,2> , mVU_MAX<0,2>,
mVU_SUB<0,2> , mVU_MSUB<0,2> , mVU_OPMSUB<0,2> , mVU_MINI<0,2>,
mVUunknown<0,2> , mVUunknown<0,2> , mVUunknown<0,2> , mVUunknown<0,2>, /* 0x30 */
mVUunknown<0,2> , mVUunknown<0,2> , mVUunknown<0,2> , mVUunknown<0,2>,
mVUunknown<0,2> , mVUunknown<0,2> , mVUunknown<0,2> , mVUunknown<0,2>,
mVU_UPPER_FD_00<0,2>, mVU_UPPER_FD_01<0,2>, mVU_UPPER_FD_10<0,2>, mVU_UPPER_FD_11<0,2>,
};
void (* mVU_UPPER_OPCODE12 [64])() = {
mVU_ADDx<1,2> , mVU_ADDy<1,2> , mVU_ADDz<1,2> , mVU_ADDw<1,2>,
mVU_SUBx<1,2> , mVU_SUBy<1,2> , mVU_SUBz<1,2> , mVU_SUBw<1,2>,
mVU_MADDx<1,2> , mVU_MADDy<1,2> , mVU_MADDz<1,2> , mVU_MADDw<1,2>,
mVU_MSUBx<1,2> , mVU_MSUBy<1,2> , mVU_MSUBz<1,2> , mVU_MSUBw<1,2>,
mVU_MAXx<1,2> , mVU_MAXy<1,2> , mVU_MAXz<1,2> , mVU_MAXw<1,2>, /* 0x10 */
mVU_MINIx<1,2> , mVU_MINIy<1,2> , mVU_MINIz<1,2> , mVU_MINIw<1,2>,
mVU_MULx<1,2> , mVU_MULy<1,2> , mVU_MULz<1,2> , mVU_MULw<1,2>,
mVU_MULq<1,2> , mVU_MAXi<1,2> , mVU_MULi<1,2> , mVU_MINIi<1,2>,
mVU_ADDq<1,2> , mVU_MADDq<1,2> , mVU_ADDi<1,2> , mVU_MADDi<1,2>, /* 0x20 */
mVU_SUBq<1,2> , mVU_MSUBq<1,2> , mVU_SUBi<1,2> , mVU_MSUBi<1,2>,
mVU_ADD<1,2> , mVU_MADD<1,2> , mVU_MUL<1,2> , mVU_MAX<1,2>,
mVU_SUB<1,2> , mVU_MSUB<1,2> , mVU_OPMSUB<1,2> , mVU_MINI<1,2>,
mVUunknown<1,2> , mVUunknown<1,2> , mVUunknown<1,2> , mVUunknown<1,2>, /* 0x30 */
mVUunknown<1,2> , mVUunknown<1,2> , mVUunknown<1,2> , mVUunknown<1,2>,
mVUunknown<1,2> , mVUunknown<1,2> , mVUunknown<1,2> , mVUunknown<1,2>,
mVU_UPPER_FD_00<1,2>, mVU_UPPER_FD_01<1,2>, mVU_UPPER_FD_10<1,2>, mVU_UPPER_FD_11<1,2>,
};
//------------------------------------------------------------------
//------------------------------------------------------------------
@ -578,6 +813,28 @@ void (* mVU_UPPER_FD_00_TABLE11 [32])() = {
mVUunknown<1,1> , mVUunknown<1,1> , mVUunknown<1,1> , mVUunknown<1,1>,
mVUunknown<1,1> , mVUunknown<1,1> , mVUunknown<1,1> , mVUunknown<1,1>,
};
void (* mVU_UPPER_FD_00_TABLE02 [32])() = {
mVU_ADDAx<0,2> , mVU_SUBAx<0,2> , mVU_MADDAx<0,2> , mVU_MSUBAx<0,2>,
mVU_ITOF0<0,2> , mVU_FTOI0<0,2> , mVU_MULAx<0,2> , mVU_MULAq<0,2>,
mVU_ADDAq<0,2> , mVU_SUBAq<0,2> , mVU_ADDA<0,2> , mVU_SUBA<0,2>,
mVUunknown<0,2> , mVUunknown<0,2> , mVUunknown<0,2> , mVUunknown<0,2>,
mVUunknown<0,2> , mVUunknown<0,2> , mVUunknown<0,2> , mVUunknown<0,2>,
mVUunknown<0,2> , mVUunknown<0,2> , mVUunknown<0,2> , mVUunknown<0,2>,
mVUunknown<0,2> , mVUunknown<0,2> , mVUunknown<0,2> , mVUunknown<0,2>,
mVUunknown<0,2> , mVUunknown<0,2> , mVUunknown<0,2> , mVUunknown<0,2>,
};
void (* mVU_UPPER_FD_00_TABLE12 [32])() = {
mVU_ADDAx<1,2> , mVU_SUBAx<1,2> , mVU_MADDAx<1,2> , mVU_MSUBAx<1,2>,
mVU_ITOF0<1,2> , mVU_FTOI0<1,2> , mVU_MULAx<1,2> , mVU_MULAq<1,2>,
mVU_ADDAq<1,2> , mVU_SUBAq<1,2> , mVU_ADDA<1,2> , mVU_SUBA<1,2>,
mVUunknown<1,2> , mVUunknown<1,2> , mVUunknown<1,2> , mVUunknown<1,2>,
mVUunknown<1,2> , mVUunknown<1,2> , mVUunknown<1,2> , mVUunknown<1,2>,
mVUunknown<1,2> , mVUunknown<1,2> , mVUunknown<1,2> , mVUunknown<1,2>,
mVUunknown<1,2> , mVUunknown<1,2> , mVUunknown<1,2> , mVUunknown<1,2>,
mVUunknown<1,2> , mVUunknown<1,2> , mVUunknown<1,2> , mVUunknown<1,2>,
};
//------------------------------------------------------------------
//------------------------------------------------------------------
@ -626,6 +883,28 @@ void (* mVU_UPPER_FD_01_TABLE11 [32])() = {
mVUunknown<1,1> , mVUunknown<1,1> , mVUunknown<1,1> , mVUunknown<1,1>,
mVUunknown<1,1> , mVUunknown<1,1> , mVUunknown<1,1> , mVUunknown<1,1>,
};
void (* mVU_UPPER_FD_01_TABLE02 [32])() = {
mVU_ADDAy<0,2> , mVU_SUBAy<0,2> , mVU_MADDAy<0,2> , mVU_MSUBAy<0,2>,
mVU_ITOF4<0,2> , mVU_FTOI4<0,2> , mVU_MULAy<0,2> , mVU_ABS<0,2>,
mVU_MADDAq<0,2> , mVU_MSUBAq<0,2> , mVU_MADDA<0,2> , mVU_MSUBA<0,2>,
mVUunknown<0,2> , mVUunknown<0,2> , mVUunknown<0,2> , mVUunknown<0,2>,
mVUunknown<0,2> , mVUunknown<0,2> , mVUunknown<0,2> , mVUunknown<0,2>,
mVUunknown<0,2> , mVUunknown<0,2> , mVUunknown<0,2> , mVUunknown<0,2>,
mVUunknown<0,2> , mVUunknown<0,2> , mVUunknown<0,2> , mVUunknown<0,2>,
mVUunknown<0,2> , mVUunknown<0,2> , mVUunknown<0,2> , mVUunknown<0,2>,
};
void (* mVU_UPPER_FD_01_TABLE12 [32])() = {
mVU_ADDAy<1,2> , mVU_SUBAy<1,2> , mVU_MADDAy<1,2> , mVU_MSUBAy<1,2>,
mVU_ITOF4<1,2> , mVU_FTOI4<1,2> , mVU_MULAy<1,2> , mVU_ABS<1,2>,
mVU_MADDAq<1,2> , mVU_MSUBAq<1,2> , mVU_MADDA<1,2> , mVU_MSUBA<1,2>,
mVUunknown<1,2> , mVUunknown<1,2> , mVUunknown<1,2> , mVUunknown<1,2>,
mVUunknown<1,2> , mVUunknown<1,2> , mVUunknown<1,2> , mVUunknown<1,2>,
mVUunknown<1,2> , mVUunknown<1,2> , mVUunknown<1,2> , mVUunknown<1,2>,
mVUunknown<1,2> , mVUunknown<1,2> , mVUunknown<1,2> , mVUunknown<1,2>,
mVUunknown<1,2> , mVUunknown<1,2> , mVUunknown<1,2> , mVUunknown<1,2>,
};
//------------------------------------------------------------------
//------------------------------------------------------------------
@ -674,6 +953,28 @@ void (* mVU_UPPER_FD_10_TABLE11 [32])() = {
mVUunknown<1,1> , mVUunknown<1,1> , mVUunknown<1,1> , mVUunknown<1,1>,
mVUunknown<1,1> , mVUunknown<1,1> , mVUunknown<1,1> , mVUunknown<1,1>,
};
void (* mVU_UPPER_FD_10_TABLE02 [32])() = {
mVU_ADDAz<0,2> , mVU_SUBAz<0,2> , mVU_MADDAz<0,2> , mVU_MSUBAz<0,2>,
mVU_ITOF12<0,2> , mVU_FTOI12<0,2> , mVU_MULAz<0,2> , mVU_MULAi<0,2>,
mVU_ADDAi<0,2> , mVU_SUBAi<0,2> , mVU_MULA<0,2> , mVU_OPMULA<0,2>,
mVUunknown<0,2> , mVUunknown<0,2> , mVUunknown<0,2> , mVUunknown<0,2>,
mVUunknown<0,2> , mVUunknown<0,2> , mVUunknown<0,2> , mVUunknown<0,2>,
mVUunknown<0,2> , mVUunknown<0,2> , mVUunknown<0,2> , mVUunknown<0,2>,
mVUunknown<0,2> , mVUunknown<0,2> , mVUunknown<0,2> , mVUunknown<0,2>,
mVUunknown<0,2> , mVUunknown<0,2> , mVUunknown<0,2> , mVUunknown<0,2>,
};
void (* mVU_UPPER_FD_10_TABLE12 [32])() = {
mVU_ADDAz<1,2> , mVU_SUBAz<1,2> , mVU_MADDAz<1,2> , mVU_MSUBAz<1,2>,
mVU_ITOF12<1,2> , mVU_FTOI12<1,2> , mVU_MULAz<1,2> , mVU_MULAi<1,2>,
mVU_ADDAi<1,2> , mVU_SUBAi<1,2> , mVU_MULA<1,2> , mVU_OPMULA<1,2>,
mVUunknown<1,2> , mVUunknown<1,2> , mVUunknown<1,2> , mVUunknown<1,2>,
mVUunknown<1,2> , mVUunknown<1,2> , mVUunknown<1,2> , mVUunknown<1,2>,
mVUunknown<1,2> , mVUunknown<1,2> , mVUunknown<1,2> , mVUunknown<1,2>,
mVUunknown<1,2> , mVUunknown<1,2> , mVUunknown<1,2> , mVUunknown<1,2>,
mVUunknown<1,2> , mVUunknown<1,2> , mVUunknown<1,2> , mVUunknown<1,2>,
};
//------------------------------------------------------------------
//------------------------------------------------------------------
@ -722,19 +1023,45 @@ void (* mVU_UPPER_FD_11_TABLE11 [32])() = {
mVUunknown<1,1> , mVUunknown<1,1> , mVUunknown<1,1> , mVUunknown<1,1>,
mVUunknown<1,1> , mVUunknown<1,1> , mVUunknown<1,1> , mVUunknown<1,1>,
};
void (* mVU_UPPER_FD_11_TABLE02 [32])() = {
mVU_ADDAw<0,2> , mVU_SUBAw<0,2> , mVU_MADDAw<0,2> , mVU_MSUBAw<0,2>,
mVU_ITOF15<0,2> , mVU_FTOI15<0,2> , mVU_MULAw<0,2> , mVU_CLIP<0,2>,
mVU_MADDAi<0,2> , mVU_MSUBAi<0,2> , mVUunknown<0,2> , mVU_NOP<0,2>,
mVUunknown<0,2> , mVUunknown<0,2> , mVUunknown<0,2> , mVUunknown<0,2>,
mVUunknown<0,2> , mVUunknown<0,2> , mVUunknown<0,2> , mVUunknown<0,2>,
mVUunknown<0,2> , mVUunknown<0,2> , mVUunknown<0,2> , mVUunknown<0,2>,
mVUunknown<0,2> , mVUunknown<0,2> , mVUunknown<0,2> , mVUunknown<0,2>,
mVUunknown<0,2> , mVUunknown<0,2> , mVUunknown<0,2> , mVUunknown<0,2>,
};
void (* mVU_UPPER_FD_11_TABLE12 [32])() = {
mVU_ADDAw<1,2> , mVU_SUBAw<1,2> , mVU_MADDAw<1,2> , mVU_MSUBAw<1,2>,
mVU_ITOF15<1,2> , mVU_FTOI15<1,2> , mVU_MULAw<1,2> , mVU_CLIP<1,2>,
mVU_MADDAi<1,2> , mVU_MSUBAi<1,2> , mVUunknown<1,2> , mVU_NOP<1,2>,
mVUunknown<1,2> , mVUunknown<1,2> , mVUunknown<1,2> , mVUunknown<1,2>,
mVUunknown<1,2> , mVUunknown<1,2> , mVUunknown<1,2> , mVUunknown<1,2>,
mVUunknown<1,2> , mVUunknown<1,2> , mVUunknown<1,2> , mVUunknown<1,2>,
mVUunknown<1,2> , mVUunknown<1,2> , mVUunknown<1,2> , mVUunknown<1,2>,
mVUunknown<1,2> , mVUunknown<1,2> , mVUunknown<1,2> , mVUunknown<1,2>,
};
//------------------------------------------------------------------
//------------------------------------------------------------------
// Table Functions
//------------------------------------------------------------------
#define doTableStuff(tableName, args) { \
if (recPass) { \
pass1 { \
if (vuIndex) tableName##10[ args ](); \
else tableName##00[ args ](); \
} \
pass2 { \
if (vuIndex) tableName##11[ args ](); \
else tableName##01[ args ](); \
} \
else { \
if (vuIndex) tableName##10[ args ](); \
else tableName##00[ args ](); \
pass3 { \
if (vuIndex) tableName##12[ args ](); \
else tableName##02[ args ](); \
} \
}
@ -750,8 +1077,9 @@ microVUf(void) mVULowerOP_T3_11() { doTableStuff(mVULowerOP_T3_11_OPCODE, ((mVUg
microVUf(void) mVUopU() { doTableStuff(mVU_UPPER_OPCODE, (mVUgetCode & 0x3f)); } // Gets Upper Opcode
microVUf(void) mVUopL() { doTableStuff(mVULOWER_OPCODE, (mVUgetCode >> 25)); } // Gets Lower Opcode
microVUf(void) mVUunknown() {
//if (recPass) return;
SysPrintf("mVUunknown<%d,%d> : Unknown Micro VU opcode called (%x)\n", vuIndex, recPass, mVUgetCode);
//pass2 { write8(0xcc); }
pass3 { mVUlog("Unknown", mVUgetCode); }
}
#endif //PCSX2_MICROVU

361
pcsx2/x86/microVU_Upper.inl
View File

@ -79,10 +79,10 @@ microVUt(void) mVUupdateFlags(int reg, int regT1, int regT2, int xyzw, bool modX
//------------------------------------------------------------------
// FMAC1 - Normal FMAC Opcodes
#define mVU_FMAC1(operation) { \
#define mVU_FMAC1(operation, OPname) { \
microVU* mVU = mVUx; \
if (!recPass) { mVUanalyzeFMAC1<vuIndex>(_Fd_, _Fs_, _Ft_); } \
else { \
pass1 { mVUanalyzeFMAC1<vuIndex>(_Fd_, _Fs_, _Ft_); } \
pass2 { \
int Fd, Fs, Ft; \
mVUallocFMAC1a<vuIndex>(Fd, Fs, Ft); \
if (_XYZW_SS) SSE_##operation##SS_XMM_to_XMM(Fs, Ft); \
@ -90,12 +90,13 @@ microVUt(void) mVUupdateFlags(int reg, int regT1, int regT2, int xyzw, bool modX
mVUupdateFlags<vuIndex>(Fd, xmmT1, xmmT2, _X_Y_Z_W, 1); \
mVUallocFMAC1b<vuIndex>(Fd); \
} \
pass3 { mVUlog(OPname); } \
}
// FMAC3 - BC(xyzw) FMAC Opcodes
#define mVU_FMAC3(operation) { \
#define mVU_FMAC3(operation, OPname) { \
microVU* mVU = mVUx; \
if (!recPass) { mVUanalyzeFMAC3<vuIndex>(_Fd_, _Fs_, _Ft_); } \
else { \
pass1 { mVUanalyzeFMAC3<vuIndex>(_Fd_, _Fs_, _Ft_); } \
pass2 { \
int Fd, Fs, Ft; \
mVUallocFMAC3a<vuIndex>(Fd, Fs, Ft); \
if (_XYZW_SS) SSE_##operation##SS_XMM_to_XMM(Fs, Ft); \
@ -103,12 +104,13 @@ microVUt(void) mVUupdateFlags(int reg, int regT1, int regT2, int xyzw, bool modX
mVUupdateFlags<vuIndex>(Fd, xmmT1, xmmT2, _X_Y_Z_W, 1); \
mVUallocFMAC3b<vuIndex>(Fd); \
} \
pass3 { mVUlog(OPname); } \
}
// FMAC4 - FMAC Opcodes Storing Result to ACC
#define mVU_FMAC4(operation) { \
#define mVU_FMAC4(operation, OPname) { \
microVU* mVU = mVUx; \
if (!recPass) { mVUanalyzeFMAC1<vuIndex>(0, _Fs_, _Ft_); } \
else { \
pass1 { mVUanalyzeFMAC1<vuIndex>(0, _Fs_, _Ft_); } \
pass2 { \
int ACC, Fs, Ft; \
mVUallocFMAC4a<vuIndex>(ACC, Fs, Ft); \
if (_X_Y_Z_W == 8) SSE_##operation##SS_XMM_to_XMM(Fs, Ft); \
@ -116,12 +118,13 @@ microVUt(void) mVUupdateFlags(int reg, int regT1, int regT2, int xyzw, bool modX
mVUupdateFlags<vuIndex>(Fs, xmmT1, xmmT2, _X_Y_Z_W, 0); \
mVUallocFMAC4b<vuIndex>(ACC, Fs); \
} \
pass3 { mVUlog(OPname); } \
}
// FMAC5 - FMAC BC(xyzw) Opcodes Storing Result to ACC
#define mVU_FMAC5(operation) { \
#define mVU_FMAC5(operation, OPname) { \
microVU* mVU = mVUx; \
if (!recPass) { mVUanalyzeFMAC3<vuIndex>(0, _Fs_, _Ft_); } \
else { \
pass1 { mVUanalyzeFMAC3<vuIndex>(0, _Fs_, _Ft_); } \
pass2 { \
int ACC, Fs, Ft; \
mVUallocFMAC5a<vuIndex>(ACC, Fs, Ft); \
if (_X_Y_Z_W == 8) SSE_##operation##SS_XMM_to_XMM(Fs, Ft); \
@ -129,12 +132,13 @@ microVUt(void) mVUupdateFlags(int reg, int regT1, int regT2, int xyzw, bool modX
mVUupdateFlags<vuIndex>(Fs, xmmT1, xmmT2, _X_Y_Z_W, 0); \
mVUallocFMAC5b<vuIndex>(ACC, Fs); \
} \
pass3 { mVUlog(OPname); } \
}
// FMAC6 - Normal FMAC Opcodes (I Reg)
#define mVU_FMAC6(operation) { \
#define mVU_FMAC6(operation, OPname) { \
microVU* mVU = mVUx; \
if (!recPass) { mVUanalyzeFMAC1<vuIndex>(_Fd_, _Fs_, 0); } \
else { \
pass1 { mVUanalyzeFMAC1<vuIndex>(_Fd_, _Fs_, 0); } \
pass2 { \
int Fd, Fs, Ft; \
mVUallocFMAC6a<vuIndex>(Fd, Fs, Ft); \
if (_XYZW_SS) SSE_##operation##SS_XMM_to_XMM(Fs, Ft); \
@ -142,12 +146,13 @@ microVUt(void) mVUupdateFlags(int reg, int regT1, int regT2, int xyzw, bool modX
mVUupdateFlags<vuIndex>(Fd, xmmT1, xmmT2, _X_Y_Z_W, 1); \
mVUallocFMAC6b<vuIndex>(Fd); \
} \
pass3 { mVUlog(OPname); } \
}
// FMAC7 - FMAC Opcodes Storing Result to ACC (I Reg)
#define mVU_FMAC7(operation) { \
#define mVU_FMAC7(operation, OPname) { \
microVU* mVU = mVUx; \
if (!recPass) { mVUanalyzeFMAC1<vuIndex>(0, _Fs_, 0); } \
else { \
pass1 { mVUanalyzeFMAC1<vuIndex>(0, _Fs_, 0); } \
pass2 { \
int ACC, Fs, Ft; \
mVUallocFMAC7a<vuIndex>(ACC, Fs, Ft); \
if (_X_Y_Z_W == 8) SSE_##operation##SS_XMM_to_XMM(Fs, Ft); \
@ -155,12 +160,13 @@ microVUt(void) mVUupdateFlags(int reg, int regT1, int regT2, int xyzw, bool modX
mVUupdateFlags<vuIndex>(Fs, xmmT1, xmmT2, _X_Y_Z_W, 0); \
mVUallocFMAC7b<vuIndex>(ACC, Fs); \
} \
pass3 { mVUlog(OPname); } \
}
// FMAC8 - MADD FMAC Opcode Storing Result to Fd
#define mVU_FMAC8(operation) { \
#define mVU_FMAC8(operation, OPname) { \
microVU* mVU = mVUx; \
if (!recPass) { mVUanalyzeFMAC1<vuIndex>(_Fd_, _Fs_, _Ft_); } \
else { \
pass1 { mVUanalyzeFMAC1<vuIndex>(_Fd_, _Fs_, _Ft_); } \
pass2 { \
int Fd, ACC, Fs, Ft; \
mVUallocFMAC8a<vuIndex>(Fd, ACC, Fs, Ft); \
if (_X_Y_Z_W == 8) { \
@ -174,12 +180,13 @@ microVUt(void) mVUupdateFlags(int reg, int regT1, int regT2, int xyzw, bool modX
mVUupdateFlags<vuIndex>(Fd, xmmT1, xmmT2, _X_Y_Z_W, 0); \
mVUallocFMAC8b<vuIndex>(Fd); \
} \
pass3 { mVUlog(OPname); } \
}
// FMAC9 - MSUB FMAC Opcode Storing Result to Fd
#define mVU_FMAC9(operation) { \
#define mVU_FMAC9(operation, OPname) { \
microVU* mVU = mVUx; \
if (!recPass) { mVUanalyzeFMAC1<vuIndex>(_Fd_, _Fs_, _Ft_); } \
else { \
pass1 { mVUanalyzeFMAC1<vuIndex>(_Fd_, _Fs_, _Ft_); } \
pass2 { \
int Fd, ACC, Fs, Ft; \
mVUallocFMAC9a<vuIndex>(Fd, ACC, Fs, Ft); \
if (_X_Y_Z_W == 8) { \
@ -193,12 +200,13 @@ microVUt(void) mVUupdateFlags(int reg, int regT1, int regT2, int xyzw, bool modX
mVUupdateFlags<vuIndex>(Fd, Fs, xmmT2, _X_Y_Z_W, 0); \
mVUallocFMAC9b<vuIndex>(Fd); \
} \
pass3 { mVUlog(OPname); } \
}
// FMAC10 - MADD FMAC BC(xyzw) Opcode Storing Result to Fd
#define mVU_FMAC10(operation) { \
#define mVU_FMAC10(operation, OPname) { \
microVU* mVU = mVUx; \
if (!recPass) { mVUanalyzeFMAC3<vuIndex>(_Fd_, _Fs_, _Ft_); } \
else { \
pass1 { mVUanalyzeFMAC3<vuIndex>(_Fd_, _Fs_, _Ft_); } \
pass2 { \
int Fd, ACC, Fs, Ft; \
mVUallocFMAC10a<vuIndex>(Fd, ACC, Fs, Ft); \
if (_X_Y_Z_W == 8) { \
@ -212,12 +220,13 @@ microVUt(void) mVUupdateFlags(int reg, int regT1, int regT2, int xyzw, bool modX
mVUupdateFlags<vuIndex>(Fd, xmmT1, xmmT2, _X_Y_Z_W, 0); \
mVUallocFMAC10b<vuIndex>(Fd); \
} \
pass3 { mVUlog(OPname); } \
}
// FMAC11 - MSUB FMAC BC(xyzw) Opcode Storing Result to Fd
#define mVU_FMAC11(operation) { \
#define mVU_FMAC11(operation, OPname) { \
microVU* mVU = mVUx; \
if (!recPass) { mVUanalyzeFMAC3<vuIndex>(_Fd_, _Fs_, _Ft_); } \
else { \
pass1 { mVUanalyzeFMAC3<vuIndex>(_Fd_, _Fs_, _Ft_); } \
pass2 { \
int Fd, ACC, Fs, Ft; \
mVUallocFMAC11a<vuIndex>(Fd, ACC, Fs, Ft); \
if (_X_Y_Z_W == 8) { \
@ -231,12 +240,13 @@ microVUt(void) mVUupdateFlags(int reg, int regT1, int regT2, int xyzw, bool modX
mVUupdateFlags<vuIndex>(Fd, Fs, xmmT2, _X_Y_Z_W, 0); \
mVUallocFMAC11b<vuIndex>(Fd); \
} \
pass3 { mVUlog(OPname); } \
}
// FMAC12 - MADD FMAC Opcode Storing Result to Fd (I Reg)
#define mVU_FMAC12(operation) { \
#define mVU_FMAC12(operation, OPname) { \
microVU* mVU = mVUx; \
if (!recPass) { mVUanalyzeFMAC1<vuIndex>(_Fd_, _Fs_, 0); } \
else { \
pass1 { mVUanalyzeFMAC1<vuIndex>(_Fd_, _Fs_, 0); } \
pass2 { \
int Fd, ACC, Fs, Ft; \
mVUallocFMAC12a<vuIndex>(Fd, ACC, Fs, Ft); \
if (_X_Y_Z_W == 8) { \
@ -250,12 +260,13 @@ microVUt(void) mVUupdateFlags(int reg, int regT1, int regT2, int xyzw, bool modX
mVUupdateFlags<vuIndex>(Fd, xmmT1, xmmT2, _X_Y_Z_W, 0); \
mVUallocFMAC12b<vuIndex>(Fd); \
} \
pass3 { mVUlog(OPname); } \
}
// FMAC13 - MSUB FMAC Opcode Storing Result to Fd (I Reg)
#define mVU_FMAC13(operation) { \
#define mVU_FMAC13(operation, OPname) { \
microVU* mVU = mVUx; \
if (!recPass) { mVUanalyzeFMAC1<vuIndex>(_Fd_, _Fs_, 0); } \
else { \
pass1 { mVUanalyzeFMAC1<vuIndex>(_Fd_, _Fs_, 0); } \
pass2 { \
int Fd, ACC, Fs, Ft; \
mVUallocFMAC13a<vuIndex>(Fd, ACC, Fs, Ft); \
if (_X_Y_Z_W == 8) { \
@ -269,12 +280,13 @@ microVUt(void) mVUupdateFlags(int reg, int regT1, int regT2, int xyzw, bool modX
mVUupdateFlags<vuIndex>(Fd, Fs, xmmT2, _X_Y_Z_W, 0); \
mVUallocFMAC13b<vuIndex>(Fd); \
} \
pass3 { mVUlog(OPname); } \
}
// FMAC14 - MADDA/MSUBA FMAC Opcode
#define mVU_FMAC14(operation) { \
#define mVU_FMAC14(operation, OPname) { \
microVU* mVU = mVUx; \
if (!recPass) { mVUanalyzeFMAC1<vuIndex>(0, _Fs_, _Ft_); } \
else { \
pass1 { mVUanalyzeFMAC1<vuIndex>(0, _Fs_, _Ft_); } \
pass2 { \
int ACCw, ACCr, Fs, Ft; \
mVUallocFMAC14a<vuIndex>(ACCw, ACCr, Fs, Ft); \
if (_X_Y_Z_W == 8) { \
@ -288,12 +300,13 @@ microVUt(void) mVUupdateFlags(int reg, int regT1, int regT2, int xyzw, bool modX
mVUupdateFlags<vuIndex>(ACCr, Fs, xmmT2, _X_Y_Z_W, 0); \
mVUallocFMAC14b<vuIndex>(ACCw, ACCr); \
} \
pass3 { mVUlog(OPname); } \
}
// FMAC15 - MADDA/MSUBA BC(xyzw) FMAC Opcode
#define mVU_FMAC15(operation) { \
#define mVU_FMAC15(operation, OPname) { \
microVU* mVU = mVUx; \
if (!recPass) { mVUanalyzeFMAC3<vuIndex>(0, _Fs_, _Ft_); } \
else { \
pass1 { mVUanalyzeFMAC3<vuIndex>(0, _Fs_, _Ft_); } \
pass2 { \
int ACCw, ACCr, Fs, Ft; \
mVUallocFMAC15a<vuIndex>(ACCw, ACCr, Fs, Ft); \
if (_X_Y_Z_W == 8) { \
@ -307,12 +320,13 @@ microVUt(void) mVUupdateFlags(int reg, int regT1, int regT2, int xyzw, bool modX
mVUupdateFlags<vuIndex>(ACCr, Fs, xmmT2, _X_Y_Z_W, 0); \
mVUallocFMAC15b<vuIndex>(ACCw, ACCr); \
} \
pass3 { mVUlog(OPname); } \
}
// FMAC16 - MADDA/MSUBA FMAC Opcode (I Reg)
#define mVU_FMAC16(operation) { \
#define mVU_FMAC16(operation, OPname) { \
microVU* mVU = mVUx; \
if (!recPass) { mVUanalyzeFMAC1<vuIndex>(0, _Fs_, 0); } \
else { \
pass1 { mVUanalyzeFMAC1<vuIndex>(0, _Fs_, 0); } \
pass2 { \
int ACCw, ACCr, Fs, Ft; \
mVUallocFMAC16a<vuIndex>(ACCw, ACCr, Fs, Ft); \
if (_X_Y_Z_W == 8) { \
@ -326,24 +340,26 @@ microVUt(void) mVUupdateFlags(int reg, int regT1, int regT2, int xyzw, bool modX
mVUupdateFlags<vuIndex>(ACCr, Fs, xmmT2, _X_Y_Z_W, 0); \
mVUallocFMAC16b<vuIndex>(ACCw, ACCr); \
} \
pass3 { mVUlog(OPname); } \
}
// FMAC18 - OPMULA FMAC Opcode
#define mVU_FMAC18(operation) { \
#define mVU_FMAC18(operation, OPname) { \
microVU* mVU = mVUx; \
if (!recPass) { mVUanalyzeFMAC1<vuIndex>(0, _Fs_, _Ft_); } \
else { \
pass1 { mVUanalyzeFMAC1<vuIndex>(0, _Fs_, _Ft_); } \
pass2 { \
int ACC, Fs, Ft; \
mVUallocFMAC18a<vuIndex>(ACC, Fs, Ft); \
SSE_##operation##PS_XMM_to_XMM(Fs, Ft); \
mVUupdateFlags<vuIndex>(Fs, xmmT1, xmmT2, _X_Y_Z_W, 0); \
mVUallocFMAC18b<vuIndex>(ACC, Fs); \
} \
pass3 { mVUlog(OPname); } \
}
// FMAC19 - OPMULA FMAC Opcode
#define mVU_FMAC19(operation) { \
#define mVU_FMAC19(operation, OPname) { \
microVU* mVU = mVUx; \
if (!recPass) { mVUanalyzeFMAC1<vuIndex>(_Fd_, _Fs_, _Ft_); } \
else { \
pass1 { mVUanalyzeFMAC1<vuIndex>(_Fd_, _Fs_, _Ft_); } \
pass2 { \
int Fd, ACC, Fs, Ft; \
mVUallocFMAC19a<vuIndex>(Fd, ACC, Fs, Ft); \
SSE_MULPS_XMM_to_XMM(Fs, Ft); \
@ -351,12 +367,13 @@ microVUt(void) mVUupdateFlags(int reg, int regT1, int regT2, int xyzw, bool modX
mVUupdateFlags<vuIndex>(Fd, Fs, xmmT2, _X_Y_Z_W, 0); \
mVUallocFMAC19b<vuIndex>(Fd); \
} \
pass3 { mVUlog(OPname); } \
}
// FMAC22 - Normal FMAC Opcodes (Q Reg)
#define mVU_FMAC22(operation) { \
#define mVU_FMAC22(operation, OPname) { \
microVU* mVU = mVUx; \
if (!recPass) { mVUanalyzeFMAC1<vuIndex>(_Fd_, _Fs_, 0); } \
else { \
pass1 { mVUanalyzeFMAC1<vuIndex>(_Fd_, _Fs_, 0); } \
pass2 { \
int Fd, Fs, Ft; \
mVUallocFMAC22a<vuIndex>(Fd, Fs, Ft); \
if (_XYZW_SS) SSE_##operation##SS_XMM_to_XMM(Fs, Ft); \
@ -364,12 +381,13 @@ microVUt(void) mVUupdateFlags(int reg, int regT1, int regT2, int xyzw, bool modX
mVUupdateFlags<vuIndex>(Fd, xmmT1, xmmT2, _X_Y_Z_W, 1); \
mVUallocFMAC22b<vuIndex>(Fd); \
} \
pass3 { mVUlog(OPname); } \
}
// FMAC23 - FMAC Opcodes Storing Result to ACC (Q Reg)
#define mVU_FMAC23(operation) { \
#define mVU_FMAC23(operation, OPname) { \
microVU* mVU = mVUx; \
if (!recPass) { mVUanalyzeFMAC1<vuIndex>(0, _Fs_, 0); } \
else { \
pass1 { mVUanalyzeFMAC1<vuIndex>(0, _Fs_, 0); } \
pass2 { \
int ACC, Fs, Ft; \
mVUallocFMAC23a<vuIndex>(ACC, Fs, Ft); \
if (_X_Y_Z_W == 8) SSE_##operation##SS_XMM_to_XMM(Fs, Ft); \
@ -377,12 +395,13 @@ microVUt(void) mVUupdateFlags(int reg, int regT1, int regT2, int xyzw, bool modX
mVUupdateFlags<vuIndex>(Fs, xmmT1, xmmT2, _X_Y_Z_W, 0); \
mVUallocFMAC23b<vuIndex>(ACC, Fs); \
} \
pass3 { mVUlog(OPname); } \
}
// FMAC24 - MADD FMAC Opcode Storing Result to Fd (Q Reg)
#define mVU_FMAC24(operation) { \
#define mVU_FMAC24(operation, OPname) { \
microVU* mVU = mVUx; \
if (!recPass) { mVUanalyzeFMAC1<vuIndex>(_Fd_, _Fs_, 0); } \
else { \
pass1 { mVUanalyzeFMAC1<vuIndex>(_Fd_, _Fs_, 0); } \
pass2 { \
int Fd, ACC, Fs, Ft; \
mVUallocFMAC24a<vuIndex>(Fd, ACC, Fs, Ft); \
if (_X_Y_Z_W == 8) { \
@ -396,12 +415,13 @@ microVUt(void) mVUupdateFlags(int reg, int regT1, int regT2, int xyzw, bool modX
mVUupdateFlags<vuIndex>(Fd, xmmT1, xmmT2, _X_Y_Z_W, 0); \
mVUallocFMAC24b<vuIndex>(Fd); \
} \
pass3 { mVUlog(OPname); } \
}
// FMAC25 - MSUB FMAC Opcode Storing Result to Fd (Q Reg)
#define mVU_FMAC25(operation) { \
#define mVU_FMAC25(operation, OPname) { \
microVU* mVU = mVUx; \
if (!recPass) { mVUanalyzeFMAC1<vuIndex>(_Fd_, _Fs_, 0); } \
else { \
pass1 { mVUanalyzeFMAC1<vuIndex>(_Fd_, _Fs_, 0); } \
pass2 { \
int Fd, ACC, Fs, Ft; \
mVUallocFMAC25a<vuIndex>(Fd, ACC, Fs, Ft); \
if (_X_Y_Z_W == 8) { \
@ -415,12 +435,13 @@ microVUt(void) mVUupdateFlags(int reg, int regT1, int regT2, int xyzw, bool modX
mVUupdateFlags<vuIndex>(Fd, Fs, xmmT2, _X_Y_Z_W, 0); \
mVUallocFMAC25b<vuIndex>(Fd); \
} \
pass3 { mVUlog(OPname); } \
}
// FMAC26 - MADDA/MSUBA FMAC Opcode (Q Reg)
#define mVU_FMAC26(operation) { \
#define mVU_FMAC26(operation, OPname) { \
microVU* mVU = mVUx; \
if (!recPass) { mVUanalyzeFMAC1<vuIndex>(0, _Fs_, 0); } \
else { \
pass1 { mVUanalyzeFMAC1<vuIndex>(0, _Fs_, 0); } \
pass2 { \
int ACCw, ACCr, Fs, Ft; \
mVUallocFMAC26a<vuIndex>(ACCw, ACCr, Fs, Ft); \
if (_X_Y_Z_W == 8) { \
@ -434,6 +455,7 @@ microVUt(void) mVUupdateFlags(int reg, int regT1, int regT2, int xyzw, bool modX
mVUupdateFlags<vuIndex>(ACCr, Fs, xmmT2, _X_Y_Z_W, 0); \
mVUallocFMAC26b<vuIndex>(ACCw, ACCr); \
} \
pass3 { mVUlog(OPname); } \
}
//------------------------------------------------------------------
@ -442,105 +464,105 @@ microVUt(void) mVUupdateFlags(int reg, int regT1, int regT2, int xyzw, bool modX
microVUf(void) mVU_ABS() {
microVU* mVU = mVUx;
if (!recPass) { mVUanalyzeFMAC2<vuIndex>(_Fs_, _Ft_); }
else {
pass1 { mVUanalyzeFMAC2<vuIndex>(_Fs_, _Ft_); }
pass2 {
int Fs, Ft;
mVUallocFMAC2a<vuIndex>(Fs, Ft);
SSE_ANDPS_M128_to_XMM(Fs, (uptr)mVU_absclip);
mVUallocFMAC2b<vuIndex>(Ft);
}
pass3 { mVUlog("ABS"); }
}
microVUf(void) mVU_ADD() { mVU_FMAC1(ADD); mVUlog("ADD"); }
microVUf(void) mVU_ADDi() { mVU_FMAC6(ADD); mVUlog("ADDi"); }
microVUf(void) mVU_ADDq() { mVU_FMAC22(ADD); mVUlog("ADDq"); }
microVUf(void) mVU_ADDx() { mVU_FMAC3(ADD); mVUlog("ADDx"); }
microVUf(void) mVU_ADDy() { mVU_FMAC3(ADD); mVUlog("ADDy"); }
microVUf(void) mVU_ADDz() { mVU_FMAC3(ADD); mVUlog("ADDz"); }
microVUf(void) mVU_ADDw() { mVU_FMAC3(ADD); mVUlog("ADDw"); }
microVUf(void) mVU_ADDA() { mVU_FMAC4(ADD); mVUlog("ADDA"); }
microVUf(void) mVU_ADDAi() { mVU_FMAC7(ADD); mVUlog("ADDAi"); }
microVUf(void) mVU_ADDAq() { mVU_FMAC23(ADD); mVUlog("ADDAq"); }
microVUf(void) mVU_ADDAx() { mVU_FMAC5(ADD); mVUlog("ADDAx"); }
microVUf(void) mVU_ADDAy() { mVU_FMAC5(ADD); mVUlog("ADDAy"); }
microVUf(void) mVU_ADDAz() { mVU_FMAC5(ADD); mVUlog("ADDAz"); }
microVUf(void) mVU_ADDAw() { mVU_FMAC5(ADD); mVUlog("ADDAw"); }
microVUf(void) mVU_SUB() { mVU_FMAC1(SUB); mVUlog("SUB"); }
microVUf(void) mVU_SUBi() { mVU_FMAC6(SUB); mVUlog("SUBi"); }
microVUf(void) mVU_SUBq() { mVU_FMAC22(SUB); mVUlog("SUBq"); }
microVUf(void) mVU_SUBx() { mVU_FMAC3(SUB); mVUlog("SUBx"); }
microVUf(void) mVU_SUBy() { mVU_FMAC3(SUB); mVUlog("SUBy"); }
microVUf(void) mVU_SUBz() { mVU_FMAC3(SUB); mVUlog("SUBz"); }
microVUf(void) mVU_SUBw() { mVU_FMAC3(SUB); mVUlog("SUBw"); }
microVUf(void) mVU_SUBA() { mVU_FMAC4(SUB); mVUlog("SUBA"); }
microVUf(void) mVU_SUBAi() { mVU_FMAC7(SUB); mVUlog("SUBAi"); }
microVUf(void) mVU_SUBAq() { mVU_FMAC23(SUB); mVUlog("SUBAq"); }
microVUf(void) mVU_SUBAx() { mVU_FMAC5(SUB); mVUlog("SUBAx"); }
microVUf(void) mVU_SUBAy() { mVU_FMAC5(SUB); mVUlog("SUBAy"); }
microVUf(void) mVU_SUBAz() { mVU_FMAC5(SUB); mVUlog("SUBAz"); }
microVUf(void) mVU_SUBAw() { mVU_FMAC5(SUB); mVUlog("SUBAw"); }
microVUf(void) mVU_MUL() { mVU_FMAC1(MUL); mVUlog("MUL"); }
microVUf(void) mVU_MULi() { mVU_FMAC6(MUL); mVUlog("MULi"); }
microVUf(void) mVU_MULq() { mVU_FMAC22(MUL); mVUlog("MULq"); }
microVUf(void) mVU_MULx() { mVU_FMAC3(MUL); mVUlog("MULx"); }
microVUf(void) mVU_MULy() { mVU_FMAC3(MUL); mVUlog("MULy"); }
microVUf(void) mVU_MULz() { mVU_FMAC3(MUL); mVUlog("MULz"); }
microVUf(void) mVU_MULw() { mVU_FMAC3(MUL); mVUlog("MULw"); }
microVUf(void) mVU_MULA() { mVU_FMAC4(MUL); mVUlog("MULA"); }
microVUf(void) mVU_MULAi() { mVU_FMAC7(MUL); mVUlog("MULAi"); }
microVUf(void) mVU_MULAq() { mVU_FMAC23(MUL); mVUlog("MULAq"); }
microVUf(void) mVU_MULAx() { mVU_FMAC5(MUL); mVUlog("MULAx"); }
microVUf(void) mVU_MULAy() { mVU_FMAC5(MUL); mVUlog("MULAy"); }
microVUf(void) mVU_MULAz() { mVU_FMAC5(MUL); mVUlog("MULAz"); }
microVUf(void) mVU_MULAw() { mVU_FMAC5(MUL); mVUlog("MULAw"); }
microVUf(void) mVU_MADD() { mVU_FMAC8(ADD); mVUlog("MADD"); }
microVUf(void) mVU_MADDi() { mVU_FMAC12(ADD); mVUlog("MADDi"); }
microVUf(void) mVU_MADDq() { mVU_FMAC24(ADD); mVUlog("MADDq"); }
microVUf(void) mVU_MADDx() { mVU_FMAC10(ADD); mVUlog("MADDx"); }
microVUf(void) mVU_MADDy() { mVU_FMAC10(ADD); mVUlog("MADDy"); }
microVUf(void) mVU_MADDz() { mVU_FMAC10(ADD); mVUlog("MADDz"); }
microVUf(void) mVU_MADDw() { mVU_FMAC10(ADD); mVUlog("MADDw"); }
microVUf(void) mVU_MADDA() { mVU_FMAC14(ADD); mVUlog("MADDA"); }
microVUf(void) mVU_MADDAi() { mVU_FMAC16(ADD); mVUlog("MADDAi"); }
microVUf(void) mVU_MADDAq() { mVU_FMAC26(ADD); mVUlog("MADDAq"); }
microVUf(void) mVU_MADDAx() { mVU_FMAC15(ADD); mVUlog("MADDAx"); }
microVUf(void) mVU_MADDAy() { mVU_FMAC15(ADD); mVUlog("MADDAy"); }
microVUf(void) mVU_MADDAz() { mVU_FMAC15(ADD); mVUlog("MADDAz"); }
microVUf(void) mVU_MADDAw() { mVU_FMAC15(ADD); mVUlog("MADDAw"); }
microVUf(void) mVU_MSUB() { mVU_FMAC9(SUB); mVUlog("MSUB"); }
microVUf(void) mVU_MSUBi() { mVU_FMAC13(SUB); mVUlog("MSUBi"); }
microVUf(void) mVU_MSUBq() { mVU_FMAC25(SUB); mVUlog("MSUBq"); }
microVUf(void) mVU_MSUBx() { mVU_FMAC11(SUB); mVUlog("MSUBx"); }
microVUf(void) mVU_MSUBy() { mVU_FMAC11(SUB); mVUlog("MSUBy"); }
microVUf(void) mVU_MSUBz() { mVU_FMAC11(SUB); mVUlog("MSUBz"); }
microVUf(void) mVU_MSUBw() { mVU_FMAC11(SUB); mVUlog("MSUBw"); }
microVUf(void) mVU_MSUBA() { mVU_FMAC14(SUB); mVUlog("MSUBA"); }
microVUf(void) mVU_MSUBAi() { mVU_FMAC16(SUB); mVUlog("MSUBAi"); }
microVUf(void) mVU_MSUBAq() { mVU_FMAC26(SUB); mVUlog("MSUBAq"); }
microVUf(void) mVU_MSUBAx() { mVU_FMAC15(SUB); mVUlog("MSUBAx"); }
microVUf(void) mVU_MSUBAy() { mVU_FMAC15(SUB); mVUlog("MSUBAy"); }
microVUf(void) mVU_MSUBAz() { mVU_FMAC15(SUB); mVUlog("MSUBAz"); }
microVUf(void) mVU_MSUBAw() { mVU_FMAC15(SUB); mVUlog("MSUBAw"); }
microVUf(void) mVU_MAX() { mVU_FMAC1(MAX); mVUlog("MAX"); }
microVUf(void) mVU_MAXi() { mVU_FMAC6(MAX); mVUlog("MAXi"); }
microVUf(void) mVU_MAXx() { mVU_FMAC3(MAX); mVUlog("MAXq"); }
microVUf(void) mVU_MAXy() { mVU_FMAC3(MAX); mVUlog("MAXy"); }
microVUf(void) mVU_MAXz() { mVU_FMAC3(MAX); mVUlog("MAXz"); }
microVUf(void) mVU_MAXw() { mVU_FMAC3(MAX); mVUlog("MAXw"); }
microVUf(void) mVU_MINI() { mVU_FMAC1(MIN); mVUlog("MINI"); }
microVUf(void) mVU_MINIi() { mVU_FMAC6(MIN); mVUlog("MINIi"); }
microVUf(void) mVU_MINIx() { mVU_FMAC3(MIN); mVUlog("MINIx"); }
microVUf(void) mVU_MINIy() { mVU_FMAC3(MIN); mVUlog("MINIy"); }
microVUf(void) mVU_MINIz() { mVU_FMAC3(MIN); mVUlog("MINIz"); }
microVUf(void) mVU_MINIw() { mVU_FMAC3(MIN); mVUlog("MINIw"); }
microVUf(void) mVU_OPMULA() { mVU_FMAC18(MUL); mVUlog("OPMULA"); }
microVUf(void) mVU_OPMSUB() { mVU_FMAC19(SUB); mVUlog("OPMSUB"); }
microVUf(void) mVU_NOP() { /*mVUlog("NOP");*/ }
microVUf(void) mVU_ADD() { mVU_FMAC1 (ADD, "ADD"); }
microVUf(void) mVU_ADDi() { mVU_FMAC6 (ADD, "ADDi"); }
microVUf(void) mVU_ADDq() { mVU_FMAC22(ADD, "ADDq"); }
microVUf(void) mVU_ADDx() { mVU_FMAC3 (ADD, "ADDx"); }
microVUf(void) mVU_ADDy() { mVU_FMAC3 (ADD, "ADDy"); }
microVUf(void) mVU_ADDz() { mVU_FMAC3 (ADD, "ADDz"); }
microVUf(void) mVU_ADDw() { mVU_FMAC3 (ADD, "ADDw"); }
microVUf(void) mVU_ADDA() { mVU_FMAC4 (ADD, "ADDA"); }
microVUf(void) mVU_ADDAi() { mVU_FMAC7 (ADD, "ADDAi"); }
microVUf(void) mVU_ADDAq() { mVU_FMAC23(ADD, "ADDAq"); }
microVUf(void) mVU_ADDAx() { mVU_FMAC5 (ADD, "ADDAx"); }
microVUf(void) mVU_ADDAy() { mVU_FMAC5 (ADD, "ADDAy"); }
microVUf(void) mVU_ADDAz() { mVU_FMAC5 (ADD, "ADDAz"); }
microVUf(void) mVU_ADDAw() { mVU_FMAC5 (ADD, "ADDAw"); }
microVUf(void) mVU_SUB() { mVU_FMAC1 (SUB, "SUB"); }
microVUf(void) mVU_SUBi() { mVU_FMAC6 (SUB, "SUBi"); }
microVUf(void) mVU_SUBq() { mVU_FMAC22(SUB, "SUBq"); }
microVUf(void) mVU_SUBx() { mVU_FMAC3 (SUB, "SUBx"); }
microVUf(void) mVU_SUBy() { mVU_FMAC3 (SUB, "SUBy"); }
microVUf(void) mVU_SUBz() { mVU_FMAC3 (SUB, "SUBz"); }
microVUf(void) mVU_SUBw() { mVU_FMAC3 (SUB, "SUBw"); }
microVUf(void) mVU_SUBA() { mVU_FMAC4 (SUB, "SUBA"); }
microVUf(void) mVU_SUBAi() { mVU_FMAC7 (SUB, "SUBAi"); }
microVUf(void) mVU_SUBAq() { mVU_FMAC23(SUB, "SUBAq"); }
microVUf(void) mVU_SUBAx() { mVU_FMAC5 (SUB, "SUBAx"); }
microVUf(void) mVU_SUBAy() { mVU_FMAC5 (SUB, "SUBAy"); }
microVUf(void) mVU_SUBAz() { mVU_FMAC5 (SUB, "SUBAz"); }
microVUf(void) mVU_SUBAw() { mVU_FMAC5 (SUB, "SUBAw"); }
microVUf(void) mVU_MUL() { mVU_FMAC1 (MUL, "MUL"); }
microVUf(void) mVU_MULi() { mVU_FMAC6 (MUL, "MULi"); }
microVUf(void) mVU_MULq() { mVU_FMAC22(MUL, "MULq"); }
microVUf(void) mVU_MULx() { mVU_FMAC3 (MUL, "MULx"); }
microVUf(void) mVU_MULy() { mVU_FMAC3 (MUL, "MULy"); }
microVUf(void) mVU_MULz() { mVU_FMAC3 (MUL, "MULz"); }
microVUf(void) mVU_MULw() { mVU_FMAC3 (MUL, "MULw"); }
microVUf(void) mVU_MULA() { mVU_FMAC4 (MUL, "MULA"); }
microVUf(void) mVU_MULAi() { mVU_FMAC7 (MUL, "MULAi"); }
microVUf(void) mVU_MULAq() { mVU_FMAC23(MUL, "MULAq"); }
microVUf(void) mVU_MULAx() { mVU_FMAC5 (MUL, "MULAx"); }
microVUf(void) mVU_MULAy() { mVU_FMAC5 (MUL, "MULAy"); }
microVUf(void) mVU_MULAz() { mVU_FMAC5 (MUL, "MULAz"); }
microVUf(void) mVU_MULAw() { mVU_FMAC5 (MUL, "MULAw"); }
microVUf(void) mVU_MADD() { mVU_FMAC8 (ADD, "MADD"); }
microVUf(void) mVU_MADDi() { mVU_FMAC12(ADD, "MADDi"); }
microVUf(void) mVU_MADDq() { mVU_FMAC24(ADD, "MADDq"); }
microVUf(void) mVU_MADDx() { mVU_FMAC10(ADD, "MADDx"); }
microVUf(void) mVU_MADDy() { mVU_FMAC10(ADD, "MADDy"); }
microVUf(void) mVU_MADDz() { mVU_FMAC10(ADD, "MADDz"); }
microVUf(void) mVU_MADDw() { mVU_FMAC10(ADD, "MADDw"); }
microVUf(void) mVU_MADDA() { mVU_FMAC14(ADD, "MADDA"); }
microVUf(void) mVU_MADDAi() { mVU_FMAC16(ADD, "MADDAi"); }
microVUf(void) mVU_MADDAq() { mVU_FMAC26(ADD, "MADDAq"); }
microVUf(void) mVU_MADDAx() { mVU_FMAC15(ADD, "MADDAx"); }
microVUf(void) mVU_MADDAy() { mVU_FMAC15(ADD, "MADDAy"); }
microVUf(void) mVU_MADDAz() { mVU_FMAC15(ADD, "MADDAz"); }
microVUf(void) mVU_MADDAw() { mVU_FMAC15(ADD, "MADDAw"); }
microVUf(void) mVU_MSUB() { mVU_FMAC9 (SUB, "MSUB"); }
microVUf(void) mVU_MSUBi() { mVU_FMAC13(SUB, "MSUBi"); }
microVUf(void) mVU_MSUBq() { mVU_FMAC25(SUB, "MSUBq"); }
microVUf(void) mVU_MSUBx() { mVU_FMAC11(SUB, "MSUBx"); }
microVUf(void) mVU_MSUBy() { mVU_FMAC11(SUB, "MSUBy"); }
microVUf(void) mVU_MSUBz() { mVU_FMAC11(SUB, "MSUBz"); }
microVUf(void) mVU_MSUBw() { mVU_FMAC11(SUB, "MSUBw"); }
microVUf(void) mVU_MSUBA() { mVU_FMAC14(SUB, "MSUBA"); }
microVUf(void) mVU_MSUBAi() { mVU_FMAC16(SUB, "MSUBAi"); }
microVUf(void) mVU_MSUBAq() { mVU_FMAC26(SUB, "MSUBAq"); }
microVUf(void) mVU_MSUBAx() { mVU_FMAC15(SUB, "MSUBAx"); }
microVUf(void) mVU_MSUBAy() { mVU_FMAC15(SUB, "MSUBAy"); }
microVUf(void) mVU_MSUBAz() { mVU_FMAC15(SUB, "MSUBAz"); }
microVUf(void) mVU_MSUBAw() { mVU_FMAC15(SUB, "MSUBAw"); }
microVUf(void) mVU_MAX() { mVU_FMAC1 (MAX, "MAX"); }
microVUf(void) mVU_MAXi() { mVU_FMAC6 (MAX, "MAXi"); }
microVUf(void) mVU_MAXx() { mVU_FMAC3 (MAX, "MAXq"); }
microVUf(void) mVU_MAXy() { mVU_FMAC3 (MAX, "MAXy"); }
microVUf(void) mVU_MAXz() { mVU_FMAC3 (MAX, "MAXz"); }
microVUf(void) mVU_MAXw() { mVU_FMAC3 (MAX, "MAXw"); }
microVUf(void) mVU_MINI() { mVU_FMAC1 (MIN, "MINI"); }
microVUf(void) mVU_MINIi() { mVU_FMAC6 (MIN, "MINIi"); }
microVUf(void) mVU_MINIx() { mVU_FMAC3 (MIN, "MINIx"); }
microVUf(void) mVU_MINIy() { mVU_FMAC3 (MIN, "MINIy"); }
microVUf(void) mVU_MINIz() { mVU_FMAC3 (MIN, "MINIz"); }
microVUf(void) mVU_MINIw() { mVU_FMAC3 (MIN, "MINIw"); }
microVUf(void) mVU_OPMULA() { mVU_FMAC18(MUL, "OPMULA"); }
microVUf(void) mVU_OPMSUB() { mVU_FMAC19(SUB, "OPMSUB"); }
microVUf(void) mVU_NOP() { pass3 { mVUlog("NOP"); } }
microVUq(void) mVU_FTOIx(uptr addr) {
microVU* mVU = mVUx;
if (!recPass) { mVUanalyzeFMAC2<vuIndex>(_Fs_, _Ft_); }
else {
pass1 { mVUanalyzeFMAC2<vuIndex>(_Fs_, _Ft_); }
pass2 {
int Fs, Ft;
mVUlog("FTOIx");
mVUallocFMAC2a<vuIndex>(Fs, Ft);
// Note: For help understanding this algorithm see recVUMI_FTOI_Saturate()
@ -557,16 +579,15 @@ microVUq(void) mVU_FTOIx(uptr addr) {
mVUallocFMAC2b<vuIndex>(Ft);
}
}
microVUf(void) mVU_FTOI0() { mVU_FTOIx<vuIndex, recPass>(0); }
microVUf(void) mVU_FTOI4() { mVU_FTOIx<vuIndex, recPass>((uptr)mVU_FTOI_4); }
microVUf(void) mVU_FTOI12() { mVU_FTOIx<vuIndex, recPass>((uptr)mVU_FTOI_12); }
microVUf(void) mVU_FTOI15() { mVU_FTOIx<vuIndex, recPass>((uptr)mVU_FTOI_15); }
microVUf(void) mVU_FTOI0() { mVU_FTOIx<vuIndex, recPass>((uptr)0); pass3 { mVUlog("FTOI0"); } }
microVUf(void) mVU_FTOI4() { mVU_FTOIx<vuIndex, recPass>((uptr)mVU_FTOI_4); pass3 { mVUlog("FTOI4"); } }
microVUf(void) mVU_FTOI12() { mVU_FTOIx<vuIndex, recPass>((uptr)mVU_FTOI_12); pass3 { mVUlog("FTOI12"); } }
microVUf(void) mVU_FTOI15() { mVU_FTOIx<vuIndex, recPass>((uptr)mVU_FTOI_15); pass3 { mVUlog("FTOI15"); } }
microVUq(void) mVU_ITOFx(uptr addr) {
microVU* mVU = mVUx;
if (!recPass) { mVUanalyzeFMAC2<vuIndex>(_Fs_, _Ft_); }
else {
pass1 { mVUanalyzeFMAC2<vuIndex>(_Fs_, _Ft_); }
pass2 {
int Fs, Ft;
mVUlog("ITOFx");
mVUallocFMAC2a<vuIndex>(Fs, Ft);
SSE2_CVTDQ2PS_XMM_to_XMM(Ft, Fs);
@ -576,16 +597,15 @@ microVUq(void) mVU_ITOFx(uptr addr) {
mVUallocFMAC2b<vuIndex>(Ft);
}
}
microVUf(void) mVU_ITOF0() { mVU_ITOFx<vuIndex, recPass>(0); }
microVUf(void) mVU_ITOF4() { mVU_ITOFx<vuIndex, recPass>((uptr)mVU_ITOF_4); }
microVUf(void) mVU_ITOF12() { mVU_ITOFx<vuIndex, recPass>((uptr)mVU_ITOF_12); }
microVUf(void) mVU_ITOF15() { mVU_ITOFx<vuIndex, recPass>((uptr)mVU_ITOF_15); }
microVUf(void) mVU_ITOF0() { mVU_ITOFx<vuIndex, recPass>((uptr)0); pass3 { mVUlog("ITOF0"); } }
microVUf(void) mVU_ITOF4() { mVU_ITOFx<vuIndex, recPass>((uptr)mVU_ITOF_4); pass3 { mVUlog("ITOF4"); } }
microVUf(void) mVU_ITOF12() { mVU_ITOFx<vuIndex, recPass>((uptr)mVU_ITOF_12); pass3 { mVUlog("ITOF12"); } }
microVUf(void) mVU_ITOF15() { mVU_ITOFx<vuIndex, recPass>((uptr)mVU_ITOF_15); pass3 { mVUlog("ITOF15"); } }
microVUf(void) mVU_CLIP() {
microVU* mVU = mVUx;
if (!recPass) { mVUanalyzeFMAC4<vuIndex>(_Fs_, _Ft_); mVUlog("clip broken"); }
else {
pass1 { mVUanalyzeFMAC4<vuIndex>(_Fs_, _Ft_); mVUprint("clip broken"); }
pass2 {
int Fs, Ft;
mVUlog("CLIP");
mVUallocFMAC17a<vuIndex>(Fs, Ft);
mVUallocCFLAGa<vuIndex>(gprT1, fpcInstance);
SHL32ItoR(gprT1, 6);
@ -613,5 +633,6 @@ microVUf(void) mVU_CLIP() {
mVUallocCFLAGb<vuIndex>(gprT1, fcInstance);
}
pass3 { mVUlog("CLIP"); }
}
#endif //PCSX2_MICROVU