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Debugger Assembler: BC1(t|f) 24 bit immediates to 16 bit immediates

This commit is contained in:
Ty 2025-02-21 11:59:21 -05:00 committed by Ty
parent 5dd36a7969
commit 4db23e6677
3 changed files with 12 additions and 8 deletions
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6
pcsx2/DebugTools/ExpressionParser.cpp
View File

@ -599,7 +599,11 @@ bool parsePostfixExpression(PostfixExpression& exp, IExpressionFunctions* funcs,
}
}
if (valueStack.size() != 1) return false;
if (valueStack.size() != 1)
{
error = TRANSLATE("ExpressionParser", "Invalid expression (Too many constants?)");
return false;
}
dest = valueStack[0];
return true;
}

6
pcsx2/DebugTools/MipsAssembler.cpp
View File

@ -637,14 +637,14 @@ bool CMipsInstruction::Validate()
immediate.value = (immediate.value >> 2) & 0x3FFFFFF;
} else if (Opcode.flags & MO_IPCR) // relative 16 bit value
{
int num = (immediate.value-RamPos-4);
const int num = (immediate.value-RamPos-4) >> 2;
if (num > 0x20000 || num < (-0x20000))
if (num > std::numeric_limits<short>::max() || num < std::numeric_limits<short>::min())
{
Logger::queueError(Logger::Error,L"Branch target %08X out of range",immediate.value);
return false;
}
immediate.value = num >> 2;
immediate.value = num;
}
int immediateBits = getImmediateBits(immediateType);

8
pcsx2/DebugTools/MipsAssemblerTables.cpp
View File

@ -596,10 +596,10 @@ const tMipsOpcode MipsOpcodes[] = {
// 10 | --- | --- | --- | --- | --- | --- | --- | --- | 10..17
// 11 | --- | --- | --- | --- | --- | --- | --- | --- | 18..1F
// hi |-------|-------|-------|-------|-------|-------|-------|-------|
{ "bc1f", "I", MIPS_COP1BC(0x00), MA_MIPS2, MO_IPCR|MO_DELAY|MO_NODELAYSLOT },
{ "bc1t", "I", MIPS_COP1BC(0x01), MA_MIPS2, MO_IPCR|MO_DELAY|MO_NODELAYSLOT },
{ "bc1fl", "I", MIPS_COP1BC(0x02), MA_MIPS2, MO_IPCR|MO_DELAY|MO_NODELAYSLOT },
{ "bc1tl", "I", MIPS_COP1BC(0x03), MA_MIPS2, MO_IPCR|MO_DELAY|MO_NODELAYSLOT },
{ "bc1f", "i", MIPS_COP1BC(0x00), MA_MIPS2, MO_IPCR|MO_DELAY|MO_NODELAYSLOT },
{ "bc1t", "i", MIPS_COP1BC(0x01), MA_MIPS2, MO_IPCR|MO_DELAY|MO_NODELAYSLOT },
{ "bc1fl", "i", MIPS_COP1BC(0x02), MA_MIPS2, MO_IPCR|MO_DELAY|MO_NODELAYSLOT },
{ "bc1tl", "i", MIPS_COP1BC(0x03), MA_MIPS2, MO_IPCR|MO_DELAY|MO_NODELAYSLOT },
// 31---------21------------------------------------------5--------0
// |= COP1S | | function|