mirror of https://github.com/PCSX2/pcsx2.git
cleaned up some code (knocked off 100+ lines in Alloc.inl), and implemented 'ESUM' opcode.
<drk||Razi>cotton2: write more helpful logs kthx ;p <cotton2>doesn't matter, no-one cares what i write since it doesn't effect anything for now <Krakatos>cotton, stop posting those useless commit comments XD <feal87>no no, please continue. they're fun, i look forward to read them <feal87>from time to time <feal87>:°D <cotton2>lol :D <Dwarg>Please spend more time making them more amusing. <drk||Razi>cotton2: it does matter <cotton2>dwarg: yeah i know! <Dwarg>drk||Raz: Why? They're useless for reversion testing <cotton2>i have to think of good stuff to write :O <drk||Razi>when the next vu coders (if any, ever ;p) want to look at your code .. and the history is full of crap <drk||Razi>that won't be much useful <drk||Razi>;p <cotton2>there won't be a next vu coder! <Dwarg>Comments in the actual code would be more useful, wouldn't they? <cotton2>my code is perfect! <drk||Razi>lol <cotton2>>.> <.< <cotton2>but seriously <cotton2>i don't think it can get better <cotton2>unless like <Dwarg>Rather than going back and comparing SVN comments to changes made way back when <cotton2>you want to support AVX <cotton2>or w/e intel's new SSE thing is called <feal87>and anyway AVX is like 3 years away <feal87>in that timeline pcsx2 i think will be stabilized <feal87>:°D <cotton2>yeah <drk||Razi>cotton2: just log kthx <drk||Razi>implemented y,x,z <drk||Razi>:> <cotton2>thats what the diffs are for! <feal87>and anyway really its useless for this stage <drk||Razi>yea i know <feal87>until microVU is active and used by PCSX2 <cotton2>i'm just implementing different opcodes though, its not like i'm chaning features <drk||Razi>you can tell anything from the code -- no comments or changelog needed.Right ? ;p <feal87>then every change should be documented for regression testing <cotton2>drk: yup! <cotton2>well <cotton2>its not like i'm changing stuff <cotton2>i'm just implementing things that havn't been coded <cotton2>so theres nothing to regress to <feal87>yep git-svn-id: http://pcsx2.googlecode.com/svn/trunk@742 96395faa-99c1-11dd-bbfe-3dabce05a288
This commit is contained in:
cottonvibes
parent
68ec2f25a8
commit
4620f4c5aa
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@ -36,14 +36,14 @@
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if (CHECK_VU_EXTRA_OVERFLOW) mVUclamp2<vuIndex>(reg, xmmT1, _X_Y_Z_W); \
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}
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#define getZeroSS(reg) { \
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#define getZero(reg) { \
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if (_W) { mVUloadReg<vuIndex>(reg, (uptr)&mVU->regs->VF[0].UL[0], _X_Y_Z_W); } \
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else { SSE_XORPS_XMM_to_XMM(reg, reg); } \
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}
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#define getZero(reg) { \
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if (_W) { mVUloadReg<vuIndex>(reg, (uptr)&mVU->regs->VF[0].UL[0], _X_Y_Z_W); } \
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else { SSE_XORPS_XMM_to_XMM(reg, reg); } \
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#define getReg6(reg, _reg_) { \
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if (!_reg_) { getZero(reg); } \
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else { getReg(reg, _reg_); } \
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}
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microVUt(void) mVUallocFMAC1a(int& Fd, int& Fs, int& Ft) {
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@ -51,26 +51,9 @@ microVUt(void) mVUallocFMAC1a(int& Fd, int& Fs, int& Ft) {
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Fs = xmmFs;
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Ft = xmmFt;
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Fd = xmmFs;
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if (_XYZW_SS) {
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if (!_Fs_) { getZeroSS(Fs); }
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else { getReg(Fs, _Fs_); }
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if (_Ft_ == _Fs_) { Ft = Fs; }
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else {
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if (!_Ft_) { getZeroSS(Ft); }
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else { getReg(Ft, _Ft_); }
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}
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}
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else {
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if (!_Fs_) { getZero(Fs); }
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else { getReg(Fs, _Fs_); }
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if (_Ft_ == _Fs_) { Ft = Fs; }
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else {
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if (!_Ft_) { getZero(Ft); }
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else { getReg(Ft, _Ft_); }
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}
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}
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getReg6(Fs, _Fs_);
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if (_Ft_ == _Fs_) { Ft = Fs; }
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else { getReg6(Ft, _Ft_); }
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}
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microVUt(void) mVUallocFMAC1b(int& Fd) {
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@ -88,14 +71,7 @@ microVUt(void) mVUallocFMAC2a(int& Fs, int& Ft) {
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microVU* mVU = mVUx;
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Fs = xmmFs;
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Ft = xmmFs;
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if (_XYZW_SS) {
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if (!_Fs_) { getZeroSS(Fs); }
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else { getReg(Fs, _Fs_); }
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}
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else {
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if (!_Fs_) { getZero(Fs); }
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else { getReg(Fs, _Fs_); }
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}
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getReg6(Fs, _Fs_);
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}
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microVUt(void) mVUallocFMAC2b(int& Ft) {
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@ -139,21 +115,15 @@ microVUt(void) mVUallocFMAC3a(int& Fd, int& Fs, int& Ft) {
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Ft = xmmFt;
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Fd = xmmFs;
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if (_XYZW_SS) {
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if (!_Fs_) { getZeroSS(Fs); }
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else { getReg(Fs, _Fs_); }
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getReg6(Fs, _Fs_);
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if ( (_Ft_ == _Fs_) && ((_X && _bc_x) || (_Y && _bc_y) || (_Z && _bc_w) || (_W && _bc_w)) ) {
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Ft = Fs;
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}
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else {
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if (!_Ft_) { getZero3SS(Ft); }
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else { getReg3SS(Ft, _Ft_); }
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}
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else if (!_Ft_) { getZero3SS(Ft); }
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else { getReg3SS(Ft, _Ft_); }
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}
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else {
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if (!_Fs_) { getZero(Fs); }
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else { getReg(Fs, _Fs_); }
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getReg6(Fs, _Fs_);
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if (!_Ft_) { getZero3(Ft); }
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else { getReg3(Ft, _Ft_); }
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}
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@ -188,24 +158,17 @@ microVUt(void) mVUallocFMAC4a(int& ACC, int& Fs, int& Ft) {
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Ft = xmmFt;
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getACC(ACC);
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if (_XYZW_SS && _X) {
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if (!_Fs_) { getZeroSS(Fs); }
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else { getReg(Fs, _Fs_); }
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getReg6(Fs, _Fs_);
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if (_Ft_ == _Fs_) { Ft = Fs; }
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else {
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if (!_Ft_) { getZeroSS(Ft); }
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else { getReg(Ft, _Ft_); }
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}
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else { getReg6(Ft, _Ft_); }
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}
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else {
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if (!_Fs_) { getZero4(Fs); }
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else { getReg4(Fs, _Fs_); }
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if (!_Fs_) { getZero4(Fs); }
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else { getReg4(Fs, _Fs_); }
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if (_Ft_ == _Fs_) { Ft = Fs; }
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else {
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if (!_Ft_) { getZero4(Ft); }
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else { getReg4(Ft, _Ft_); }
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}
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else if (!_Ft_) { getZero4(Ft); }
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else { getReg4(Ft, _Ft_); }
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}
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}
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@ -225,16 +188,10 @@ microVUt(void) mVUallocFMAC5a(int& ACC, int& Fs, int& Ft) {
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Ft = xmmFt;
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getACC(ACC);
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if (_XYZW_SS && _X) {
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if (!_Fs_) { getZeroSS(Fs); }
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else { getReg(Fs, _Fs_); }
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if ( (_Ft_ == _Fs_) && _bc_x) {
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Ft = Fs;
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}
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else {
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if (!_Ft_) { getZero3SS(Ft); }
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else { getReg3SS(Ft, _Ft_); }
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}
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getReg6(Fs, _Fs_);
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if ((_Ft_ == _Fs_) && _bc_x) { Ft = Fs; }
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else if (!_Ft_) { getZero3SS(Ft); }
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else { getReg3SS(Ft, _Ft_); }
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}
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else {
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if (!_Fs_) { getZero4(Fs); }
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@ -266,14 +223,7 @@ microVUt(void) mVUallocFMAC6a(int& Fd, int& Fs, int& Ft) {
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Ft = xmmFt;
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Fd = xmmFs;
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getIreg(Ft);
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if (_XYZW_SS) {
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if (!_Fs_) { getZeroSS(Fs); }
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else { getReg(Fs, _Fs_); }
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}
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else {
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if (!_Fs_) { getZero(Fs); }
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else { getReg(Fs, _Fs_); }
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}
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getReg6(Fs, _Fs_);
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}
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microVUt(void) mVUallocFMAC6b(int& Fd) {
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@ -290,14 +240,9 @@ microVUt(void) mVUallocFMAC7a(int& ACC, int& Fs, int& Ft) {
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Ft = xmmFt;
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getACC(ACC);
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getIreg(Ft);
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if (_XYZW_SS && _X) {
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if (!_Fs_) { getZeroSS(Fs); }
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else { getReg(Fs, _Fs_); }
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}
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else {
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if (!_Fs_) { getZero4(Fs); }
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else { getReg4(Fs, _Fs_); }
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}
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if (_XYZW_SS && _X) { getReg6(Fs, _Fs_); }
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else if (!_Fs_) { getZero4(Fs); }
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else { getReg4(Fs, _Fs_); }
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}
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microVUt(void) mVUallocFMAC7b(int& ACC, int& Fs) {
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@ -315,24 +260,17 @@ microVUt(void) mVUallocFMAC8a(int& Fd, int&ACC, int& Fs, int& Ft) {
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Fd = xmmFs;
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ACC = xmmACC0 + readACC;
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if (_XYZW_SS && _X) {
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if (!_Fs_) { getZeroSS(Fs); }
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else { getReg(Fs, _Fs_); }
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getReg6(Fs, _Fs_);
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if (_Ft_ == _Fs_) { Ft = Fs; }
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else {
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if (!_Ft_) { getZeroSS(Ft); }
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else { getReg(Ft, _Ft_); }
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}
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else { getReg6(Ft, _Ft_); }
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}
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else {
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if (!_Fs_) { getZero4(Fs); }
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else { getReg4(Fs, _Fs_); }
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if (!_Fs_) { getZero4(Fs); }
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else { getReg4(Fs, _Fs_); }
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if (_Ft_ == _Fs_) { Ft = Fs; }
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else {
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if (!_Ft_) { getZero4(Ft); }
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else { getReg4(Ft, _Ft_); }
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}
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else if (!_Ft_) { getZero4(Ft); }
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else { getReg4(Ft, _Ft_); }
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}
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}
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@ -355,24 +293,17 @@ microVUt(void) mVUallocFMAC9a(int& Fd, int&ACC, int& Fs, int& Ft) {
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ACC = xmmT1;
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SSE_MOVAPS_XMM_to_XMM(ACC, xmmACC0 + readACC);
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if (_XYZW_SS && _X) {
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if (!_Fs_) { getZeroSS(Fs); }
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else { getReg(Fs, _Fs_); }
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getReg6(Fs, _Fs_);
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if (_Ft_ == _Fs_) { Ft = Fs; }
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else {
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if (!_Ft_) { getZeroSS(Ft); }
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else { getReg(Ft, _Ft_); }
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}
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else { getReg6(Ft, _Ft_); }
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}
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else {
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if (!_Fs_) { getZero4(Fs); }
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else { getReg4(Fs, _Fs_); }
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if (!_Fs_) { getZero4(Fs); }
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else { getReg4(Fs, _Fs_); }
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if (_Ft_ == _Fs_) { Ft = Fs; }
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else {
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if (!_Ft_) { getZero4(Ft); }
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else { getReg4(Ft, _Ft_); }
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}
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else if (!_Ft_) { getZero4(Ft); }
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else { getReg4(Ft, _Ft_); }
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}
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}
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@ -394,16 +325,10 @@ microVUt(void) mVUallocFMAC10a(int& Fd, int& ACC, int& Fs, int& Ft) {
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Fd = xmmFs;
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ACC = xmmACC0 + readACC;
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if (_XYZW_SS && _X) {
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if (!_Fs_) { getZeroSS(Fs); }
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else { getReg(Fs, _Fs_); }
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if ( (_Ft_ == _Fs_) && _bc_x) {
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Ft = Fs;
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}
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else {
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if (!_Ft_) { getZero3SS(Ft); }
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else { getReg3SS(Ft, _Ft_); }
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}
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getReg6(Fs, _Fs_);
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if ( (_Ft_ == _Fs_) && _bc_x) { Ft = Fs; }
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else if (!_Ft_) { getZero3SS(Ft); }
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else { getReg3SS(Ft, _Ft_); }
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}
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else {
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if (!_Fs_) { getZero4(Fs); }
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@ -430,16 +355,10 @@ microVUt(void) mVUallocFMAC11a(int& Fd, int& ACC, int& Fs, int& Ft) {
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ACC = xmmT1;
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SSE_MOVAPS_XMM_to_XMM(ACC, xmmACC0 + readACC);
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if (_XYZW_SS && _X) {
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if (!_Fs_) { getZeroSS(Fs); }
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else { getReg(Fs, _Fs_); }
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if ( (_Ft_ == _Fs_) && _bc_x) {
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Ft = Fs;
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}
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else {
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if (!_Ft_) { getZero3SS(Ft); }
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else { getReg3SS(Ft, _Ft_); }
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}
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getReg6(Fs, _Fs_);
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if ( (_Ft_ == _Fs_) && _bc_x) { Ft = Fs; }
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else if (!_Ft_) { getZero3SS(Ft); }
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else { getReg3SS(Ft, _Ft_); }
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}
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else {
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if (!_Fs_) { getZero4(Fs); }
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@ -465,14 +384,9 @@ microVUt(void) mVUallocFMAC12a(int& Fd, int&ACC, int& Fs, int& Ft) {
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Fd = xmmFs;
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ACC = xmmACC0 + readACC;
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getIreg(Ft);
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if (_XYZW_SS && _X) {
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if (!_Fs_) { getZeroSS(Fs); }
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else { getReg(Fs, _Fs_); }
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}
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else {
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if (!_Fs_) { getZero4(Fs); }
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else { getReg4(Fs, _Fs_); }
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}
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if (_XYZW_SS && _X) { getReg6(Fs, _Fs_); }
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else if (!_Fs_) { getZero4(Fs); }
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else { getReg4(Fs, _Fs_); }
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}
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microVUt(void) mVUallocFMAC12b(int& Fd) {
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@ -491,14 +405,9 @@ microVUt(void) mVUallocFMAC13a(int& Fd, int&ACC, int& Fs, int& Ft) {
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ACC = xmmT1;
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SSE_MOVAPS_XMM_to_XMM(ACC, xmmACC0 + readACC);
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getIreg(Ft);
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if (_XYZW_SS && _X) {
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if (!_Fs_) { getZeroSS(Fs); }
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else { getReg(Fs, _Fs_); }
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}
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else {
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if (!_Fs_) { getZero4(Fs); }
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else { getReg4(Fs, _Fs_); }
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}
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if (_XYZW_SS && _X) { getReg6(Fs, _Fs_); }
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else if (!_Fs_) { getZero4(Fs); }
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else { getReg4(Fs, _Fs_); }
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}
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microVUt(void) mVUallocFMAC13b(int& Fd) {
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@ -516,24 +425,17 @@ microVUt(void) mVUallocFMAC14a(int& ACCw, int&ACCr, int& Fs, int& Ft) {
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Ft = xmmFt;
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ACCr = xmmACC0 + readACC;
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if (_XYZW_SS && _X) {
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if (!_Fs_) { getZeroSS(Fs); }
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else { getReg(Fs, _Fs_); }
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getReg6(Fs, _Fs_);
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if (_Ft_ == _Fs_) { Ft = Fs; }
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else {
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if (!_Ft_) { getZeroSS(Ft); }
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else { getReg(Ft, _Ft_); }
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}
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else { getReg6(Ft, _Ft_); }
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}
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else {
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if (!_Fs_) { getZero4(Fs); }
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else { getReg4(Fs, _Fs_); }
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if (!_Fs_) { getZero4(Fs); }
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else { getReg4(Fs, _Fs_); }
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if (_Ft_ == _Fs_) { Ft = Fs; }
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else {
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if (!_Ft_) { getZero4(Ft); }
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else { getReg4(Ft, _Ft_); }
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}
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else if (!_Ft_) { getZero4(Ft); }
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else { getReg4(Ft, _Ft_); }
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}
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}
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@ -570,16 +472,10 @@ microVUt(void) mVUallocFMAC16a(int& ACCw, int&ACCr, int& Fs, int& Ft) {
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Ft = xmmFt;
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ACCr = xmmACC0 + readACC;
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if (_XYZW_SS && _X) {
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if (!_Fs_) { getZeroSS(Fs); }
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else { getReg(Fs, _Fs_); }
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if ( (_Ft_ == _Fs_) && _bc_x) {
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Ft = Fs;
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}
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else {
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if (!_Ft_) { getZero3SS(Ft); }
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else { getReg3SS(Ft, _Ft_); }
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}
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getReg6(Fs, _Fs_);
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if ((_Ft_ == _Fs_) && _bc_x) { Ft = Fs; }
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else if (!_Ft_) { getZero3SS(Ft); }
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else { getReg3SS(Ft, _Ft_); }
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}
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else {
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if (!_Fs_) { getZero4(Fs); }
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|
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@ -669,14 +565,9 @@ microVUt(void) mVUallocFMAC20a(int& ACCw, int&ACCr, int& Fs, int& Ft) {
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Ft = xmmFt;
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ACCr = xmmACC0 + readACC;
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getIreg(Ft);
|
||||
if (_XYZW_SS && _X) {
|
||||
if (!_Fs_) { getZeroSS(Fs); }
|
||||
else { getReg(Fs, _Fs_); }
|
||||
}
|
||||
else {
|
||||
if (!_Fs_) { getZero4(Fs); }
|
||||
else { getReg4(Fs, _Fs_); }
|
||||
}
|
||||
if (_XYZW_SS && _X) { getReg6(Fs, _Fs_); }
|
||||
else if (!_Fs_) { getZero4(Fs); }
|
||||
else { getReg4(Fs, _Fs_); }
|
||||
}
|
||||
|
||||
microVUt(void) mVUallocFMAC20b(int& ACCw, int& Fs) {
|
||||
|
|
@ -712,14 +603,7 @@ microVUt(void) mVUallocFMAC22a(int& Fd, int& Fs, int& Ft) {
|
|||
Ft = xmmFt;
|
||||
Fd = xmmFs;
|
||||
getQreg(Ft);
|
||||
if (_XYZW_SS) {
|
||||
if (!_Fs_) { getZeroSS(Fs); }
|
||||
else { getReg(Fs, _Fs_); }
|
||||
}
|
||||
else {
|
||||
if (!_Fs_) { getZero(Fs); }
|
||||
else { getReg(Fs, _Fs_); }
|
||||
}
|
||||
getReg6(Fs, _Fs_);
|
||||
}
|
||||
|
||||
microVUt(void) mVUallocFMAC22b(int& Fd) {
|
||||
|
|
@ -736,21 +620,15 @@ microVUt(void) mVUallocFMAC23a(int& ACC, int& Fs, int& Ft) {
|
|||
Ft = xmmFt;
|
||||
getACC(ACC);
|
||||
getQreg(Ft);
|
||||
if (_XYZW_SS && _X) {
|
||||
if (!_Fs_) { getZeroSS(Fs); }
|
||||
else { getReg(Fs, _Fs_); }
|
||||
}
|
||||
else {
|
||||
if (!_Fs_) { getZero4(Fs); }
|
||||
else { getReg4(Fs, _Fs_); }
|
||||
}
|
||||
if (_XYZW_SS && _X) { getReg6(Fs, _Fs_); }
|
||||
else if (!_Fs_) { getZero4(Fs); }
|
||||
else { getReg4(Fs, _Fs_); }
|
||||
}
|
||||
|
||||
microVUt(void) mVUallocFMAC23b(int& ACC, int& Fs) {
|
||||
mVUallocFMAC4b<vuIndex>(ACC, Fs);
|
||||
}
|
||||
|
||||
|
||||
//------------------------------------------------------------------
|
||||
// FMAC24 - MADD FMAC Opcode Storing Result to Fd (Q Reg)
|
||||
//------------------------------------------------------------------
|
||||
|
|
@ -762,14 +640,9 @@ microVUt(void) mVUallocFMAC24a(int& Fd, int&ACC, int& Fs, int& Ft) {
|
|||
Fd = xmmFs;
|
||||
ACC = xmmACC0 + readACC;
|
||||
getQreg(Ft);
|
||||
if (_XYZW_SS && _X) {
|
||||
if (!_Fs_) { getZeroSS(Fs); }
|
||||
else { getReg(Fs, _Fs_); }
|
||||
}
|
||||
else {
|
||||
if (!_Fs_) { getZero4(Fs); }
|
||||
else { getReg4(Fs, _Fs_); }
|
||||
}
|
||||
if (_XYZW_SS && _X) { getReg6(Fs, _Fs_); }
|
||||
else if (!_Fs_) { getZero4(Fs); }
|
||||
else { getReg4(Fs, _Fs_); }
|
||||
}
|
||||
|
||||
microVUt(void) mVUallocFMAC24b(int& Fd) {
|
||||
|
|
@ -788,14 +661,9 @@ microVUt(void) mVUallocFMAC25a(int& Fd, int&ACC, int& Fs, int& Ft) {
|
|||
ACC = xmmT1;
|
||||
SSE_MOVAPS_XMM_to_XMM(ACC, xmmACC0 + readACC);
|
||||
getQreg(Ft);
|
||||
if (_XYZW_SS && _X) {
|
||||
if (!_Fs_) { getZeroSS(Fs); }
|
||||
else { getReg(Fs, _Fs_); }
|
||||
}
|
||||
else {
|
||||
if (!_Fs_) { getZero4(Fs); }
|
||||
else { getReg4(Fs, _Fs_); }
|
||||
}
|
||||
if (_XYZW_SS && _X) { getReg6(Fs, _Fs_); }
|
||||
else if (!_Fs_) { getZero4(Fs); }
|
||||
else { getReg4(Fs, _Fs_); }
|
||||
}
|
||||
|
||||
microVUt(void) mVUallocFMAC25b(int& Fd) {
|
||||
|
|
@ -813,14 +681,9 @@ microVUt(void) mVUallocFMAC26a(int& ACCw, int&ACCr, int& Fs, int& Ft) {
|
|||
Ft = xmmFt;
|
||||
ACCr = xmmACC0 + readACC;
|
||||
getQreg(Ft);
|
||||
if (_XYZW_SS && _X) {
|
||||
if (!_Fs_) { getZeroSS(Fs); }
|
||||
else { getReg(Fs, _Fs_); }
|
||||
}
|
||||
else {
|
||||
if (!_Fs_) { getZero4(Fs); }
|
||||
else { getReg4(Fs, _Fs_); }
|
||||
}
|
||||
if (_XYZW_SS && _X) { getReg6(Fs, _Fs_); }
|
||||
else if (!_Fs_) { getZero4(Fs); }
|
||||
else { getReg4(Fs, _Fs_); }
|
||||
}
|
||||
|
||||
microVUt(void) mVUallocFMAC26b(int& ACCw, int& Fs) {
|
||||
|
|
|
|||
|
|
@ -217,7 +217,20 @@ microVUf(void) mVU_ERSQRT() {}
|
|||
microVUf(void) mVU_ESADD() {}
|
||||
microVUf(void) mVU_ESIN() {}
|
||||
microVUf(void) mVU_ESQRT() {}
|
||||
microVUf(void) mVU_ESUM() {}
|
||||
microVUf(void) mVU_ESUM() {
|
||||
microVU* mVU = mVUx;
|
||||
if (recPass == 0) {}
|
||||
else {
|
||||
getReg6(xmmFs, _Fs_);
|
||||
SSE_SHUFPS_XMM_to_XMM(xmmPQ, xmmPQ, writeP ? 0x27 : 0xC6); // Flip xmmPQ to get Valid P instance
|
||||
SSE2_PSHUFD_XMM_to_XMM(xmmFt, xmmFs, 0x1b);
|
||||
SSE_ADDPS_XMM_to_XMM(xmmFs, xmmFt);
|
||||
SSE2_PSHUFD_XMM_to_XMM(xmmFt, xmmFs, 0x01);
|
||||
SSE_ADDSS_XMM_to_XMM(xmmFs, xmmFt);
|
||||
SSE_MOVSS_XMM_to_XMM(xmmPQ, xmmFs);
|
||||
SSE_SHUFPS_XMM_to_XMM(xmmPQ, xmmPQ, writeP ? 0x27 : 0xC6); // Flip back
|
||||
}
|
||||
}
|
||||
|
||||
microVUf(void) mVU_FCAND() {}
|
||||
microVUf(void) mVU_FCEQ() {}
|
||||
|
|
|
|||
|
|
@ -78,6 +78,7 @@ microVUt(void) mVUupdateFlags(int reg, int regT1, int regT2, int xyzw, bool modX
|
|||
// Helper Macros
|
||||
//------------------------------------------------------------------
|
||||
|
||||
// FMAC1 - Normal FMAC Opcodes
|
||||
#define mVU_FMAC1(operation) { \
|
||||
microVU* mVU = mVUx; \
|
||||
if (recPass == 0) {} \
|
||||
|
|
@ -91,7 +92,7 @@ microVUt(void) mVUupdateFlags(int reg, int regT1, int regT2, int xyzw, bool modX
|
|||
mVUallocFMAC1b<vuIndex>(Fd); \
|
||||
} \
|
||||
}
|
||||
|
||||
// FMAC3 - BC(xyzw) FMAC Opcodes
|
||||
#define mVU_FMAC3(operation) { \
|
||||
microVU* mVU = mVUx; \
|
||||
if (recPass == 0) {} \
|
||||
|
|
@ -105,7 +106,7 @@ microVUt(void) mVUupdateFlags(int reg, int regT1, int regT2, int xyzw, bool modX
|
|||
mVUallocFMAC3b<vuIndex>(Fd); \
|
||||
} \
|
||||
}
|
||||
|
||||
// FMAC4 - FMAC Opcodes Storing Result to ACC
|
||||
#define mVU_FMAC4(operation) { \
|
||||
microVU* mVU = mVUx; \
|
||||
if (recPass == 0) {} \
|
||||
|
|
@ -119,7 +120,7 @@ microVUt(void) mVUupdateFlags(int reg, int regT1, int regT2, int xyzw, bool modX
|
|||
mVUallocFMAC4b<vuIndex>(ACC, Fs); \
|
||||
} \
|
||||
}
|
||||
|
||||
// FMAC5 - FMAC BC(xyzw) Opcodes Storing Result to ACC
|
||||
#define mVU_FMAC5(operation) { \
|
||||
microVU* mVU = mVUx; \
|
||||
if (recPass == 0) {} \
|
||||
|
|
@ -133,7 +134,7 @@ microVUt(void) mVUupdateFlags(int reg, int regT1, int regT2, int xyzw, bool modX
|
|||
mVUallocFMAC5b<vuIndex>(ACC, Fs); \
|
||||
} \
|
||||
}
|
||||
|
||||
// FMAC6 - Normal FMAC Opcodes (I Reg)
|
||||
#define mVU_FMAC6(operation) { \
|
||||
microVU* mVU = mVUx; \
|
||||
if (recPass == 0) {} \
|
||||
|
|
@ -147,7 +148,7 @@ microVUt(void) mVUupdateFlags(int reg, int regT1, int regT2, int xyzw, bool modX
|
|||
mVUallocFMAC6b<vuIndex>(Fd); \
|
||||
} \
|
||||
}
|
||||
|
||||
// FMAC7 - FMAC Opcodes Storing Result to ACC (I Reg)
|
||||
#define mVU_FMAC7(operation) { \
|
||||
microVU* mVU = mVUx; \
|
||||
if (recPass == 0) {} \
|
||||
|
|
@ -161,7 +162,7 @@ microVUt(void) mVUupdateFlags(int reg, int regT1, int regT2, int xyzw, bool modX
|
|||
mVUallocFMAC7b<vuIndex>(ACC, Fs); \
|
||||
} \
|
||||
}
|
||||
|
||||
// FMAC8 - MADD FMAC Opcode Storing Result to Fd
|
||||
#define mVU_FMAC8(operation) { \
|
||||
microVU* mVU = mVUx; \
|
||||
if (recPass == 0) {} \
|
||||
|
|
@ -181,7 +182,7 @@ microVUt(void) mVUupdateFlags(int reg, int regT1, int regT2, int xyzw, bool modX
|
|||
mVUallocFMAC8b<vuIndex>(Fd); \
|
||||
} \
|
||||
}
|
||||
|
||||
// FMAC9 - MSUB FMAC Opcode Storing Result to Fd
|
||||
#define mVU_FMAC9(operation) { \
|
||||
microVU* mVU = mVUx; \
|
||||
if (recPass == 0) {} \
|
||||
|
|
@ -201,7 +202,7 @@ microVUt(void) mVUupdateFlags(int reg, int regT1, int regT2, int xyzw, bool modX
|
|||
mVUallocFMAC9b<vuIndex>(Fd); \
|
||||
} \
|
||||
}
|
||||
|
||||
// FMAC10 - MADD FMAC BC(xyzw) Opcode Storing Result to Fd
|
||||
#define mVU_FMAC10(operation) { \
|
||||
microVU* mVU = mVUx; \
|
||||
if (recPass == 0) {} \
|
||||
|
|
@ -221,7 +222,7 @@ microVUt(void) mVUupdateFlags(int reg, int regT1, int regT2, int xyzw, bool modX
|
|||
mVUallocFMAC10b<vuIndex>(Fd); \
|
||||
} \
|
||||
}
|
||||
|
||||
// FMAC11 - MSUB FMAC BC(xyzw) Opcode Storing Result to Fd
|
||||
#define mVU_FMAC11(operation) { \
|
||||
microVU* mVU = mVUx; \
|
||||
if (recPass == 0) {} \
|
||||
|
|
@ -241,7 +242,7 @@ microVUt(void) mVUupdateFlags(int reg, int regT1, int regT2, int xyzw, bool modX
|
|||
mVUallocFMAC11b<vuIndex>(Fd); \
|
||||
} \
|
||||
}
|
||||
|
||||
// FMAC12 - MADD FMAC Opcode Storing Result to Fd (I Reg)
|
||||
#define mVU_FMAC12(operation) { \
|
||||
microVU* mVU = mVUx; \
|
||||
if (recPass == 0) {} \
|
||||
|
|
@ -261,7 +262,7 @@ microVUt(void) mVUupdateFlags(int reg, int regT1, int regT2, int xyzw, bool modX
|
|||
mVUallocFMAC12b<vuIndex>(Fd); \
|
||||
} \
|
||||
}
|
||||
|
||||
// FMAC13 - MSUB FMAC Opcode Storing Result to Fd (I Reg)
|
||||
#define mVU_FMAC13(operation) { \
|
||||
microVU* mVU = mVUx; \
|
||||
if (recPass == 0) {} \
|
||||
|
|
@ -281,7 +282,7 @@ microVUt(void) mVUupdateFlags(int reg, int regT1, int regT2, int xyzw, bool modX
|
|||
mVUallocFMAC13b<vuIndex>(Fd); \
|
||||
} \
|
||||
}
|
||||
|
||||
// FMAC14 - MADDA FMAC Opcode
|
||||
#define mVU_FMAC14(operation) { \
|
||||
microVU* mVU = mVUx; \
|
||||
if (recPass == 0) {} \
|
||||
|
|
@ -301,7 +302,7 @@ microVUt(void) mVUupdateFlags(int reg, int regT1, int regT2, int xyzw, bool modX
|
|||
mVUallocFMAC14b<vuIndex>(ACCw, Fs); \
|
||||
} \
|
||||
}
|
||||
|
||||
// FMAC15 - MSUBA FMAC Opcode
|
||||
#define mVU_FMAC15(operation) { \
|
||||
microVU* mVU = mVUx; \
|
||||
if (recPass == 0) {} \
|
||||
|
|
@ -321,7 +322,7 @@ microVUt(void) mVUupdateFlags(int reg, int regT1, int regT2, int xyzw, bool modX
|
|||
mVUallocFMAC15b<vuIndex>(ACCw, ACCr); \
|
||||
} \
|
||||
}
|
||||
|
||||
// FMAC16 - MADDA BC(xyzw) FMAC Opcode
|
||||
#define mVU_FMAC16(operation) { \
|
||||
microVU* mVU = mVUx; \
|
||||
if (recPass == 0) {} \
|
||||
|
|
@ -341,7 +342,7 @@ microVUt(void) mVUupdateFlags(int reg, int regT1, int regT2, int xyzw, bool modX
|
|||
mVUallocFMAC16b<vuIndex>(ACCw, Fs); \
|
||||
} \
|
||||
}
|
||||
|
||||
// FMAC17 - MSUBA BC(xyzw) FMAC Opcode
|
||||
#define mVU_FMAC17(operation) { \
|
||||
microVU* mVU = mVUx; \
|
||||
if (recPass == 0) {} \
|
||||
|
|
@ -361,7 +362,7 @@ microVUt(void) mVUupdateFlags(int reg, int regT1, int regT2, int xyzw, bool modX
|
|||
mVUallocFMAC17b<vuIndex>(ACCw, ACCr); \
|
||||
} \
|
||||
}
|
||||
|
||||
// FMAC18 - OPMULA FMAC Opcode
|
||||
#define mVU_FMAC18(operation) { \
|
||||
microVU* mVU = mVUx; \
|
||||
if (recPass == 0) {} \
|
||||
|
|
@ -374,7 +375,7 @@ microVUt(void) mVUupdateFlags(int reg, int regT1, int regT2, int xyzw, bool modX
|
|||
mVUallocFMAC18b<vuIndex>(ACC, Fs); \
|
||||
} \
|
||||
}
|
||||
|
||||
// FMAC19 - OPMULA FMAC Opcode
|
||||
#define mVU_FMAC19(operation) { \
|
||||
microVU* mVU = mVUx; \
|
||||
if (recPass == 0) {} \
|
||||
|
|
@ -388,7 +389,7 @@ microVUt(void) mVUupdateFlags(int reg, int regT1, int regT2, int xyzw, bool modX
|
|||
mVUallocFMAC19b<vuIndex>(Fd); \
|
||||
} \
|
||||
}
|
||||
|
||||
// FMAC20 - MADDA FMAC Opcode (I Reg)
|
||||
#define mVU_FMAC20(operation) { \
|
||||
microVU* mVU = mVUx; \
|
||||
if (recPass == 0) {} \
|
||||
|
|
@ -408,7 +409,7 @@ microVUt(void) mVUupdateFlags(int reg, int regT1, int regT2, int xyzw, bool modX
|
|||
mVUallocFMAC20b<vuIndex>(ACCw, Fs); \
|
||||
} \
|
||||
}
|
||||
|
||||
// FMAC21 - MSUBA FMAC Opcode (I Reg)
|
||||
#define mVU_FMAC21(operation) { \
|
||||
microVU* mVU = mVUx; \
|
||||
if (recPass == 0) {} \
|
||||
|
|
@ -428,7 +429,7 @@ microVUt(void) mVUupdateFlags(int reg, int regT1, int regT2, int xyzw, bool modX
|
|||
mVUallocFMAC21b<vuIndex>(ACCw, ACCr); \
|
||||
} \
|
||||
}
|
||||
|
||||
// FMAC22 - Normal FMAC Opcodes (Q Reg)
|
||||
#define mVU_FMAC22(operation) { \
|
||||
microVU* mVU = mVUx; \
|
||||
if (recPass == 0) {} \
|
||||
|
|
@ -442,7 +443,7 @@ microVUt(void) mVUupdateFlags(int reg, int regT1, int regT2, int xyzw, bool modX
|
|||
mVUallocFMAC22b<vuIndex>(Fd); \
|
||||
} \
|
||||
}
|
||||
|
||||
// FMAC23 - FMAC Opcodes Storing Result to ACC (Q Reg)
|
||||
#define mVU_FMAC23(operation) { \
|
||||
microVU* mVU = mVUx; \
|
||||
if (recPass == 0) {} \
|
||||
|
|
@ -456,7 +457,7 @@ microVUt(void) mVUupdateFlags(int reg, int regT1, int regT2, int xyzw, bool modX
|
|||
mVUallocFMAC23b<vuIndex>(ACC, Fs); \
|
||||
} \
|
||||
}
|
||||
|
||||
// FMAC24 - MADD FMAC Opcode Storing Result to Fd (Q Reg)
|
||||
#define mVU_FMAC24(operation) { \
|
||||
microVU* mVU = mVUx; \
|
||||
if (recPass == 0) {} \
|
||||
|
|
@ -476,7 +477,7 @@ microVUt(void) mVUupdateFlags(int reg, int regT1, int regT2, int xyzw, bool modX
|
|||
mVUallocFMAC24b<vuIndex>(Fd); \
|
||||
} \
|
||||
}
|
||||
|
||||
// FMAC25 - MSUB FMAC Opcode Storing Result to Fd (Q Reg)
|
||||
#define mVU_FMAC25(operation) { \
|
||||
microVU* mVU = mVUx; \
|
||||
if (recPass == 0) {} \
|
||||
|
|
@ -496,7 +497,7 @@ microVUt(void) mVUupdateFlags(int reg, int regT1, int regT2, int xyzw, bool modX
|
|||
mVUallocFMAC25b<vuIndex>(Fd); \
|
||||
} \
|
||||
}
|
||||
|
||||
// FMAC26 - MADDA FMAC Opcode (Q Reg)
|
||||
#define mVU_FMAC26(operation) { \
|
||||
microVU* mVU = mVUx; \
|
||||
if (recPass == 0) {} \
|
||||
|
|
@ -516,7 +517,7 @@ microVUt(void) mVUupdateFlags(int reg, int regT1, int regT2, int xyzw, bool modX
|
|||
mVUallocFMAC26b<vuIndex>(ACCw, Fs); \
|
||||
} \
|
||||
}
|
||||
|
||||
// FMAC27 - MSUBA FMAC Opcode (Q Reg)
|
||||
#define mVU_FMAC27(operation) { \
|
||||
microVU* mVU = mVUx; \
|
||||
if (recPass == 0) {} \
|
||||
|
|
|
|||
Loading…
Reference in New Issue